| # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s --verify-machineinstrs -o - | FileCheck %s |
| |
| # CHECK: name: non_loop |
| # CHECK: bb.0.entry: |
| # CHECK: tBcc %bb.2, 3 |
| # CHECK: bb.1.not.preheader: |
| # CHECK: $lr = t2SUBri killed renamable $lr, 0, 14 |
| # CHECK: tBcc %bb.4, 0 |
| # CHECK: tB %bb.2 |
| # CHECK: bb.3.while.body: |
| # CHECK: t2CMPri renamable $lr, 0, 14 |
| # CHECK: tBcc %bb.3, 1 |
| # CHECK: tB %bb.4 |
| # CHECK: bb.4.while.end: |
| |
| --- | |
| target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" |
| target triple = "thumbv8.1m.main" |
| |
| define void @non_loop(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) { |
| entry: |
| %cmp = icmp ugt i32 %N, 2 |
| br i1 %cmp, label %not.preheader, label %while.body.preheader |
| |
| not.preheader: ; preds = %entry |
| %test = call i1 @llvm.test.set.loop.iterations.i32(i32 %N) |
| br i1 %test, label %while.body.preheader, label %while.end |
| |
| while.body.preheader: ; preds = %not.preheader, %entry |
| %scevgep = getelementptr i16, i16* %a, i32 -1 |
| %scevgep3 = getelementptr i16, i16* %b, i32 -1 |
| br label %while.body |
| |
| while.body: ; preds = %while.body, %while.body.preheader |
| %lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ] |
| %lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ] |
| %count = phi i32 [ %count.next, %while.body ], [ %N, %while.body.preheader ] |
| %scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1 |
| %scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1 |
| %load = load i16, i16* %scevgep4, align 2 |
| store i16 %load, i16* %scevgep7, align 2 |
| %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1) |
| %cmp1 = icmp ne i32 %count.next, 0 |
| %scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1 |
| %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1 |
| br i1 %cmp1, label %while.body, label %while.end |
| |
| while.end: ; preds = %while.body, %not.preheader |
| ret void |
| } |
| |
| declare i1 @llvm.test.set.loop.iterations.i32(i32) #0 |
| declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 |
| declare void @llvm.stackprotector(i8*, i8**) #1 |
| |
| attributes #0 = { noduplicate nounwind } |
| attributes #1 = { nounwind } |
| |
| ... |
| --- |
| name: non_loop |
| alignment: 2 |
| exposesReturnsTwice: false |
| legalized: false |
| regBankSelected: false |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| hasWinCFI: false |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| isFrameAddressTaken: false |
| isReturnAddressTaken: false |
| hasStackMap: false |
| hasPatchPoint: false |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| adjustsStack: false |
| hasCalls: false |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| hasOpaqueSPAdjustment: false |
| hasVAStart: false |
| hasMustTailInVarArgFunc: false |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| bb.0.entry: |
| successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| $lr = tMOVr $r2, 14, $noreg |
| tCMPi8 killed $r2, 3, 14, $noreg, implicit-def $cpsr |
| tBcc %bb.2, 3, killed $cpsr |
| |
| bb.1.not.preheader: |
| successors: %bb.2(0x40000000), %bb.4(0x40000000) |
| liveins: $lr, $r0, $r1 |
| |
| $lr = t2WhileLoopStartLR killed renamable $lr, %bb.4, implicit-def dead $cpsr |
| tB %bb.2, 14, $noreg |
| |
| bb.2.while.body.preheader: |
| successors: %bb.3(0x80000000) |
| liveins: $lr, $r0, $r1 |
| |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg |
| renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg |
| |
| bb.3.while.body: |
| successors: %bb.3(0x7c000000), %bb.4(0x04000000) |
| liveins: $lr, $r0, $r1 |
| |
| renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load (s16) from %ir.scevgep4) |
| early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store (s16) into %ir.scevgep7) |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr |
| tB %bb.4, 14, $noreg |
| |
| bb.4.while.end: |
| tPOP_RET 14, $noreg, def $r7, def $pc |
| |
| ... |