| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s |
| |
| # Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE. |
| --- |
| name: f |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: f |
| ; CHECK: liveins: $vgpr0, $vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: undef %2.sub0:vreg_64 = COPY $vgpr0 |
| ; CHECK-NEXT: %2.sub1:vreg_64 = COPY $vgpr1 |
| ; CHECK-NEXT: $vgpr2_vgpr3 = COPY %2 |
| ; CHECK-NEXT: S_NOP 0, implicit $vgpr2_vgpr3 |
| %0:vgpr_32 = COPY $vgpr0 |
| %1:vgpr_32 = COPY $vgpr1 |
| %35:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| $vgpr2_vgpr3 = COPY %35 |
| S_NOP 0, implicit $vgpr2_vgpr3 |
| ... |
