llvm/test/CodeGen/AMDGPU/hazard-pseudo-machineinstrs.mir

# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck -check-prefix=GCN %s

# WAVE_BARRIER and SI_MASKED_UNREACHABLE are not really instructions.
# To fix the hazard (m0 def followed by V_INTERP), the scheduler
# should move another instruction into the slot.
---
# CHECK-LABEL: name: hazard_wave_barrier
# CHECK-LABEL: bb.0:
# GCN: $m0 = S_MOV_B32 killed renamable $sgpr0
# GCN-NEXT: WAVE_BARRIER
# GCN-NEXT: S_MOV_B32 0
# GCN-NEXT: V_INTERP_MOV_F32
name: hazard_wave_barrier
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr0

    $m0 = S_MOV_B32 killed renamable $sgpr0
    WAVE_BARRIER
    renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $mode, implicit $m0, implicit $exec
    renamable $sgpr1 = S_MOV_B32 0
    S_ENDPGM 0

...
# GCN-LABEL: name: hazard-masked-unreachable
# CHECK-LABEL: bb.0:
# GCN: $m0 = S_MOV_B32 killed renamable $sgpr0
# GCN-NEXT: SI_MASKED_UNREACHABLE
# GCN-NEXT: S_MOV_B32 0
# GCN-NEXT: V_INTERP_MOV_F32
---
name: hazard-masked-unreachable
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr0

    $m0 = S_MOV_B32 killed renamable $sgpr0
    SI_MASKED_UNREACHABLE
    renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $mode, implicit $m0, implicit $exec
    renamable $sgpr1 = S_MOV_B32 0
  bb.1:
    S_ENDPGM 0
...