llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amdpal -mcpu=gfx1200 -run-pass=legalizer %s -o - | FileCheck %s

---
name: test_struct
body: |
  bb.1.entry:

    ; CHECK-LABEL: name: test_struct
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<3 x s32>)
    ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
    ; CHECK-NEXT: $vgpr1 = COPY [[UV]](s32)
    ; CHECK-NEXT: $vgpr2 = COPY [[UV1]](s32)
    ; CHECK-NEXT: $vgpr3 = COPY [[UV2]](s32)
    ; CHECK-NEXT: $vgpr4_vgpr5 = COPY [[DEF2]](s64)
    ; CHECK-NEXT: $vgpr6 = COPY [[DEF3]](<2 x s16>)
    ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
    %0:_(s32), %1:_(<3 x s32>), %2:_(s64), %3:_(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.dead)

    %4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %1(<3 x s32>)
    $vgpr0 = COPY %0(s32)
    $vgpr1 = COPY %4(s32)
    $vgpr2 = COPY %5(s32)
    $vgpr3 = COPY %6(s32)
    $vgpr4_vgpr5 = COPY %2(s64)
    $vgpr6 = COPY %3(<2 x s16>)
    SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
...