llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-- -run-pass=instruction-select -o - %s | FileCheck %s

# Checks MI Flags are preserved on selected instructions.

---
name:            s_or_i32_disjoint
tracksRegLiveness: true
regBankSelected: true
legalized: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: s_or_i32_disjoint
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = disjoint S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
    ; CHECK-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s32) = disjoint G_OR %0, %1
    $sgpr0 = COPY %2
    SI_RETURN_TO_EPILOG implicit $sgpr0
...