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llvm / llvm-project / c9998ec145972714d581e19fd1c9cb276b836387 / . / llvm / test / CodeGen / X86 / vector-interleaved-load-i32-stride-2.ll
blob: f39e643368df3551ae122cdcfa1e381e710fda31 [file] [log] [blame]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,FALLBACK0
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1,AVX1-ONLY,FALLBACK1
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX1,AVX2,AVX2-ONLY,AVX2-SLOW,FALLBACK2
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX1,AVX2,AVX2-ONLY,AVX2-FAST,FALLBACK3
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX1,AVX2,AVX2-ONLY,AVX2-FAST-PERLANE,FALLBACK4
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512F,AVX512F-SLOW,AVX512F-ONLY-SLOW,FALLBACK5
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512F,AVX512F-FAST,AVX512F-ONLY-FAST,FALLBACK6
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512F,AVX512F-SLOW,AVX512DQ-SLOW,FALLBACK7
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512F,AVX512F-FAST,AVX512DQ-FAST,FALLBACK8
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512BW,AVX512BW-SLOW,AVX512BW-ONLY-SLOW,FALLBACK9
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512bw,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512BW,AVX512BW-FAST,AVX512BW-ONLY-FAST,FALLBACK10
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512BW,AVX512BW-SLOW,AVX512DQBW-SLOW,FALLBACK11
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq,+avx512bw,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX512,AVX512BW,AVX512BW-FAST,AVX512DQBW-FAST,FALLBACK12
; These patterns are produced by LoopVectorizer for interleaved loads.
define void @load_i32_stride2_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
; SSE-LABEL: load_i32_stride2_vf2:
; SSE: # %bb.0:
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,2,2,3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
; SSE-NEXT: movq %xmm1, (%rsi)
; SSE-NEXT: movq %xmm0, (%rdx)
; SSE-NEXT: retq
;
; AVX-LABEL: load_i32_stride2_vf2:
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm0
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm0[0,2,2,3]
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3,2,3]
; AVX-NEXT: vmovlps %xmm1, (%rsi)
; AVX-NEXT: vmovlps %xmm0, (%rdx)
; AVX-NEXT: retq
%wide.vec = load <4 x i32>, ptr %in.vec, align 64
%strided.vec0 = shufflevector <4 x i32> %wide.vec, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%strided.vec1 = shufflevector <4 x i32> %wide.vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
store <2 x i32> %strided.vec0, ptr %out.vec0, align 64
store <2 x i32> %strided.vec1, ptr %out.vec1, align 64
ret void
}
define void @load_i32_stride2_vf4(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
; SSE-LABEL: load_i32_stride2_vf4:
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: movaps 16(%rdi), %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
; SSE-NEXT: movaps %xmm2, (%rsi)
; SSE-NEXT: movaps %xmm0, (%rdx)
; SSE-NEXT: retq
;
; AVX1-LABEL: load_i32_stride2_vf4:
; AVX1: # %bb.0:
; AVX1-NEXT: vmovaps (%rdi), %xmm0
; AVX1-NEXT: vmovaps 16(%rdi), %xmm1
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,2],xmm1[0,2]
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
; AVX1-NEXT: vmovaps %xmm2, (%rsi)
; AVX1-NEXT: vmovaps %xmm0, (%rdx)
; AVX1-NEXT: retq
;
; AVX512-LABEL: load_i32_stride2_vf4:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa (%rdi), %ymm0
; AVX512-NEXT: vmovaps (%rdi), %xmm1
; AVX512-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3],mem[1,3]
; AVX512-NEXT: vpmovqd %ymm0, (%rsi)
; AVX512-NEXT: vmovaps %xmm1, (%rdx)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%wide.vec = load <8 x i32>, ptr %in.vec, align 64
%strided.vec0 = shufflevector <8 x i32> %wide.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%strided.vec1 = shufflevector <8 x i32> %wide.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
store <4 x i32> %strided.vec0, ptr %out.vec0, align 64
store <4 x i32> %strided.vec1, ptr %out.vec1, align 64
ret void
}
define void @load_i32_stride2_vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
; SSE-LABEL: load_i32_stride2_vf8:
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: movaps 16(%rdi), %xmm1
; SSE-NEXT: movaps 32(%rdi), %xmm2
; SSE-NEXT: movaps 48(%rdi), %xmm3
; SSE-NEXT: movaps %xmm2, %xmm4
; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm3[0,2]
; SSE-NEXT: movaps %xmm0, %xmm5
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm1[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
; SSE-NEXT: movaps %xmm5, (%rsi)
; SSE-NEXT: movaps %xmm4, 16(%rsi)
; SSE-NEXT: movaps %xmm0, (%rdx)
; SSE-NEXT: movaps %xmm2, 16(%rdx)
; SSE-NEXT: retq
;
; AVX1-ONLY-LABEL: load_i32_stride2_vf8:
; AVX1-ONLY: # %bb.0:
; AVX1-ONLY-NEXT: vmovaps (%rdi), %ymm0
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 32(%rdi), %ymm0, %ymm0
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm2 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX1-ONLY-NEXT: vmovaps %ymm2, (%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm0, (%rdx)
; AVX1-ONLY-NEXT: vzeroupper
; AVX1-ONLY-NEXT: retq
;
; AVX2-ONLY-LABEL: load_i32_stride2_vf8:
; AVX2-ONLY: # %bb.0:
; AVX2-ONLY-NEXT: vmovaps (%rdi), %ymm0
; AVX2-ONLY-NEXT: vmovaps 32(%rdi), %ymm1
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm2 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm2, (%rsi)
; AVX2-ONLY-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-ONLY-NEXT: vzeroupper
; AVX2-ONLY-NEXT: retq
;
; AVX512F-SLOW-LABEL: load_i32_stride2_vf8:
; AVX512F-SLOW: # %bb.0:
; AVX512F-SLOW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512F-SLOW-NEXT: vmovaps (%rdi), %ymm1
; AVX512F-SLOW-NEXT: vshufps {{.*#+}} ymm1 = ymm1[1,3],mem[1,3],ymm1[5,7],mem[5,7]
; AVX512F-SLOW-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,1,3]
; AVX512F-SLOW-NEXT: vpmovqd %zmm0, (%rsi)
; AVX512F-SLOW-NEXT: vmovaps %ymm1, (%rdx)
; AVX512F-SLOW-NEXT: vzeroupper
; AVX512F-SLOW-NEXT: retq
;
; AVX512F-FAST-LABEL: load_i32_stride2_vf8:
; AVX512F-FAST: # %bb.0:
; AVX512F-FAST-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512F-FAST-NEXT: vmovdqa (%rdi), %ymm1
; AVX512F-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [1,3,5,7,9,11,13,15]
; AVX512F-FAST-NEXT: vpermi2d 32(%rdi), %ymm1, %ymm2
; AVX512F-FAST-NEXT: vpmovqd %zmm0, (%rsi)
; AVX512F-FAST-NEXT: vmovdqa %ymm2, (%rdx)
; AVX512F-FAST-NEXT: vzeroupper
; AVX512F-FAST-NEXT: retq
;
; AVX512BW-SLOW-LABEL: load_i32_stride2_vf8:
; AVX512BW-SLOW: # %bb.0:
; AVX512BW-SLOW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-SLOW-NEXT: vmovaps (%rdi), %ymm1
; AVX512BW-SLOW-NEXT: vshufps {{.*#+}} ymm1 = ymm1[1,3],mem[1,3],ymm1[5,7],mem[5,7]
; AVX512BW-SLOW-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,1,3]
; AVX512BW-SLOW-NEXT: vpmovqd %zmm0, (%rsi)
; AVX512BW-SLOW-NEXT: vmovaps %ymm1, (%rdx)
; AVX512BW-SLOW-NEXT: vzeroupper
; AVX512BW-SLOW-NEXT: retq
;
; AVX512BW-FAST-LABEL: load_i32_stride2_vf8:
; AVX512BW-FAST: # %bb.0:
; AVX512BW-FAST-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-FAST-NEXT: vmovdqa (%rdi), %ymm1
; AVX512BW-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [1,3,5,7,9,11,13,15]
; AVX512BW-FAST-NEXT: vpermi2d 32(%rdi), %ymm1, %ymm2
; AVX512BW-FAST-NEXT: vpmovqd %zmm0, (%rsi)
; AVX512BW-FAST-NEXT: vmovdqa %ymm2, (%rdx)
; AVX512BW-FAST-NEXT: vzeroupper
; AVX512BW-FAST-NEXT: retq
%wide.vec = load <16 x i32>, ptr %in.vec, align 64
%strided.vec0 = shufflevector <16 x i32> %wide.vec, <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%strided.vec1 = shufflevector <16 x i32> %wide.vec, <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
store <8 x i32> %strided.vec0, ptr %out.vec0, align 64
store <8 x i32> %strided.vec1, ptr %out.vec1, align 64
ret void
}
define void @load_i32_stride2_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
; SSE-LABEL: load_i32_stride2_vf16:
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: movaps 16(%rdi), %xmm1
; SSE-NEXT: movaps 32(%rdi), %xmm2
; SSE-NEXT: movaps 48(%rdi), %xmm3
; SSE-NEXT: movaps 112(%rdi), %xmm4
; SSE-NEXT: movaps 96(%rdi), %xmm5
; SSE-NEXT: movaps 80(%rdi), %xmm6
; SSE-NEXT: movaps 64(%rdi), %xmm7
; SSE-NEXT: movaps %xmm7, %xmm8
; SSE-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,2],xmm6[0,2]
; SSE-NEXT: movaps %xmm5, %xmm9
; SSE-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm4[0,2]
; SSE-NEXT: movaps %xmm0, %xmm10
; SSE-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm1[0,2]
; SSE-NEXT: movaps %xmm2, %xmm11
; SSE-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,2],xmm3[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,3],xmm6[1,3]
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,3],xmm4[1,3]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
; SSE-NEXT: movaps %xmm11, 16(%rsi)
; SSE-NEXT: movaps %xmm10, (%rsi)
; SSE-NEXT: movaps %xmm9, 48(%rsi)
; SSE-NEXT: movaps %xmm8, 32(%rsi)
; SSE-NEXT: movaps %xmm2, 16(%rdx)
; SSE-NEXT: movaps %xmm0, (%rdx)
; SSE-NEXT: movaps %xmm5, 48(%rdx)
; SSE-NEXT: movaps %xmm7, 32(%rdx)
; SSE-NEXT: retq
;
; AVX1-ONLY-LABEL: load_i32_stride2_vf16:
; AVX1-ONLY: # %bb.0:
; AVX1-ONLY-NEXT: vmovaps (%rdi), %ymm0
; AVX1-ONLY-NEXT: vmovaps 64(%rdi), %ymm1
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm1[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 96(%rdi), %ymm1, %ymm1
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm3 = ymm1[0,2],ymm2[0,2],ymm1[4,6],ymm2[4,6]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm4 = ymm0[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 32(%rdi), %ymm0, %ymm0
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm5 = ymm0[0,2],ymm4[0,2],ymm0[4,6],ymm4[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm1 = ymm1[1,3],ymm2[1,3],ymm1[5,7],ymm2[5,7]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm4[1,3],ymm0[5,7],ymm4[5,7]
; AVX1-ONLY-NEXT: vmovaps %ymm5, (%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm3, 32(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm0, (%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm1, 32(%rdx)
; AVX1-ONLY-NEXT: vzeroupper
; AVX1-ONLY-NEXT: retq
;
; AVX2-ONLY-LABEL: load_i32_stride2_vf16:
; AVX2-ONLY: # %bb.0:
; AVX2-ONLY-NEXT: vmovaps (%rdi), %ymm0
; AVX2-ONLY-NEXT: vmovaps 32(%rdi), %ymm1
; AVX2-ONLY-NEXT: vmovaps 64(%rdi), %ymm2
; AVX2-ONLY-NEXT: vmovaps 96(%rdi), %ymm3
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm4 = ymm2[0,2],ymm3[0,2],ymm2[4,6],ymm3[4,6]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm4 = ymm4[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm5 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm5 = ymm5[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm2 = ymm2[1,3],ymm3[1,3],ymm2[5,7],ymm3[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm5, (%rsi)
; AVX2-ONLY-NEXT: vmovaps %ymm4, 32(%rsi)
; AVX2-ONLY-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-ONLY-NEXT: vmovaps %ymm2, 32(%rdx)
; AVX2-ONLY-NEXT: vzeroupper
; AVX2-ONLY-NEXT: retq
;
; AVX512-LABEL: load_i32_stride2_vf16:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512-NEXT: vmovdqa64 64(%rdi), %zmm1
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30]
; AVX512-NEXT: vpermi2d %zmm1, %zmm0, %zmm2
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm3 = [1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31]
; AVX512-NEXT: vpermi2d %zmm1, %zmm0, %zmm3
; AVX512-NEXT: vmovdqa64 %zmm2, (%rsi)
; AVX512-NEXT: vmovdqa64 %zmm3, (%rdx)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%wide.vec = load <32 x i32>, ptr %in.vec, align 64
%strided.vec0 = shufflevector <32 x i32> %wide.vec, <32 x i32> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%strided.vec1 = shufflevector <32 x i32> %wide.vec, <32 x i32> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
store <16 x i32> %strided.vec0, ptr %out.vec0, align 64
store <16 x i32> %strided.vec1, ptr %out.vec1, align 64
ret void
}
define void @load_i32_stride2_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
; SSE-LABEL: load_i32_stride2_vf32:
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: movaps 32(%rdi), %xmm1
; SSE-NEXT: movaps 48(%rdi), %xmm8
; SSE-NEXT: movaps 208(%rdi), %xmm9
; SSE-NEXT: movaps 192(%rdi), %xmm3
; SSE-NEXT: movaps 80(%rdi), %xmm11
; SSE-NEXT: movaps 64(%rdi), %xmm2
; SSE-NEXT: movaps 240(%rdi), %xmm10
; SSE-NEXT: movaps 224(%rdi), %xmm5
; SSE-NEXT: movaps 112(%rdi), %xmm12
; SSE-NEXT: movaps 96(%rdi), %xmm4
; SSE-NEXT: movaps 144(%rdi), %xmm13
; SSE-NEXT: movaps 128(%rdi), %xmm6
; SSE-NEXT: movaps 176(%rdi), %xmm14
; SSE-NEXT: movaps 160(%rdi), %xmm7
; SSE-NEXT: movaps %xmm4, %xmm15
; SSE-NEXT: shufps {{.*#+}} xmm15 = xmm15[0,2],xmm12[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm12[1,3]
; SSE-NEXT: movaps %xmm2, %xmm12
; SSE-NEXT: shufps {{.*#+}} xmm12 = xmm12[0,2],xmm11[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm11[1,3]
; SSE-NEXT: movaps %xmm7, %xmm11
; SSE-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,2],xmm14[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,3],xmm14[1,3]
; SSE-NEXT: movaps %xmm6, %xmm14
; SSE-NEXT: shufps {{.*#+}} xmm14 = xmm14[0,2],xmm13[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm13[1,3]
; SSE-NEXT: movaps %xmm5, %xmm13
; SSE-NEXT: shufps {{.*#+}} xmm13 = xmm13[0,2],xmm10[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,3],xmm10[1,3]
; SSE-NEXT: movaps %xmm3, %xmm10
; SSE-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm9[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,3],xmm9[1,3]
; SSE-NEXT: movaps %xmm1, %xmm9
; SSE-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm8[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm8[1,3]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps 16(%rdi), %xmm8
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm8[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm8[1,3]
; SSE-NEXT: movaps %xmm10, 96(%rsi)
; SSE-NEXT: movaps %xmm12, 32(%rsi)
; SSE-NEXT: movaps %xmm13, 112(%rsi)
; SSE-NEXT: movaps %xmm15, 48(%rsi)
; SSE-NEXT: movaps %xmm14, 64(%rsi)
; SSE-NEXT: movaps %xmm1, (%rsi)
; SSE-NEXT: movaps %xmm11, 80(%rsi)
; SSE-NEXT: movaps %xmm9, 16(%rsi)
; SSE-NEXT: movaps %xmm3, 96(%rdx)
; SSE-NEXT: movaps %xmm5, 112(%rdx)
; SSE-NEXT: movaps %xmm6, 64(%rdx)
; SSE-NEXT: movaps %xmm7, 80(%rdx)
; SSE-NEXT: movaps %xmm2, 32(%rdx)
; SSE-NEXT: movaps %xmm4, 48(%rdx)
; SSE-NEXT: movaps %xmm0, (%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 16(%rdx)
; SSE-NEXT: retq
;
; AVX1-ONLY-LABEL: load_i32_stride2_vf32:
; AVX1-ONLY: # %bb.0:
; AVX1-ONLY-NEXT: vmovaps (%rdi), %ymm0
; AVX1-ONLY-NEXT: vmovaps 64(%rdi), %ymm1
; AVX1-ONLY-NEXT: vmovaps 128(%rdi), %ymm2
; AVX1-ONLY-NEXT: vmovaps 192(%rdi), %ymm3
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm4 = ymm3[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 224(%rdi), %ymm3, %ymm3
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm5 = ymm3[0,2],ymm4[0,2],ymm3[4,6],ymm4[4,6]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm6 = ymm1[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 96(%rdi), %ymm1, %ymm1
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm7 = ymm1[0,2],ymm6[0,2],ymm1[4,6],ymm6[4,6]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm8 = ymm0[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 32(%rdi), %ymm0, %ymm0
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm9 = ymm0[0,2],ymm8[0,2],ymm0[4,6],ymm8[4,6]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm10 = ymm2[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 160(%rdi), %ymm2, %ymm2
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm11 = ymm2[0,2],ymm10[0,2],ymm2[4,6],ymm10[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm1 = ymm1[1,3],ymm6[1,3],ymm1[5,7],ymm6[5,7]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm3 = ymm3[1,3],ymm4[1,3],ymm3[5,7],ymm4[5,7]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm8[1,3],ymm0[5,7],ymm8[5,7]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm2 = ymm2[1,3],ymm10[1,3],ymm2[5,7],ymm10[5,7]
; AVX1-ONLY-NEXT: vmovaps %ymm11, 64(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm9, (%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm7, 32(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm5, 96(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm2, 64(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm0, (%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm3, 96(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm1, 32(%rdx)
; AVX1-ONLY-NEXT: vzeroupper
; AVX1-ONLY-NEXT: retq
;
; AVX2-ONLY-LABEL: load_i32_stride2_vf32:
; AVX2-ONLY: # %bb.0:
; AVX2-ONLY-NEXT: vmovaps (%rdi), %ymm0
; AVX2-ONLY-NEXT: vmovaps 32(%rdi), %ymm1
; AVX2-ONLY-NEXT: vmovaps 64(%rdi), %ymm2
; AVX2-ONLY-NEXT: vmovaps 96(%rdi), %ymm3
; AVX2-ONLY-NEXT: vmovaps 160(%rdi), %ymm4
; AVX2-ONLY-NEXT: vmovaps 128(%rdi), %ymm5
; AVX2-ONLY-NEXT: vmovaps 224(%rdi), %ymm6
; AVX2-ONLY-NEXT: vmovaps 192(%rdi), %ymm7
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm8 = ymm7[0,2],ymm6[0,2],ymm7[4,6],ymm6[4,6]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm8 = ymm8[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm9 = ymm5[0,2],ymm4[0,2],ymm5[4,6],ymm4[4,6]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm9 = ymm9[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm10 = ymm2[0,2],ymm3[0,2],ymm2[4,6],ymm3[4,6]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm10 = ymm10[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm11 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm11 = ymm11[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm6 = ymm7[1,3],ymm6[1,3],ymm7[5,7],ymm6[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm6 = ymm6[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm4 = ymm5[1,3],ymm4[1,3],ymm5[5,7],ymm4[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm4 = ymm4[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm2 = ymm2[1,3],ymm3[1,3],ymm2[5,7],ymm3[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,2,1,3]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm9, 64(%rsi)
; AVX2-ONLY-NEXT: vmovaps %ymm11, (%rsi)
; AVX2-ONLY-NEXT: vmovaps %ymm8, 96(%rsi)
; AVX2-ONLY-NEXT: vmovaps %ymm10, 32(%rsi)
; AVX2-ONLY-NEXT: vmovaps %ymm4, 64(%rdx)
; AVX2-ONLY-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-ONLY-NEXT: vmovaps %ymm6, 96(%rdx)
; AVX2-ONLY-NEXT: vmovaps %ymm2, 32(%rdx)
; AVX2-ONLY-NEXT: vzeroupper
; AVX2-ONLY-NEXT: retq
;
; AVX512-LABEL: load_i32_stride2_vf32:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512-NEXT: vmovdqa64 64(%rdi), %zmm1
; AVX512-NEXT: vmovdqa64 128(%rdi), %zmm2
; AVX512-NEXT: vmovdqa64 192(%rdi), %zmm3
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm4 = [0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30]
; AVX512-NEXT: vmovdqa64 %zmm0, %zmm5
; AVX512-NEXT: vpermt2d %zmm1, %zmm4, %zmm5
; AVX512-NEXT: vpermi2d %zmm3, %zmm2, %zmm4
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm6 = [1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31]
; AVX512-NEXT: vpermt2d %zmm1, %zmm6, %zmm0
; AVX512-NEXT: vpermt2d %zmm3, %zmm6, %zmm2
; AVX512-NEXT: vmovdqa64 %zmm4, 64(%rsi)
; AVX512-NEXT: vmovdqa64 %zmm5, (%rsi)
; AVX512-NEXT: vmovdqa64 %zmm2, 64(%rdx)
; AVX512-NEXT: vmovdqa64 %zmm0, (%rdx)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%wide.vec = load <64 x i32>, ptr %in.vec, align 64
%strided.vec0 = shufflevector <64 x i32> %wide.vec, <64 x i32> poison, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62>
%strided.vec1 = shufflevector <64 x i32> %wide.vec, <64 x i32> poison, <32 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 33, i32 35, i32 37, i32 39, i32 41, i32 43, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 59, i32 61, i32 63>
store <32 x i32> %strided.vec0, ptr %out.vec0, align 64
store <32 x i32> %strided.vec1, ptr %out.vec1, align 64
ret void
}
define void @load_i32_stride2_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nounwind {
; SSE-LABEL: load_i32_stride2_vf64:
; SSE: # %bb.0:
; SSE-NEXT: subq $152, %rsp
; SSE-NEXT: movaps 208(%rdi), %xmm7
; SSE-NEXT: movaps 192(%rdi), %xmm1
; SSE-NEXT: movaps 80(%rdi), %xmm10
; SSE-NEXT: movaps 64(%rdi), %xmm0
; SSE-NEXT: movaps 240(%rdi), %xmm11
; SSE-NEXT: movaps 224(%rdi), %xmm3
; SSE-NEXT: movaps 112(%rdi), %xmm13
; SSE-NEXT: movaps 96(%rdi), %xmm2
; SSE-NEXT: movaps 272(%rdi), %xmm9
; SSE-NEXT: movaps 144(%rdi), %xmm14
; SSE-NEXT: movaps 128(%rdi), %xmm4
; SSE-NEXT: movaps 304(%rdi), %xmm12
; SSE-NEXT: movaps 288(%rdi), %xmm6
; SSE-NEXT: movaps 176(%rdi), %xmm15
; SSE-NEXT: movaps 160(%rdi), %xmm5
; SSE-NEXT: movaps %xmm2, %xmm8
; SSE-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,2],xmm13[0,2]
; SSE-NEXT: movaps %xmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm13[1,3]
; SSE-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm10[0,2]
; SSE-NEXT: movaps %xmm2, (%rsp) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm10[1,3]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm5, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm15[0,2]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,3],xmm15[1,3]
; SSE-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm4, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm14[0,2]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm14[1,3]
; SSE-NEXT: movaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm11[0,2]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,3],xmm11[1,3]
; SSE-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm7[0,2]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm7[1,3]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm6, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm12[0,2]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm12[1,3]
; SSE-NEXT: movaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps 256(%rdi), %xmm0
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm9[0,2]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm9[1,3]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps 368(%rdi), %xmm0
; SSE-NEXT: movaps 352(%rdi), %xmm15
; SSE-NEXT: movaps %xmm15, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,2]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: shufps {{.*#+}} xmm15 = xmm15[1,3],xmm0[1,3]
; SSE-NEXT: movaps 336(%rdi), %xmm0
; SSE-NEXT: movaps 320(%rdi), %xmm13
; SSE-NEXT: movaps %xmm13, %xmm12
; SSE-NEXT: shufps {{.*#+}} xmm12 = xmm12[0,2],xmm0[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm13 = xmm13[1,3],xmm0[1,3]
; SSE-NEXT: movaps 432(%rdi), %xmm0
; SSE-NEXT: movaps 416(%rdi), %xmm9
; SSE-NEXT: movaps %xmm9, %xmm14
; SSE-NEXT: shufps {{.*#+}} xmm14 = xmm14[0,2],xmm0[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm9 = xmm9[1,3],xmm0[1,3]
; SSE-NEXT: movaps 400(%rdi), %xmm0
; SSE-NEXT: movaps 384(%rdi), %xmm6
; SSE-NEXT: movaps %xmm6, %xmm10
; SSE-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm0[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm0[1,3]
; SSE-NEXT: movaps 496(%rdi), %xmm1
; SSE-NEXT: movaps 480(%rdi), %xmm4
; SSE-NEXT: movaps %xmm4, %xmm5
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm1[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm1[1,3]
; SSE-NEXT: movaps 464(%rdi), %xmm3
; SSE-NEXT: movaps 448(%rdi), %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm3[1,3]
; SSE-NEXT: movaps 32(%rdi), %xmm11
; SSE-NEXT: movaps 48(%rdi), %xmm2
; SSE-NEXT: movaps %xmm11, %xmm3
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2],xmm2[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm11 = xmm11[1,3],xmm2[1,3]
; SSE-NEXT: movaps (%rdi), %xmm8
; SSE-NEXT: movaps 16(%rdi), %xmm2
; SSE-NEXT: movaps %xmm8, %xmm7
; SSE-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2],xmm2[0,2]
; SSE-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,3],xmm2[1,3]
; SSE-NEXT: movaps %xmm0, 224(%rsi)
; SSE-NEXT: movaps %xmm12, 160(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 96(%rsi)
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 32(%rsi)
; SSE-NEXT: movaps %xmm5, 240(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 176(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 112(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 48(%rsi)
; SSE-NEXT: movaps %xmm10, 192(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 128(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 64(%rsi)
; SSE-NEXT: movaps %xmm7, (%rsi)
; SSE-NEXT: movaps %xmm14, 208(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 144(%rsi)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 80(%rsi)
; SSE-NEXT: movaps %xmm3, 16(%rsi)
; SSE-NEXT: movaps %xmm1, 224(%rdx)
; SSE-NEXT: movaps %xmm4, 240(%rdx)
; SSE-NEXT: movaps %xmm6, 192(%rdx)
; SSE-NEXT: movaps %xmm9, 208(%rdx)
; SSE-NEXT: movaps %xmm13, 160(%rdx)
; SSE-NEXT: movaps %xmm15, 176(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 128(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 144(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 96(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 112(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 64(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 80(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 32(%rdx)
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movaps %xmm0, 48(%rdx)
; SSE-NEXT: movaps %xmm8, (%rdx)
; SSE-NEXT: movaps %xmm11, 16(%rdx)
; SSE-NEXT: addq $152, %rsp
; SSE-NEXT: retq
;
; AVX1-ONLY-LABEL: load_i32_stride2_vf64:
; AVX1-ONLY: # %bb.0:
; AVX1-ONLY-NEXT: vmovaps 384(%rdi), %ymm2
; AVX1-ONLY-NEXT: vmovaps 256(%rdi), %ymm4
; AVX1-ONLY-NEXT: vmovaps 320(%rdi), %ymm5
; AVX1-ONLY-NEXT: vmovaps (%rdi), %ymm1
; AVX1-ONLY-NEXT: vmovaps 64(%rdi), %ymm3
; AVX1-ONLY-NEXT: vmovaps 128(%rdi), %ymm6
; AVX1-ONLY-NEXT: vmovaps 192(%rdi), %ymm7
; AVX1-ONLY-NEXT: vmovaps 448(%rdi), %ymm0
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm8 = ymm0[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 480(%rdi), %ymm0, %ymm9
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm9[0,2],ymm8[0,2],ymm9[4,6],ymm8[4,6]
; AVX1-ONLY-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm10 = ymm3[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 96(%rdi), %ymm3, %ymm11
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm3 = ymm11[0,2],ymm10[0,2],ymm11[4,6],ymm10[4,6]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm12 = ymm7[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 224(%rdi), %ymm7, %ymm7
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm13 = ymm7[0,2],ymm12[0,2],ymm7[4,6],ymm12[4,6]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm14 = ymm5[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 352(%rdi), %ymm5, %ymm5
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm15 = ymm5[0,2],ymm14[0,2],ymm5[4,6],ymm14[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm10 = ymm11[1,3],ymm10[1,3],ymm11[5,7],ymm10[5,7]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm11 = ymm6[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 160(%rdi), %ymm6, %ymm6
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm7 = ymm7[1,3],ymm12[1,3],ymm7[5,7],ymm12[5,7]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm12 = ymm4[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 288(%rdi), %ymm4, %ymm4
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm5 = ymm5[1,3],ymm14[1,3],ymm5[5,7],ymm14[5,7]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm14 = ymm2[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 416(%rdi), %ymm2, %ymm2
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm8 = ymm9[1,3],ymm8[1,3],ymm9[5,7],ymm8[5,7]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm9 = ymm2[0,2],ymm14[0,2],ymm2[4,6],ymm14[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm2 = ymm2[1,3],ymm14[1,3],ymm2[5,7],ymm14[5,7]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm14 = ymm4[0,2],ymm12[0,2],ymm4[4,6],ymm12[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm4 = ymm4[1,3],ymm12[1,3],ymm4[5,7],ymm12[5,7]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm12 = ymm6[0,2],ymm11[0,2],ymm6[4,6],ymm11[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm6 = ymm6[1,3],ymm11[1,3],ymm6[5,7],ymm11[5,7]
; AVX1-ONLY-NEXT: vperm2f128 {{.*#+}} ymm11 = ymm1[2,3],mem[2,3]
; AVX1-ONLY-NEXT: vinsertf128 $1, 32(%rdi), %ymm1, %ymm1
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,2],ymm11[0,2],ymm1[4,6],ymm11[4,6]
; AVX1-ONLY-NEXT: vshufps {{.*#+}} ymm1 = ymm1[1,3],ymm11[1,3],ymm1[5,7],ymm11[5,7]
; AVX1-ONLY-NEXT: vmovaps %ymm9, 192(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm14, 128(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm12, 64(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm0, (%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm15, 160(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm13, 96(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm3, 32(%rsi)
; AVX1-ONLY-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; AVX1-ONLY-NEXT: vmovaps %ymm0, 224(%rsi)
; AVX1-ONLY-NEXT: vmovaps %ymm1, (%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm6, 64(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm4, 128(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm2, 192(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm8, 224(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm5, 160(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm7, 96(%rdx)
; AVX1-ONLY-NEXT: vmovaps %ymm10, 32(%rdx)
; AVX1-ONLY-NEXT: vzeroupper
; AVX1-ONLY-NEXT: retq
;
; AVX2-ONLY-LABEL: load_i32_stride2_vf64:
; AVX2-ONLY: # %bb.0:
; AVX2-ONLY-NEXT: vmovaps (%rdi), %ymm3
; AVX2-ONLY-NEXT: vmovaps 64(%rdi), %ymm1
; AVX2-ONLY-NEXT: vmovaps 96(%rdi), %ymm2
; AVX2-ONLY-NEXT: vmovaps 416(%rdi), %ymm4
; AVX2-ONLY-NEXT: vmovaps 384(%rdi), %ymm7
; AVX2-ONLY-NEXT: vmovaps 288(%rdi), %ymm5
; AVX2-ONLY-NEXT: vmovaps 256(%rdi), %ymm8
; AVX2-ONLY-NEXT: vmovaps 160(%rdi), %ymm6
; AVX2-ONLY-NEXT: vmovaps 128(%rdi), %ymm9
; AVX2-ONLY-NEXT: vmovaps 480(%rdi), %ymm10
; AVX2-ONLY-NEXT: vmovaps 448(%rdi), %ymm11
; AVX2-ONLY-NEXT: vmovaps 352(%rdi), %ymm12
; AVX2-ONLY-NEXT: vmovaps 320(%rdi), %ymm13
; AVX2-ONLY-NEXT: vmovaps 224(%rdi), %ymm14
; AVX2-ONLY-NEXT: vmovaps 192(%rdi), %ymm15
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm15[0,2],ymm14[0,2],ymm15[4,6],ymm14[4,6]
; AVX2-ONLY-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm14 = ymm15[1,3],ymm14[1,3],ymm15[5,7],ymm14[5,7]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm15 = ymm13[0,2],ymm12[0,2],ymm13[4,6],ymm12[4,6]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm12 = ymm13[1,3],ymm12[1,3],ymm13[5,7],ymm12[5,7]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm13 = ymm11[0,2],ymm10[0,2],ymm11[4,6],ymm10[4,6]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm10 = ymm11[1,3],ymm10[1,3],ymm11[5,7],ymm10[5,7]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm11 = ymm7[0,2],ymm4[0,2],ymm7[4,6],ymm4[4,6]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm4 = ymm7[1,3],ymm4[1,3],ymm7[5,7],ymm4[5,7]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm7 = ymm8[0,2],ymm5[0,2],ymm8[4,6],ymm5[4,6]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm5 = ymm8[1,3],ymm5[1,3],ymm8[5,7],ymm5[5,7]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm8 = ymm9[0,2],ymm6[0,2],ymm9[4,6],ymm6[4,6]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm6 = ymm9[1,3],ymm6[1,3],ymm9[5,7],ymm6[5,7]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm9 = ymm1[0,2],ymm2[0,2],ymm1[4,6],ymm2[4,6]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm1 = ymm1[1,3],ymm2[1,3],ymm1[5,7],ymm2[5,7]
; AVX2-ONLY-NEXT: vmovaps 32(%rdi), %ymm2
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm0 = ymm3[0,2],ymm2[0,2],ymm3[4,6],ymm2[4,6]
; AVX2-ONLY-NEXT: vshufps {{.*#+}} ymm2 = ymm3[1,3],ymm2[1,3],ymm3[5,7],ymm2[5,7]
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm3 = ymm11[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm3, 192(%rsi)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm3 = ymm7[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm3, 128(%rsi)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm3 = ymm8[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm3, 64(%rsi)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, (%rsi)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm13[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 224(%rsi)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm15[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 160(%rsi)
; AVX2-ONLY-NEXT: vpermpd $216, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Folded Reload
; AVX2-ONLY-NEXT: # ymm0 = mem[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 96(%rsi)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm9[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 32(%rsi)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm2[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, (%rdx)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm6[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 64(%rdx)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm5[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 128(%rdx)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm4[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 192(%rdx)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm10[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 224(%rdx)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm12[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 160(%rdx)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm14[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 96(%rdx)
; AVX2-ONLY-NEXT: vpermpd {{.*#+}} ymm0 = ymm1[0,2,1,3]
; AVX2-ONLY-NEXT: vmovaps %ymm0, 32(%rdx)
; AVX2-ONLY-NEXT: vzeroupper
; AVX2-ONLY-NEXT: retq
;
; AVX512-LABEL: load_i32_stride2_vf64:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512-NEXT: vmovdqa64 64(%rdi), %zmm1
; AVX512-NEXT: vmovdqa64 128(%rdi), %zmm2
; AVX512-NEXT: vmovdqa64 192(%rdi), %zmm3
; AVX512-NEXT: vmovdqa64 448(%rdi), %zmm4
; AVX512-NEXT: vmovdqa64 384(%rdi), %zmm5
; AVX512-NEXT: vmovdqa64 320(%rdi), %zmm6
; AVX512-NEXT: vmovdqa64 256(%rdi), %zmm7
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30]
; AVX512-NEXT: vmovdqa64 %zmm7, %zmm9
; AVX512-NEXT: vpermt2d %zmm6, %zmm8, %zmm9
; AVX512-NEXT: vmovdqa64 %zmm5, %zmm10
; AVX512-NEXT: vpermt2d %zmm4, %zmm8, %zmm10
; AVX512-NEXT: vmovdqa64 %zmm2, %zmm11
; AVX512-NEXT: vpermt2d %zmm3, %zmm8, %zmm11
; AVX512-NEXT: vpermi2d %zmm1, %zmm0, %zmm8
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm12 = [1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31]
; AVX512-NEXT: vpermt2d %zmm4, %zmm12, %zmm5
; AVX512-NEXT: vpermt2d %zmm6, %zmm12, %zmm7
; AVX512-NEXT: vpermt2d %zmm3, %zmm12, %zmm2
; AVX512-NEXT: vpermt2d %zmm1, %zmm12, %zmm0
; AVX512-NEXT: vmovdqa64 %zmm10, 192(%rsi)
; AVX512-NEXT: vmovdqa64 %zmm8, (%rsi)
; AVX512-NEXT: vmovdqa64 %zmm11, 64(%rsi)
; AVX512-NEXT: vmovdqa64 %zmm9, 128(%rsi)
; AVX512-NEXT: vmovdqa64 %zmm7, 128(%rdx)
; AVX512-NEXT: vmovdqa64 %zmm5, 192(%rdx)
; AVX512-NEXT: vmovdqa64 %zmm0, (%rdx)
; AVX512-NEXT: vmovdqa64 %zmm2, 64(%rdx)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%wide.vec = load <128 x i32>, ptr %in.vec, align 64
%strided.vec0 = shufflevector <128 x i32> %wide.vec, <128 x i32> poison, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62, i32 64, i32 66, i32 68, i32 70, i32 72, i32 74, i32 76, i32 78, i32 80, i32 82, i32 84, i32 86, i32 88, i32 90, i32 92, i32 94, i32 96, i32 98, i32 100, i32 102, i32 104, i32 106, i32 108, i32 110, i32 112, i32 114, i32 116, i32 118, i32 120, i32 122, i32 124, i32 126>
%strided.vec1 = shufflevector <128 x i32> %wide.vec, <128 x i32> poison, <64 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 33, i32 35, i32 37, i32 39, i32 41, i32 43, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 59, i32 61, i32 63, i32 65, i32 67, i32 69, i32 71, i32 73, i32 75, i32 77, i32 79, i32 81, i32 83, i32 85, i32 87, i32 89, i32 91, i32 93, i32 95, i32 97, i32 99, i32 101, i32 103, i32 105, i32 107, i32 109, i32 111, i32 113, i32 115, i32 117, i32 119, i32 121, i32 123, i32 125, i32 127>
store <64 x i32> %strided.vec0, ptr %out.vec0, align 64
store <64 x i32> %strided.vec1, ptr %out.vec1, align 64
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; AVX2: {{.*}}
; AVX2-FAST: {{.*}}
; AVX2-FAST-PERLANE: {{.*}}
; AVX2-SLOW: {{.*}}
; AVX512BW: {{.*}}
; AVX512BW-ONLY-FAST: {{.*}}
; AVX512BW-ONLY-SLOW: {{.*}}
; AVX512DQ-FAST: {{.*}}
; AVX512DQ-SLOW: {{.*}}
; AVX512DQBW-FAST: {{.*}}
; AVX512DQBW-SLOW: {{.*}}
; AVX512F: {{.*}}
; AVX512F-ONLY-FAST: {{.*}}
; AVX512F-ONLY-SLOW: {{.*}}
; FALLBACK0: {{.*}}
; FALLBACK1: {{.*}}
; FALLBACK10: {{.*}}
; FALLBACK11: {{.*}}
; FALLBACK12: {{.*}}
; FALLBACK2: {{.*}}
; FALLBACK3: {{.*}}
; FALLBACK4: {{.*}}
; FALLBACK5: {{.*}}
; FALLBACK6: {{.*}}
; FALLBACK7: {{.*}}
; FALLBACK8: {{.*}}
; FALLBACK9: {{.*}}