| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ |
| ; RUN: --riscv-no-aliases < %s | FileCheck %s |
| |
| declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8( |
| <vscale x 8 x i8>, |
| <vscale x 8 x i8>, |
| i64); |
| |
| define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu |
| ; CHECK-NEXT: vadd.vv v8, v8, v9 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8( |
| <vscale x 8 x i8> %0, |
| <vscale x 8 x i8> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x i8> %a |
| } |
| |
| declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8( |
| <vscale x 8 x i8>, |
| <vscale x 8 x i8>, |
| <vscale x 8 x i8>, |
| <vscale x 8 x i1>, |
| i64, i64); |
| |
| define <vscale x 8 x i8> @intrinsic_vadd_mask_tu(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vadd_mask_tu: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu |
| ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8( |
| <vscale x 8 x i8> %0, |
| <vscale x 8 x i8> %1, |
| <vscale x 8 x i8> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4, i64 0) |
| |
| ret <vscale x 8 x i8> %a |
| } |
| |
| define <vscale x 8 x i8> @intrinsic_vadd_mask_ta(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vadd_mask_ta: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu |
| ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8( |
| <vscale x 8 x i8> %0, |
| <vscale x 8 x i8> %1, |
| <vscale x 8 x i8> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4, i64 1) |
| |
| ret <vscale x 8 x i8> %a |
| } |
| |