| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 |
| --- | |
| |
| define void @zext() {entry: ret void} |
| define void @sext() {entry: ret void} |
| |
| ... |
| --- |
| name: zext |
| alignment: 4 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0 |
| |
| ; MIPS32-LABEL: name: zext |
| ; MIPS32: liveins: $a0 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 |
| ; MIPS32: $v0 = COPY [[COPY]](s32) |
| ; MIPS32: $v1 = COPY [[C]](s32) |
| ; MIPS32: RetRA implicit $v0, implicit $v1 |
| %0:_(s32) = COPY $a0 |
| %4:_(s32) = G_CONSTANT i32 0 |
| %1:_(s64) = G_MERGE_VALUES %0(s32), %4(s32) |
| %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) |
| $v0 = COPY %2(s32) |
| $v1 = COPY %3(s32) |
| RetRA implicit $v0, implicit $v1 |
| |
| ... |
| --- |
| name: sext |
| alignment: 4 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0 |
| |
| ; MIPS32-LABEL: name: sext |
| ; MIPS32: liveins: $a0 |
| ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 |
| ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31 |
| ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) |
| ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32) |
| ; MIPS32: $v0 = COPY [[COPY]](s32) |
| ; MIPS32: $v1 = COPY [[ASHR]](s32) |
| ; MIPS32: RetRA implicit $v0, implicit $v1 |
| %0:_(s32) = COPY $a0 |
| %7:_(s32) = G_CONSTANT i32 31 |
| %8:_(s32) = G_CONSTANT i32 0 |
| %6:_(s32) = COPY %7(s32) |
| %5:_(s32) = G_ASHR %0, %6(s32) |
| %1:_(s64) = G_MERGE_VALUES %0(s32), %5(s32) |
| %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) |
| $v0 = COPY %2(s32) |
| $v1 = COPY %3(s32) |
| RetRA implicit $v0, implicit $v1 |
| |
| ... |