llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll.expected

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; llc is replaced with cat, we just simulate llc by printing text from these files
; RUN: llc %S/amdgpu_no_merge_comments-O0.s | FileCheck -check-prefixes=GCN,GFX9-O0 %s
; RUN: llc %S/amdgpu_no_merge_comments-O3.s | FileCheck -check-prefixes=GCN,GFX9-O3 %s

target triple = "amdgcn--"

define hidden i32 @main(i32 %a) {
; GFX9-O0-LABEL: main:
; GFX9-O0:       ; %bb.0:
; GFX9-O0-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-O0-NEXT:    v_add_u32_e64 v1, v0, v0
; GFX9-O0-NEXT:    ; implicit-def: $sgpr4
; GFX9-O0-NEXT:    ; implicit-def: $sgpr4
; GFX9-O0-NEXT:    v_mul_lo_u32 v0, v1, v0
; GFX9-O0-NEXT:    v_sub_u32_e64 v0, v0, v1
; GFX9-O0-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-O3-LABEL: main:
; GFX9-O3:       ; %bb.0:
; GFX9-O3-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-O3-NEXT:    v_add_u32_e32 v1, v0, v0
; GFX9-O3-NEXT:    v_mul_lo_u32 v0, v1, v0
; GFX9-O3-NEXT:    v_sub_u32_e32 v0, v0, v1
; GFX9-O3-NEXT:    s_setpc_b64 s[30:31]
  %add = add i32 %a, %a
  %mul = mul i32 %add, %a
  %sub = sub i32 %mul, %add
  ret i32 %sub
}