Sign in
llvm
/
llvm-project
/
c01c62c76c60a5a5da0496e41faae907944c92dd
/
.
/
llvm
/
test
/
CodeGen
/
MIR
/
AMDGPU
/
mfi-parse-error-scratch-rsrc-reg.mir
blob: 0e0666d1cdeffddc643b87048159b20400393f89 [
file
] [
log
] [
blame
]
# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
---
name
:
empty_scratch_rsrc_reg
machineFunctionInfo
:
scratchRSrcReg
:
''
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
body
:
|
bb
.
0
:
S_ENDPGM
...