llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN

define void @fcmp_oeq_vv_v8f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vv_v8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v9, (a1)
; ZVFH-NEXT:    vmfeq.vv v8, v8, v9
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vv_v8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a1)
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = load <8 x half>, ptr %y
  %c = fcmp oeq <8 x half> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oeq_vv_v8f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vv_v8f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v9, (a1)
; ZVFH-NEXT:    vmfeq.vv v8, v8, v9
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vv_v8f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a1)
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = load <8 x half>, ptr %y
  %c = fcmp nnan oeq <8 x half> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_une_vv_v4f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v9, (a1)
; CHECK-NEXT:    vmfne.vv v0, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = load <4 x float>, ptr %y
  %c = fcmp une <4 x float> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_une_vv_v4f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v9, (a1)
; CHECK-NEXT:    vmfne.vv v0, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = load <4 x float>, ptr %y
  %c = fcmp nnan une <4 x float> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ogt_vv_v2f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v9, (a1)
; CHECK-NEXT:    vmflt.vv v0, v9, v8
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = load <2 x double>, ptr %y
  %c = fcmp ogt <2 x double> %a, %b
  store <2 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ogt_vv_v2f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v9, (a1)
; CHECK-NEXT:    vmflt.vv v0, v9, v8
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = load <2 x double>, ptr %y
  %c = fcmp nnan ogt <2 x double> %a, %b
  store <2 x i1> %c, ptr %z
  ret void
}

define void @fcmp_olt_vv_v16f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vv_v16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v10, (a1)
; ZVFH-NEXT:    vmflt.vv v12, v8, v10
; ZVFH-NEXT:    vsm.v v12, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vv_v16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a1)
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = load <16 x half>, ptr %y
  %c = fcmp olt <16 x half> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_olt_vv_v16f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vv_v16f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v10, (a1)
; ZVFH-NEXT:    vmflt.vv v12, v8, v10
; ZVFH-NEXT:    vsm.v v12, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vv_v16f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a1)
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = load <16 x half>, ptr %y
  %c = fcmp nnan olt <16 x half> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oge_vv_v8f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vv_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v12, v10, v8
; CHECK-NEXT:    vsm.v v12, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = load <8 x float>, ptr %y
  %c = fcmp oge <8 x float> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oge_vv_v8f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vv_v8f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v12, v10, v8
; CHECK-NEXT:    vsm.v v12, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = load <8 x float>, ptr %y
  %c = fcmp nnan oge <8 x float> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ole_vv_v4f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vv_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v0, v8, v10
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = load <4 x double>, ptr %y
  %c = fcmp ole <4 x double> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ole_vv_v4f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v10, (a1)
; CHECK-NEXT:    vmfle.vv v0, v8, v10
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = load <4 x double>, ptr %y
  %c = fcmp nnan ole <4 x double> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ule_vv_v32f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vv_v32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 32
; ZVFH-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v12, (a1)
; ZVFH-NEXT:    vmflt.vv v16, v12, v8
; ZVFH-NEXT:    vmnot.m v8, v16
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vv_v32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a3, 32
; ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    vle16.v v24, (a1)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v24, v16, v8
; ZVFHMIN-NEXT:    vmnot.m v8, v24
; ZVFHMIN-NEXT:    vsm.v v8, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = load <32 x half>, ptr %y
  %c = fcmp ule <32 x half> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ule_vv_v32f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vv_v32f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 32
; ZVFH-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v12, (a1)
; ZVFH-NEXT:    vmfle.vv v16, v8, v12
; ZVFH-NEXT:    vsm.v v16, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vv_v32f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a3, 32
; ZVFHMIN-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a1)
; ZVFHMIN-NEXT:    vle16.v v24, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmfle.vv v24, v16, v8
; ZVFHMIN-NEXT:    vsm.v v24, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = load <32 x half>, ptr %y
  %c = fcmp nnan ule <32 x half> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_uge_vv_v16f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vv_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v12, (a1)
; CHECK-NEXT:    vmflt.vv v16, v8, v12
; CHECK-NEXT:    vmnot.m v8, v16
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = load <16 x float>, ptr %y
  %c = fcmp uge <16 x float> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_uge_vv_v16f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vv_v16f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v12, (a1)
; CHECK-NEXT:    vmfle.vv v16, v12, v8
; CHECK-NEXT:    vsm.v v16, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = load <16 x float>, ptr %y
  %c = fcmp nnan uge <16 x float> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ult_vv_v8f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v12, (a1)
; CHECK-NEXT:    vmfle.vv v16, v12, v8
; CHECK-NEXT:    vmnot.m v8, v16
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = load <8 x double>, ptr %y
  %c = fcmp ult <8 x double> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ult_vv_v8f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v12, (a1)
; CHECK-NEXT:    vmflt.vv v16, v8, v12
; CHECK-NEXT:    vsm.v v16, (a2)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = load <8 x double>, ptr %y
  %c = fcmp nnan ult <8 x double> %a, %b
  store <8 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ugt_vv_v64f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vv_v64f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 64
; ZVFH-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v16, (a1)
; ZVFH-NEXT:    vmfle.vv v24, v8, v16
; ZVFH-NEXT:    vmnot.m v8, v24
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = load <64 x half>, ptr %y
  %c = fcmp ugt <64 x half> %a, %b
  store <64 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ugt_vv_v64f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vv_v64f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a3, 64
; ZVFH-NEXT:    vsetvli zero, a3, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vle16.v v16, (a1)
; ZVFH-NEXT:    vmflt.vv v24, v16, v8
; ZVFH-NEXT:    vsm.v v24, (a2)
; ZVFH-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = load <64 x half>, ptr %y
  %c = fcmp nnan ugt <64 x half> %a, %b
  store <64 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ueq_vv_v32f32(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vv_v32f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a3, 32
; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v16, (a1)
; CHECK-NEXT:    vmflt.vv v24, v8, v16
; CHECK-NEXT:    vmflt.vv v25, v16, v8
; CHECK-NEXT:    vmnor.mm v8, v25, v24
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = load <32 x float>, ptr %y
  %c = fcmp ueq <32 x float> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ueq_vv_v32f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vv_v32f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a3, 32
; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vle32.v v16, (a1)
; CHECK-NEXT:    vmfeq.vv v24, v8, v16
; CHECK-NEXT:    vsm.v v24, (a2)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = load <32 x float>, ptr %y
  %c = fcmp nnan ueq <32 x float> %a, %b
  store <32 x i1> %c, ptr %z
  ret void
}

define void @fcmp_one_vv_v8f64(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v16, (a1)
; CHECK-NEXT:    vmflt.vv v24, v8, v16
; CHECK-NEXT:    vmflt.vv v25, v16, v8
; CHECK-NEXT:    vmor.mm v8, v25, v24
; CHECK-NEXT:    vsm.v v8, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = load <16 x double>, ptr %y
  %c = fcmp one <16 x double> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_one_vv_v8f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vle64.v v16, (a1)
; CHECK-NEXT:    vmfne.vv v24, v8, v16
; CHECK-NEXT:    vsm.v v24, (a2)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = load <16 x double>, ptr %y
  %c = fcmp nnan one <16 x double> %a, %b
  store <16 x i1> %c, ptr %z
  ret void
}

define void @fcmp_ord_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_ord_vv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a1)
; ZVFH-NEXT:    vle16.v v9, (a0)
; ZVFH-NEXT:    vmfeq.vv v8, v8, v8
; ZVFH-NEXT:    vmfeq.vv v9, v9, v9
; ZVFH-NEXT:    vmand.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ord_vv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a1)
; ZVFHMIN-NEXT:    vle16.v v9, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v9, v10, v10
; ZVFHMIN-NEXT:    vmfeq.vv v8, v8, v8
; ZVFHMIN-NEXT:    vmand.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <4 x half>, ptr %x
  %b = load <4 x half>, ptr %y
  %c = fcmp ord <4 x half> %a, %b
  store <4 x i1> %c, ptr %z
  ret void
}

define void @fcmp_uno_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-LABEL: fcmp_uno_vv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a1)
; ZVFH-NEXT:    vle16.v v9, (a0)
; ZVFH-NEXT:    vmfne.vv v8, v8, v8
; ZVFH-NEXT:    vmfne.vv v9, v9, v9
; ZVFH-NEXT:    vmor.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a2)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_uno_vv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a1)
; ZVFHMIN-NEXT:    vle16.v v9, (a0)
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v9, v10, v10
; ZVFHMIN-NEXT:    vmfne.vv v8, v8, v8
; ZVFHMIN-NEXT:    vmor.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a2)
; ZVFHMIN-NEXT:    ret
  %a = load <2 x half>, ptr %x
  %b = load <2 x half>, ptr %y
  %c = fcmp uno <2 x half> %a, %b
  store <2 x i1> %c, ptr %z
  ret void
}

define void @fcmp_oeq_vf_v8f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vf_v8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vf_v8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v8, v10
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp oeq <8 x half> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oeq_vf_v8f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_vf_v8f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_vf_v8f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v8, v10
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oeq <8 x half> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_vf_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp une <4 x float> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_vf_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan une <4 x float> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_vf_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp ogt <2 x double> %a, %c
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_vf_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp nnan ogt <2 x double> %a, %c
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_vf_v16f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vf_v16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vf_v16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v8, v12
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp olt <16 x half> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_vf_v16f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_vf_v16f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_vf_v16f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v8, v12
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan olt <16 x half> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_vf_v8f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vf_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp oge <8 x float> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_vf_v8f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_vf_v8f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oge <8 x float> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_vf_v4f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp ole <4 x double> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_vf_v4f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan ole <4 x double> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_vf_v32f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vf_v32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v12, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v12
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vf_v32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v24, v16, v8
; ZVFHMIN-NEXT:    vmnot.m v8, v24
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp ule <32 x half> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_vf_v32f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_vf_v32f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfle.vf v12, v8, fa0
; ZVFH-NEXT:    vsm.v v12, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_vf_v32f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmfle.vv v24, v8, v16
; ZVFHMIN-NEXT:    vsm.v v24, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ule <32 x half> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_vf_v16f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vf_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp uge <16 x float> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_vf_v16f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_vf_v16f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan uge <16 x float> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_vf_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vf_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp ult <8 x double> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_vf_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_vf_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan ult <8 x double> %a, %c
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_vf_v64f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vf_v64f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfle.vf v16, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v16
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp ugt <64 x half> %a, %c
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_vf_v64f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_vf_v64f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v16, v8, fa0
; ZVFH-NEXT:    vsm.v v16, (a1)
; ZVFH-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp nnan ugt <64 x half> %a, %c
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_vf_v32f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vf_v32f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v16, v8, fa0
; CHECK-NEXT:    vmfgt.vf v17, v8, fa0
; CHECK-NEXT:    vmnor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp ueq <32 x float> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_vf_v32f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_vf_v32f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfeq.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ueq <32 x float> %a, %c
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_vf_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vf_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v16, v8, fa0
; CHECK-NEXT:    vmfgt.vf v17, v8, fa0
; CHECK-NEXT:    vmor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp one <16 x double> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_vf_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_vf_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan one <16 x double> %a, %c
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ord_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ord_vf_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfeq.vf v9, v9, fa0
; ZVFH-NEXT:    vmfeq.vv v8, v8, v8
; ZVFH-NEXT:    vmand.mm v0, v8, v9
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ord_vf_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmand.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <4 x half>, ptr %x
  %b = insertelement <4 x half> poison, half %y, i32 0
  %c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
  %d = fcmp ord <4 x half> %a, %c
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uno_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_uno_vf_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfne.vf v9, v9, fa0
; ZVFH-NEXT:    vmfne.vv v8, v8, v8
; ZVFH-NEXT:    vmor.mm v0, v8, v9
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_uno_vf_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmor.mm v0, v8, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <2 x half>, ptr %x
  %b = insertelement <2 x half> poison, half %y, i32 0
  %c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
  %d = fcmp uno <2 x half> %a, %c
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oeq_fv_v8f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_fv_v8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_fv_v8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp oeq <8 x half> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oeq_fv_v8f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_oeq_fv_v8f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfeq.vf v8, v8, fa0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_oeq_fv_v8f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vle16.v v10, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v12, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT:    vsm.v v12, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <8 x half>, ptr %x
  %b = insertelement <8 x half> poison, half %y, i32 0
  %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oeq <8 x half> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_fv_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp une <4 x float> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_une_fv_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x float>, ptr %x
  %b = insertelement <4 x float> poison, float %y, i32 0
  %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan une <4 x float> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_fv_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp ogt <2 x double> %c, %a
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ogt_fv_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmflt.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <2 x double>, ptr %x
  %b = insertelement <2 x double> poison, double %y, i32 0
  %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
  %d = fcmp nnan ogt <2 x double> %c, %a
  store <2 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_fv_v16f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_fv_v16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_fv_v16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp olt <16 x half> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_olt_fv_v16f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_olt_fv_v16f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfgt.vf v10, v8, fa0
; ZVFH-NEXT:    vsm.v v10, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_olt_fv_v16f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v12, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v16, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT:    vsm.v v16, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <16 x half>, ptr %x
  %b = insertelement <16 x half> poison, half %y, i32 0
  %c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan olt <16 x half> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_fv_v8f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_fv_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp oge <8 x float> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_oge_fv_v8f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_oge_fv_v8f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v10, v8, fa0
; CHECK-NEXT:    vsm.v v10, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x float>, ptr %x
  %b = insertelement <8 x float> poison, float %y, i32 0
  %c = shufflevector <8 x float> %b, <8 x float> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan oge <8 x float> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_fv_v4f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp ole <4 x double> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ole_fv_v4f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfge.vf v0, v8, fa0
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v9, 0
; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT:    vmv.v.v v9, v8
; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT:    vmsne.vi v8, v9, 0
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <4 x double>, ptr %x
  %b = insertelement <4 x double> poison, double %y, i32 0
  %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
  %d = fcmp nnan ole <4 x double> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_fv_v32f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_fv_v32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v12, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v12
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_fv_v32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmflt.vv v24, v8, v16
; ZVFHMIN-NEXT:    vmnot.m v8, v24
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp ule <32 x half> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ule_fv_v32f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ule_fv_v32f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 32
; ZVFH-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfge.vf v12, v8, fa0
; ZVFH-NEXT:    vsm.v v12, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ule_fv_v32f16_nonans:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    li a2, 32
; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v16, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v24, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v16
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vmfle.vv v24, v16, v8
; ZVFHMIN-NEXT:    vsm.v v24, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <32 x half>, ptr %x
  %b = insertelement <32 x half> poison, half %y, i32 0
  %c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ule <32 x half> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_fv_v16f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_fv_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp uge <16 x float> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uge_fv_v16f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_uge_fv_v16f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x float>, ptr %x
  %b = insertelement <16 x float> poison, float %y, i32 0
  %c = shufflevector <16 x float> %b, <16 x float> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan uge <16 x float> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_fv_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_fv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfle.vf v12, v8, fa0
; CHECK-NEXT:    vmnot.m v8, v12
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp ult <8 x double> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ult_fv_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ult_fv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v12, v8, fa0
; CHECK-NEXT:    vsm.v v12, (a1)
; CHECK-NEXT:    ret
  %a = load <8 x double>, ptr %x
  %b = insertelement <8 x double> poison, double %y, i32 0
  %c = shufflevector <8 x double> %b, <8 x double> poison, <8 x i32> zeroinitializer
  %d = fcmp nnan ult <8 x double> %c, %a
  store <8 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_fv_v64f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_fv_v64f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmfge.vf v16, v8, fa0
; ZVFH-NEXT:    vmnot.m v8, v16
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp ugt <64 x half> %c, %a
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ugt_fv_v64f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ugt_fv_v64f16_nonans:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    li a2, 64
; ZVFH-NEXT:    vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vmflt.vf v16, v8, fa0
; ZVFH-NEXT:    vsm.v v16, (a1)
; ZVFH-NEXT:    ret
  %a = load <64 x half>, ptr %x
  %b = insertelement <64 x half> poison, half %y, i32 0
  %c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
  %d = fcmp nnan ugt <64 x half> %c, %a
  store <64 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_fv_v32f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_fv_v32f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v16, v8, fa0
; CHECK-NEXT:    vmflt.vf v17, v8, fa0
; CHECK-NEXT:    vmnor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp ueq <32 x float> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ueq_fv_v32f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_ueq_fv_v32f32_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a2, 32
; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmfeq.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <32 x float>, ptr %x
  %b = insertelement <32 x float> poison, float %y, i32 0
  %c = shufflevector <32 x float> %b, <32 x float> poison, <32 x i32> zeroinitializer
  %d = fcmp nnan ueq <32 x float> %c, %a
  store <32 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_fv_v8f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_fv_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfgt.vf v16, v8, fa0
; CHECK-NEXT:    vmflt.vf v17, v8, fa0
; CHECK-NEXT:    vmor.mm v8, v17, v16
; CHECK-NEXT:    vsm.v v8, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp one <16 x double> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_one_fv_v8f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_one_fv_v8f64_nonans:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vle64.v v8, (a0)
; CHECK-NEXT:    vmfne.vf v16, v8, fa0
; CHECK-NEXT:    vsm.v v16, (a1)
; CHECK-NEXT:    ret
  %a = load <16 x double>, ptr %x
  %b = insertelement <16 x double> poison, double %y, i32 0
  %c = shufflevector <16 x double> %b, <16 x double> poison, <16 x i32> zeroinitializer
  %d = fcmp nnan one <16 x double> %c, %a
  store <16 x i1> %d, ptr %z
  ret void
}

define void @fcmp_ord_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_ord_fv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfeq.vf v9, v9, fa0
; ZVFH-NEXT:    vmfeq.vv v8, v8, v8
; ZVFH-NEXT:    vmand.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_ord_fv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vmfeq.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmand.mm v0, v9, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 4, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <4 x half>, ptr %x
  %b = insertelement <4 x half> poison, half %y, i32 0
  %c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
  %d = fcmp ord <4 x half> %c, %a
  store <4 x i1> %d, ptr %z
  ret void
}

define void @fcmp_uno_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-LABEL: fcmp_uno_fv_v4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFH-NEXT:    vle16.v v8, (a0)
; ZVFH-NEXT:    vfmv.v.f v9, fa0
; ZVFH-NEXT:    vmfne.vf v9, v9, fa0
; ZVFH-NEXT:    vmfne.vv v8, v8, v8
; ZVFH-NEXT:    vmor.mm v0, v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFH-NEXT:    vmv.v.i v8, 0
; ZVFH-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmv.v.i v9, 0
; ZVFH-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFH-NEXT:    vmv.v.v v9, v8
; ZVFH-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFH-NEXT:    vmsne.vi v8, v9, 0
; ZVFH-NEXT:    vsm.v v8, (a1)
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: fcmp_uno_fv_v4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vle16.v v8, (a0)
; ZVFHMIN-NEXT:    fmv.x.h a0, fa0
; ZVFHMIN-NEXT:    vmv.v.x v9, a0
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v9, v10, v10
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT:    vmor.mm v0, v9, v8
; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v8, 0
; ZVFHMIN-NEXT:    vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmv.v.i v9, 0
; ZVFHMIN-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
; ZVFHMIN-NEXT:    vmv.v.v v9, v8
; ZVFHMIN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
; ZVFHMIN-NEXT:    vmsne.vi v8, v9, 0
; ZVFHMIN-NEXT:    vsm.v v8, (a1)
; ZVFHMIN-NEXT:    ret
  %a = load <2 x half>, ptr %x
  %b = insertelement <2 x half> poison, half %y, i32 0
  %c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
  %d = fcmp uno <2 x half> %c, %a
  store <2 x i1> %d, ptr %z
  ret void
}