llvm/test/Transforms/PhaseOrdering/AArch64/scalarize-load-ext-extract.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -O3 -mtriple=arm64-apple-darwinos -S %s | FileCheck %s

define noundef i32 @load_ext_extract(ptr %src) {
; CHECK-LABEL: define noundef range(i32 0, 1021) i32 @load_ext_extract(
; CHECK-SAME: ptr readonly captures(none) [[SRC:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP14]], i64 0
; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], <i32 0, i32 8, i32 16, i32 24>
; CHECK-NEXT:    [[TMP5:%.*]] = and <4 x i32> [[TMP2]], <i32 255, i32 255, i32 255, i32 -1>
; CHECK-NEXT:    [[ADD3:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
; CHECK-NEXT:    ret i32 [[ADD3]]
;
entry:
  %x = load <4 x i8>, ptr %src, align 4
  %ext = zext nneg <4 x i8> %x to <4 x i32>
  %ext.0 = extractelement <4 x i32> %ext, i64 0
  %ext.1 = extractelement <4 x i32> %ext, i64 1
  %ext.2 = extractelement <4 x i32> %ext, i64 2
  %ext.3 = extractelement <4 x i32> %ext, i64 3

  %add1 = add i32 %ext.0, %ext.1
  %add2 = add i32 %add1, %ext.2
  %add3 = add i32 %add2, %ext.3
  ret i32 %add3
}