llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "middle.block:" --version 5
; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@inc = global float 5.000000e-01, align 4

;float inc = 0.5;
;void foo(ptr A, unsigned N) {
;
;  for (unsigned i=0; i<N; i++){
;    A[i] += inc;
;  }
;}

define void @foo(ptr nocapture noalias %A, i64 %N) #0 {
; CHECK-LABEL: define void @foo(
; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[TMP1:%.*]] = load float, ptr @inc, align 4
; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[TMP1]], i64 0
; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds float, ptr [[A]], i64 8
; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds float, ptr [[A]], i64 16
; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds float, ptr [[A]], i64 24
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x float>, ptr [[A]], align 4
; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <8 x float>, ptr [[TMP4]], align 4
; CHECK-NEXT:    [[WIDE_LOAD3:%.*]] = load <8 x float>, ptr [[TMP5]], align 4
; CHECK-NEXT:    [[WIDE_LOAD4:%.*]] = load <8 x float>, ptr [[TMP6]], align 4
; CHECK-NEXT:    [[TMP7:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; CHECK-NEXT:    [[TMP8:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD2]]
; CHECK-NEXT:    [[TMP9:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD3]]
; CHECK-NEXT:    [[TMP10:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD4]]
; CHECK-NEXT:    store <8 x float> [[TMP7]], ptr [[A]], align 4
; CHECK-NEXT:    store <8 x float> [[TMP8]], ptr [[TMP4]], align 4
; CHECK-NEXT:    store <8 x float> [[TMP9]], ptr [[TMP5]], align 4
; CHECK-NEXT:    store <8 x float> [[TMP10]], ptr [[TMP6]], align 4
; CHECK-NEXT:    br label %[[MIDDLE_BLOCK:.*]]
; CHECK:       [[MIDDLE_BLOCK]]:
;
entry:
  br label %loop

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %l.inc = load float, ptr @inc, align 4
  %gep.A = getelementptr inbounds float, ptr %A, i64 %iv
  %l.A = load float, ptr %gep.A, align 4
  %add = fadd float %l.inc, %l.A
  store float %add, ptr %gep.A, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, 32
  br i1 %ec, label %exit, label %loop

exit:
  ret void
}

define void @uniform_load_can_fold_users(ptr noalias %src, ptr %dst, i64 %start, double %d) {
; CHECK-LABEL: define void @uniform_load_can_fold_users(
; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i64 [[START:%.*]], double [[D:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[LOOP:.*]]
; CHECK:       [[LOOP]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT:    [[IV_2:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = load double, ptr [[SRC]], align 8
; CHECK-NEXT:    [[TMP7:%.*]] = fmul double [[TMP5]], 9.000000e+00
; CHECK-NEXT:    [[TMP8:%.*]] = fdiv double [[TMP7]], [[D]]
; CHECK-NEXT:    [[TMP10:%.*]] = sub i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr double, ptr [[TMP12]], i64 [[TMP10]]
; CHECK-NEXT:    store double [[TMP8]], ptr [[TMP14]], align 8
; CHECK-NEXT:    [[IV_1_NEXT]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[IV_2_NEXT]] = add i64 [[IV_2]], -1
; CHECK-NEXT:    [[EC:%.*]] = icmp sgt i64 [[IV_2]], 0
; CHECK-NEXT:    br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]
  %iv.2 = phi i64 [ %start, %entry ], [ %iv.2.next, %loop ]
  %l = load double, ptr %src, align 8
  %m = fmul double %l, 9.0
  %div = fdiv double %m, %d
  %sub = sub i64 %iv.1, 1
  %gep.1 = getelementptr double, ptr %dst, i64 %iv.1
  %gep.2 = getelementptr double, ptr %gep.1, i64 %sub
  store double %div, ptr %gep.2, align 8
  %iv.1.next = add i64 %iv.1, 1
  %iv.2.next = add i64 %iv.2, -1
  %ec = icmp sgt i64 %iv.2, 0
  br i1 %ec , label %loop, label %exit

exit:
  ret void
}

attributes #0 = { "target-cpu"="core-avx2" }