llvm/test/CodeGen/X86/isel-fmul.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=SDAG-X86
; RUN: llc < %s -mtriple=i686-- -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=FASTISEL-X86
; RUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=GISEL-X86
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=AVX

define float @test_fmul_f32(float %arg1, float %arg2) {
; SDAG-X86-LABEL: test_fmul_f32:
; SDAG-X86:       # %bb.0:
; SDAG-X86-NEXT:    flds {{[0-9]+}}(%esp)
; SDAG-X86-NEXT:    fmuls {{[0-9]+}}(%esp)
; SDAG-X86-NEXT:    retl
;
; FASTISEL-X86-LABEL: test_fmul_f32:
; FASTISEL-X86:       # %bb.0:
; FASTISEL-X86-NEXT:    flds {{[0-9]+}}(%esp)
; FASTISEL-X86-NEXT:    flds {{[0-9]+}}(%esp)
; FASTISEL-X86-NEXT:    fmulp %st, %st(1)
; FASTISEL-X86-NEXT:    retl
;
; GISEL-X86-LABEL: test_fmul_f32:
; GISEL-X86:       # %bb.0:
; GISEL-X86-NEXT:    flds {{[0-9]+}}(%esp)
; GISEL-X86-NEXT:    fmuls {{[0-9]+}}(%esp)
; GISEL-X86-NEXT:    retl
;
; SSE-LABEL: test_fmul_f32:
; SSE:       # %bb.0:
; SSE-NEXT:    mulss %xmm1, %xmm0
; SSE-NEXT:    retq
;
; AVX-LABEL: test_fmul_f32:
; AVX:       # %bb.0:
; AVX-NEXT:    vmulss %xmm1, %xmm0, %xmm0
; AVX-NEXT:    retq
  %ret = fmul float %arg1, %arg2
  ret float %ret
}

define double @test_fmul_f64(double %arg1, double %arg2) {
; SDAG-X86-LABEL: test_fmul_f64:
; SDAG-X86:       # %bb.0:
; SDAG-X86-NEXT:    fldl {{[0-9]+}}(%esp)
; SDAG-X86-NEXT:    fmull {{[0-9]+}}(%esp)
; SDAG-X86-NEXT:    retl
;
; FASTISEL-X86-LABEL: test_fmul_f64:
; FASTISEL-X86:       # %bb.0:
; FASTISEL-X86-NEXT:    fldl {{[0-9]+}}(%esp)
; FASTISEL-X86-NEXT:    fldl {{[0-9]+}}(%esp)
; FASTISEL-X86-NEXT:    fmulp %st, %st(1)
; FASTISEL-X86-NEXT:    retl
;
; GISEL-X86-LABEL: test_fmul_f64:
; GISEL-X86:       # %bb.0:
; GISEL-X86-NEXT:    fldl {{[0-9]+}}(%esp)
; GISEL-X86-NEXT:    fmull {{[0-9]+}}(%esp)
; GISEL-X86-NEXT:    retl
;
; SSE-LABEL: test_fmul_f64:
; SSE:       # %bb.0:
; SSE-NEXT:    mulsd %xmm1, %xmm0
; SSE-NEXT:    retq
;
; AVX-LABEL: test_fmul_f64:
; AVX:       # %bb.0:
; AVX-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT:    retq
  %ret = fmul double %arg1, %arg2
  ret double %ret
}