llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s --check-prefix=ENABLE
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-insert-vsetvli-whole-vector-register-move-valid-vtype=false | FileCheck %s --check-prefix=DISABLE

define <vscale x 8 x i8>  @foo(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2) nounwind {
; ENABLE-LABEL: foo:
; ENABLE:       # %bb.0: # %entry
; ENABLE-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
; ENABLE-NEXT:    vmv1r.v v8, v9
; ENABLE-NEXT:    vmadd.vv v8, v9, v9
; ENABLE-NEXT:    ret
;
; DISABLE-LABEL: foo:
; DISABLE:       # %bb.0: # %entry
; DISABLE-NEXT:    vmv1r.v v8, v9
; DISABLE-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
; DISABLE-NEXT:    vmadd.vv v8, v9, v9
; DISABLE-NEXT:    ret
entry:
  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
    <vscale x 8 x i8> %1,
    <vscale x 8 x i8> %1,
    <vscale x 8 x i8> %1,
    i64 1, i64 1)

  ret <vscale x 8 x i8> %a
}