llvm/test/CodeGen/RISCV/rvv/vabdu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvabd \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvabd \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64

define <vscale x 1 x i8> @vabdu_vv_i8mf8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i8mf8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v9
; CHECK-NEXT:    ret
  %res = call <vscale x 1 x i8> @llvm.riscv.vabdu(<vscale x 1 x i8> poison, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b, iXLen %vl)
  ret <vscale x 1 x i8> %res
}

define <vscale x 1 x i8> @vabdu_vv_mask_i8mf8(<vscale x 1 x i8> %passthru, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8mf8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v9, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 1 x i8> @llvm.riscv.vabdu.mask(
    <vscale x 1 x i8> %passthru,
    <vscale x 1 x i8> %a,
    <vscale x 1 x i8> %b,
    <vscale x 1 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 1 x i8> %res
}

define <vscale x 2 x i8> @vabdu_vv_i8mf4(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i8mf4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v9
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i8> @llvm.riscv.vabdu(<vscale x 2 x i8> poison, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b, iXLen %vl)
  ret <vscale x 2 x i8> %res
}

define <vscale x 2 x i8> @vabdu_vv_mask_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8mf4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v9, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i8> @llvm.riscv.vabdu.mask(
    <vscale x 2 x i8> %passthru,
    <vscale x 2 x i8> %a,
    <vscale x 2 x i8> %b,
    <vscale x 2 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 2 x i8> %res
}

define <vscale x 4 x i8> @vabdu_vv_i8mf2(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i8mf2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v9
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i8> @llvm.riscv.vabdu(<vscale x 4 x i8> poison, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b, iXLen %vl)
  ret <vscale x 4 x i8> %res
}

define <vscale x 4 x i8> @vabdu_vv_mask_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8mf2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v9, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i8> @llvm.riscv.vabdu.mask(
    <vscale x 4 x i8> %passthru,
    <vscale x 4 x i8> %a,
    <vscale x 4 x i8> %b,
    <vscale x 4 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 4 x i8> %res
}

define <vscale x 8 x i8> @vabdu_vv_i8m1(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i8m1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v9
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i8> @llvm.riscv.vabdu(<vscale x 8 x i8> poison, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b, iXLen %vl)
  ret <vscale x 8 x i8> %res
}

define <vscale x 8 x i8> @vabdu_vv_mask_i8m1(<vscale x 8 x i8> %passthru, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8m1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v9, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i8> @llvm.riscv.vabdu.mask(
    <vscale x 8 x i8> %passthru,
    <vscale x 8 x i8> %a,
    <vscale x 8 x i8> %b,
    <vscale x 8 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 8 x i8> %res
}

define <vscale x 16 x i8> @vabdu_vv_i8m2(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i8m2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v10
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i8> @llvm.riscv.vabdu(<vscale x 16 x i8> poison, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, iXLen %vl)
  ret <vscale x 16 x i8> %res
}

define <vscale x 16 x i8> @vabdu_vv_mask_i8m2(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8m2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v10, v12, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i8> @llvm.riscv.vabdu.mask(
    <vscale x 16 x i8> %passthru,
    <vscale x 16 x i8> %a,
    <vscale x 16 x i8> %b,
    <vscale x 16 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 16 x i8> %res
}

define <vscale x 32 x i8> @vabdu_vv_i8m4(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i8m4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v12
; CHECK-NEXT:    ret
  %res = call <vscale x 32 x i8> @llvm.riscv.vabdu(<vscale x 32 x i8> poison, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b, iXLen %vl)
  ret <vscale x 32 x i8> %res
}

define <vscale x 32 x i8> @vabdu_vv_mask_i8m4(<vscale x 32 x i8> %passthru, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8m4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v12, v16, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 32 x i8> @llvm.riscv.vabdu.mask(
    <vscale x 32 x i8> %passthru,
    <vscale x 32 x i8> %a,
    <vscale x 32 x i8> %b,
    <vscale x 32 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 32 x i8> %res
}

define <vscale x 64 x i8> @vabdu_vv_i8m8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i8m8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v16
; CHECK-NEXT:    ret
  %res = call <vscale x 64 x i8> @llvm.riscv.vabdu(<vscale x 64 x i8> poison, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b, iXLen %vl)
  ret <vscale x 64 x i8> %res
}

define <vscale x 64 x i8> @vabdu_vv_mask_i8m8(<vscale x 64 x i8> %passthru, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8m8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT:    vle8.v v24, (a0)
; CHECK-NEXT:    vabdu.vv v8, v16, v24, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 64 x i8> @llvm.riscv.vabdu.mask(
    <vscale x 64 x i8> %passthru,
    <vscale x 64 x i8> %a,
    <vscale x 64 x i8> %b,
    <vscale x 64 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 64 x i8> %res
}

define <vscale x 1 x i16> @vabdu_vv_i16mf4(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i16mf4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v9
; CHECK-NEXT:    ret
  %res = call <vscale x 1 x i16> @llvm.riscv.vabdu(<vscale x 1 x i16> poison, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b, iXLen %vl)
  ret <vscale x 1 x i16> %res
}

define <vscale x 1 x i16> @vabdu_vv_mask_i16mf4(<vscale x 1 x i16> %passthru, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i16mf4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v9, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 1 x i16> @llvm.riscv.vabdu.mask(
    <vscale x 1 x i16> %passthru,
    <vscale x 1 x i16> %a,
    <vscale x 1 x i16> %b,
    <vscale x 1 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 1 x i16> %res
}

define <vscale x 2 x i16> @vabdu_vv_i16mf2(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i16mf2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v9
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i16> @llvm.riscv.vabdu(<vscale x 2 x i16> poison, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %vl)
  ret <vscale x 2 x i16> %res
}

define <vscale x 2 x i16> @vabdu_vv_mask_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i16mf2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v9, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i16> @llvm.riscv.vabdu.mask(
    <vscale x 2 x i16> %passthru,
    <vscale x 2 x i16> %a,
    <vscale x 2 x i16> %b,
    <vscale x 2 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 2 x i16> %res
}

define <vscale x 4 x i16> @vabdu_vv_i16m1(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i16m1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v9
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i16> @llvm.riscv.vabdu(<vscale x 4 x i16> poison, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b, iXLen %vl)
  ret <vscale x 4 x i16> %res
}

define <vscale x 4 x i16> @vabdu_vv_mask_i16m1(<vscale x 4 x i16> %passthru, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i16m1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v9, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i16> @llvm.riscv.vabdu.mask(
    <vscale x 4 x i16> %passthru,
    <vscale x 4 x i16> %a,
    <vscale x 4 x i16> %b,
    <vscale x 4 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 4 x i16> %res
}

define <vscale x 8 x i16> @vabdu_vv_i16m2(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i16m2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v10
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.riscv.vabdu(<vscale x 8 x i16> poison, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, iXLen %vl)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @vabdu_vv_mask_i16m2(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i16m2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v10, v12, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.riscv.vabdu.mask(
    <vscale x 8 x i16> %passthru,
    <vscale x 8 x i16> %a,
    <vscale x 8 x i16> %b,
    <vscale x 8 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 8 x i16> %res
}

define <vscale x 16 x i16> @vabdu_vv_i16m4(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i16m4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v12
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i16> @llvm.riscv.vabdu(<vscale x 16 x i16> poison, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b, iXLen %vl)
  ret <vscale x 16 x i16> %res
}

define <vscale x 16 x i16> @vabdu_vv_mask_i16m4(<vscale x 16 x i16> %passthru, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i16m4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT:    vabdu.vv v8, v12, v16, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i16> @llvm.riscv.vabdu.mask(
    <vscale x 16 x i16> %passthru,
    <vscale x 16 x i16> %a,
    <vscale x 16 x i16> %b,
    <vscale x 16 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 16 x i16> %res
}

define <vscale x 32 x i16> @vabdu_vv_i16m8(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_i16m8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT:    vabdu.vv v8, v8, v16
; CHECK-NEXT:    ret
  %res = call <vscale x 32 x i16> @llvm.riscv.vabdu(<vscale x 32 x i16> poison, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b, iXLen %vl)
  ret <vscale x 32 x i16> %res
}

define <vscale x 32 x i16> @vabdu_vv_mask_i16m8(<vscale x 32 x i16> %passthru, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i16m8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT:    vle16.v v24, (a0)
; CHECK-NEXT:    vabdu.vv v8, v16, v24, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 32 x i16> @llvm.riscv.vabdu.mask(
    <vscale x 32 x i16> %passthru,
    <vscale x 32 x i16> %a,
    <vscale x 32 x i16> %b,
    <vscale x 32 x i1> %mask,
    iXLen %vl, iXLen 1)
  ret <vscale x 32 x i16> %res
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}