llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmmbase \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmmbase \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

define iXLen @test_sf_vsettnt_e8w1(iXLen %tn) {
; CHECK-LABEL: test_sf_vsettnt_e8w1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sf.vsettnt a0, a0, e8, w1
; CHECK-NEXT:    ret
 entry:
   %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 0, iXLen 1)
   ret iXLen %0
}

define iXLen @test_sf_vsettnt_e8w2(iXLen %tn) {
; CHECK-LABEL: test_sf_vsettnt_e8w2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sf.vsettnt a0, a0, e8, w2
; CHECK-NEXT:    ret
 entry:
   %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 0, iXLen 2)
   ret iXLen %0
}

define iXLen @test_sf_vsettnt_e8w4(iXLen %tn) {
; CHECK-LABEL: test_sf_vsettnt_e8w4:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sf.vsettnt a0, a0, e8, w4
; CHECK-NEXT:    ret
 entry:
   %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 0, iXLen 3)
   ret iXLen %0
}

define iXLen @test_sf_vsettnt_e16w1(iXLen %tn) {
; CHECK-LABEL: test_sf_vsettnt_e16w1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sf.vsettnt a0, a0, e16, w1
; CHECK-NEXT:    ret
 entry:
   %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 1, iXLen 1)
   ret iXLen %0
}

define iXLen @test_sf_vsettnt_e16w2(iXLen %tn) {
; CHECK-LABEL: test_sf_vsettnt_e16w2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sf.vsettnt a0, a0, e16, w2
; CHECK-NEXT:    ret
 entry:
   %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 1, iXLen 2)
   ret iXLen %0
}

define iXLen @test_sf_vsettnt_e16w4(iXLen %tn) {
; CHECK-LABEL: test_sf_vsettnt_e16w4:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sf.vsettnt a0, a0, e16, w4
; CHECK-NEXT:    ret
 entry:
   %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 1, iXLen 3)
   ret iXLen %0
}