llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmmbase \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmmbase \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

define dso_local void @test_sf_vlte32(iXLen %tss, ptr %base, iXLen %vl) {
; CHECK-LABEL: test_sf_vlte32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    sf.vsettnt zero, a2, e32, w1
; CHECK-NEXT:    sf.vlte32 a0, (a1)
; CHECK-NEXT:    ret
  entry:
    call void @llvm.riscv.sf.vlte32.iXLen(iXLen %tss, ptr %base, iXLen %vl)
    ret void
}