llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \
; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \
; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64

define <2 x i8> @vp_ctlz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)
  ret <2 x i8> %v
}

define <2 x i8> @vp_ctlz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i8> %v
}

define <4 x i8> @vp_ctlz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)
  ret <4 x i8> %v
}

define <4 x i8> @vp_ctlz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i8> %v
}

define <8 x i8> @vp_ctlz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vzext.vf2 v10, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v10
; CHECK-NEXT:    vnsrl.wi v10, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v10, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)
  ret <8 x i8> %v
}

define <8 x i8> @vp_ctlz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vzext.vf2 v10, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v10
; CHECK-NEXT:    vnsrl.wi v10, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v10, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i8> %v
}

define <16 x i8> @vp_ctlz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vzext.vf2 v12, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v12
; CHECK-NEXT:    vnsrl.wi v12, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v12, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)
  ret <16 x i8> %v
}

define <16 x i8> @vp_ctlz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vzext.vf2 v12, v8
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v12
; CHECK-NEXT:    vnsrl.wi v12, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v12, 0
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 8
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i8> %v
}

define <2 x i16> @vp_ctlz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)
  ret <2 x i16> %v
}

define <2 x i16> @vp_ctlz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i16> %v
}

define <4 x i16> @vp_ctlz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)
  ret <4 x i16> %v
}

define <4 x i16> @vp_ctlz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i16> %v
}

define <8 x i16> @vp_ctlz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v10, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)
  ret <8 x i16> %v
}

define <8 x i16> @vp_ctlz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v10, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i16> %v
}

define <16 x i16> @vp_ctlz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v12, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)
  ret <16 x i16> %v
}

define <16 x i16> @vp_ctlz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vnsrl.wi v8, v12, 23
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 16
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i16> %v
}

define <2 x i32> @vp_ctlz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v9, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)
  ret <2 x i32> %v
}

define <2 x i32> @vp_ctlz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v9, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i32> %v
}

define <4 x i32> @vp_ctlz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v10, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)
  ret <4 x i32> %v
}

define <4 x i32> @vp_ctlz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v10, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i32> %v
}

define <8 x i32> @vp_ctlz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v12, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)
  ret <8 x i32> %v
}

define <8 x i32> @vp_ctlz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v12, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i32> %v
}

define <16 x i32> @vp_ctlz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v16, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v16, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)
  ret <16 x i32> %v
}

define <16 x i32> @vp_ctlz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v16, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v16, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    vminu.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i32> %v
}

define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
  ret <2 x i64> %v
}

define <2 x i64> @vp_ctlz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i64> %v
}

define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
  ret <4 x i64> %v
}

define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i64> %v
}

define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
  ret <8 x i64> %v
}

define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i64> %v
}

define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v15i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
  ret <15 x i64> %v
}

define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v15i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl)
  ret <15 x i64> %v
}

define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
  ret <16 x i64> %v
}

define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    li a1, 64
; CHECK-NEXT:    vminu.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i64> %v
}

define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v32i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    li a2, 1086
; CHECK-NEXT:    li a3, 64
; CHECK-NEXT:    vfcvt.f.xu.v v16, v16
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    vsrl.vx v16, v16, a1
; CHECK-NEXT:    vrsub.vx v8, v8, a2
; CHECK-NEXT:    vrsub.vx v16, v16, a2
; CHECK-NEXT:    vminu.vx v8, v8, a3
; CHECK-NEXT:    vminu.vx v16, v16, a3
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
  ret <32 x i64> %v
}

define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v32i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    li a2, 1086
; CHECK-NEXT:    li a3, 64
; CHECK-NEXT:    vfcvt.f.xu.v v16, v16
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    vsrl.vx v16, v16, a1
; CHECK-NEXT:    vrsub.vx v8, v8, a2
; CHECK-NEXT:    vrsub.vx v16, v16, a2
; CHECK-NEXT:    vminu.vx v8, v8, a3
; CHECK-NEXT:    vminu.vx v16, v16, a3
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl)
  ret <32 x i64> %v
}

define <2 x i8> @vp_ctlz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl)
  ret <2 x i8> %v
}

define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i8> %v
}

define <4 x i8> @vp_ctlz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl)
  ret <4 x i8> %v
}

define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vzext.vf2 v9, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
; CHECK-NEXT:    vnsrl.wi v8, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v8, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i8> %v
}

define <8 x i8> @vp_ctlz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vzext.vf2 v10, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v10
; CHECK-NEXT:    vnsrl.wi v10, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v10, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl)
  ret <8 x i8> %v
}

define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vzext.vf2 v10, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v10
; CHECK-NEXT:    vnsrl.wi v10, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v10, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i8> %v
}

define <16 x i8> @vp_ctlz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vzext.vf2 v12, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v12
; CHECK-NEXT:    vnsrl.wi v12, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v12, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl)
  ret <16 x i8> %v
}

define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i8_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vzext.vf2 v12, v8
; CHECK-NEXT:    vfwcvt.f.xu.v v8, v12
; CHECK-NEXT:    vnsrl.wi v12, v8, 23
; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT:    vnsrl.wi v8, v12, 0
; CHECK-NEXT:    li a0, 134
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i8> %v
}

define <2 x i16> @vp_ctlz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl)
  ret <2 x i16> %v
}

define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i16> %v
}

define <4 x i16> @vp_ctlz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl)
  ret <4 x i16> %v
}

define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    vnsrl.wi v8, v9, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i16> %v
}

define <8 x i16> @vp_ctlz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    vnsrl.wi v8, v10, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl)
  ret <8 x i16> %v
}

define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    vnsrl.wi v8, v10, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i16> %v
}

define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    vnsrl.wi v8, v12, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl)
  ret <16 x i16> %v
}

define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i16_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    vnsrl.wi v8, v12, 23
; CHECK-NEXT:    li a0, 142
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i16> %v
}

define <2 x i32> @vp_ctlz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v9, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl)
  ret <2 x i32> %v
}

define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v9, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v9, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i32> %v
}

define <4 x i32> @vp_ctlz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v10, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl)
  ret <4 x i32> %v
}

define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v10, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v10, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i32> %v
}

define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v12, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl)
  ret <8 x i32> %v
}

define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v12, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v12, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i32> %v
}

define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v16, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v16, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl)
  ret <16 x i32> %v
}

define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT:    vfwcvt.f.xu.v v16, v8
; CHECK-NEXT:    li a0, 52
; CHECK-NEXT:    vnsrl.wx v8, v16, a0
; CHECK-NEXT:    li a0, 1054
; CHECK-NEXT:    vrsub.vx v8, v8, a0
; CHECK-NEXT:    ret
  %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i32> %v
}

define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)
  ret <2 x i64> %v
}

define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl)
  ret <2 x i64> %v
}

define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)
  ret <4 x i64> %v
}

define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl)
  ret <4 x i64> %v
}

define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)
  ret <8 x i64> %v
}

define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl)
  ret <8 x i64> %v
}

define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v15i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)
  ret <15 x i64> %v
}

define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v15i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> splat (i1 true), i32 %evl)
  ret <15 x i64> %v
}

define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)
  ret <16 x i64> %v
}

define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    li a1, 1086
; CHECK-NEXT:    vrsub.vx v8, v8, a1
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
  ret <16 x i64> %v
}

define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v32i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    li a2, 1086
; CHECK-NEXT:    vfcvt.f.xu.v v16, v16
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    vsrl.vx v16, v16, a1
; CHECK-NEXT:    vrsub.vx v8, v8, a2
; CHECK-NEXT:    vrsub.vx v16, v16, a2
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
  ret <32 x i64> %v
}

define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v32i64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fsrmi a0, 1
; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
; CHECK-NEXT:    li a1, 52
; CHECK-NEXT:    li a2, 1086
; CHECK-NEXT:    vfcvt.f.xu.v v16, v16
; CHECK-NEXT:    vsrl.vx v8, v8, a1
; CHECK-NEXT:    vsrl.vx v16, v16, a1
; CHECK-NEXT:    vrsub.vx v8, v8, a2
; CHECK-NEXT:    vrsub.vx v16, v16, a2
; CHECK-NEXT:    fsrm a0
; CHECK-NEXT:    ret
  %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> splat (i1 true), i32 %evl)
  ret <32 x i64> %v
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}