llvm/test/CodeGen/RISCV/inline-asm-bf-constraint-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin,+zfh -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV32FZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin,+zfh -target-abi=lp64f -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV64FZFBFMIN %s

define bfloat @constraint_f_bfloat(float %a) nounwind {
; RV32FZFBFMIN-LABEL: constraint_f_bfloat:
; RV32FZFBFMIN:       # %bb.0:
; RV32FZFBFMIN-NEXT:    fmv.w.x fa5, a0
; RV32FZFBFMIN-NEXT:    #APP
; RV32FZFBFMIN-NEXT:    fcvt.bf16.s fa5, fa5
; RV32FZFBFMIN-NEXT:    #NO_APP
; RV32FZFBFMIN-NEXT:    fmv.x.h a0, fa5
; RV32FZFBFMIN-NEXT:    ret
;
; RV64FZFBFMIN-LABEL: constraint_f_bfloat:
; RV64FZFBFMIN:       # %bb.0:
; RV64FZFBFMIN-NEXT:    #APP
; RV64FZFBFMIN-NEXT:    fcvt.bf16.s fa0, fa0
; RV64FZFBFMIN-NEXT:    #NO_APP
; RV64FZFBFMIN-NEXT:    ret
  %1 = tail call bfloat asm "fcvt.bf16.s $0, $1", "=f,f"(float %a)
  ret bfloat %1
}

define bfloat @constraint_cf_bfloat(float %a) nounwind {
; RV32FZFBFMIN-LABEL: constraint_cf_bfloat:
; RV32FZFBFMIN:       # %bb.0:
; RV32FZFBFMIN-NEXT:    fmv.w.x fa5, a0
; RV32FZFBFMIN-NEXT:    #APP
; RV32FZFBFMIN-NEXT:    fcvt.bf16.s fa5, fa5
; RV32FZFBFMIN-NEXT:    #NO_APP
; RV32FZFBFMIN-NEXT:    fmv.x.h a0, fa5
; RV32FZFBFMIN-NEXT:    ret
;
; RV64FZFBFMIN-LABEL: constraint_cf_bfloat:
; RV64FZFBFMIN:       # %bb.0:
; RV64FZFBFMIN-NEXT:    #APP
; RV64FZFBFMIN-NEXT:    fcvt.bf16.s fa0, fa0
; RV64FZFBFMIN-NEXT:    #NO_APP
; RV64FZFBFMIN-NEXT:    ret
  %1 = tail call bfloat asm "fcvt.bf16.s $0, $1", "=^cf,^cf"(float %a)
  ret bfloat %1
}