| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck -check-prefix=RV32I %s |
| |
| @x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 |
| @y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 |
| |
| ; Besides anything else, these tests help verify that libcall ABI lowering |
| ; works correctly |
| |
| define i32 @test_load_and_cmp() nounwind { |
| ; RV32I-LABEL: test_load_and_cmp: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -48 |
| ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: lui a0, %hi(x) |
| ; RV32I-NEXT: lui a1, %hi(y) |
| ; RV32I-NEXT: lw a2, %lo(x)(a0) |
| ; RV32I-NEXT: lw a3, %lo(x+4)(a0) |
| ; RV32I-NEXT: lw a4, %lo(x+8)(a0) |
| ; RV32I-NEXT: lw a5, %lo(x+12)(a0) |
| ; RV32I-NEXT: lw a0, %lo(y)(a1) |
| ; RV32I-NEXT: lw a6, %lo(y+4)(a1) |
| ; RV32I-NEXT: lw a7, %lo(y+8)(a1) |
| ; RV32I-NEXT: lw a1, %lo(y+12)(a1) |
| ; RV32I-NEXT: sw a0, 8(sp) |
| ; RV32I-NEXT: sw a6, 12(sp) |
| ; RV32I-NEXT: sw a7, 16(sp) |
| ; RV32I-NEXT: sw a1, 20(sp) |
| ; RV32I-NEXT: addi a0, sp, 24 |
| ; RV32I-NEXT: addi a1, sp, 8 |
| ; RV32I-NEXT: sw a2, 24(sp) |
| ; RV32I-NEXT: sw a3, 28(sp) |
| ; RV32I-NEXT: sw a4, 32(sp) |
| ; RV32I-NEXT: sw a5, 36(sp) |
| ; RV32I-NEXT: call __netf2 |
| ; RV32I-NEXT: snez a0, a0 |
| ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 48 |
| ; RV32I-NEXT: ret |
| %1 = load fp128, ptr @x, align 16 |
| %2 = load fp128, ptr @y, align 16 |
| %cmp = fcmp une fp128 %1, %2 |
| %3 = zext i1 %cmp to i32 |
| ret i32 %3 |
| } |
| |
| define i32 @test_add_and_fptosi() nounwind { |
| ; RV32I-LABEL: test_add_and_fptosi: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -80 |
| ; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: lui a0, %hi(x) |
| ; RV32I-NEXT: lui a1, %hi(y) |
| ; RV32I-NEXT: lw a3, %lo(x)(a0) |
| ; RV32I-NEXT: lw a4, %lo(x+4)(a0) |
| ; RV32I-NEXT: lw a5, %lo(x+8)(a0) |
| ; RV32I-NEXT: lw a6, %lo(x+12)(a0) |
| ; RV32I-NEXT: lw a0, %lo(y)(a1) |
| ; RV32I-NEXT: lw a2, %lo(y+4)(a1) |
| ; RV32I-NEXT: lw a7, %lo(y+8)(a1) |
| ; RV32I-NEXT: lw a1, %lo(y+12)(a1) |
| ; RV32I-NEXT: sw a0, 24(sp) |
| ; RV32I-NEXT: sw a2, 28(sp) |
| ; RV32I-NEXT: sw a7, 32(sp) |
| ; RV32I-NEXT: sw a1, 36(sp) |
| ; RV32I-NEXT: addi a0, sp, 56 |
| ; RV32I-NEXT: addi a1, sp, 40 |
| ; RV32I-NEXT: addi a2, sp, 24 |
| ; RV32I-NEXT: sw a3, 40(sp) |
| ; RV32I-NEXT: sw a4, 44(sp) |
| ; RV32I-NEXT: sw a5, 48(sp) |
| ; RV32I-NEXT: sw a6, 52(sp) |
| ; RV32I-NEXT: call __addtf3 |
| ; RV32I-NEXT: lw a1, 56(sp) |
| ; RV32I-NEXT: lw a2, 60(sp) |
| ; RV32I-NEXT: lw a3, 64(sp) |
| ; RV32I-NEXT: lw a4, 68(sp) |
| ; RV32I-NEXT: addi a0, sp, 8 |
| ; RV32I-NEXT: sw a1, 8(sp) |
| ; RV32I-NEXT: sw a2, 12(sp) |
| ; RV32I-NEXT: sw a3, 16(sp) |
| ; RV32I-NEXT: sw a4, 20(sp) |
| ; RV32I-NEXT: call __fixtfsi |
| ; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 80 |
| ; RV32I-NEXT: ret |
| %1 = load fp128, ptr @x, align 16 |
| %2 = load fp128, ptr @y, align 16 |
| %3 = fadd fp128 %1, %2 |
| %4 = fptosi fp128 %3 to i32 |
| ret i32 %4 |
| } |
| |
| define fp128 @fmaximum(fp128 %x, fp128 %y) { |
| ; RV32I-LABEL: fmaximum: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -64 |
| ; RV32I-NEXT: .cfi_def_cfa_offset 64 |
| ; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: .cfi_offset ra, -4 |
| ; RV32I-NEXT: .cfi_offset s0, -8 |
| ; RV32I-NEXT: lw a3, 0(a1) |
| ; RV32I-NEXT: lw a4, 4(a1) |
| ; RV32I-NEXT: lw a5, 8(a1) |
| ; RV32I-NEXT: lw a6, 12(a1) |
| ; RV32I-NEXT: lw a1, 0(a2) |
| ; RV32I-NEXT: lw a7, 4(a2) |
| ; RV32I-NEXT: lw t0, 8(a2) |
| ; RV32I-NEXT: lw a2, 12(a2) |
| ; RV32I-NEXT: mv s0, a0 |
| ; RV32I-NEXT: sw a1, 8(sp) |
| ; RV32I-NEXT: sw a7, 12(sp) |
| ; RV32I-NEXT: sw t0, 16(sp) |
| ; RV32I-NEXT: sw a2, 20(sp) |
| ; RV32I-NEXT: addi a0, sp, 40 |
| ; RV32I-NEXT: addi a1, sp, 24 |
| ; RV32I-NEXT: addi a2, sp, 8 |
| ; RV32I-NEXT: sw a3, 24(sp) |
| ; RV32I-NEXT: sw a4, 28(sp) |
| ; RV32I-NEXT: sw a5, 32(sp) |
| ; RV32I-NEXT: sw a6, 36(sp) |
| ; RV32I-NEXT: call fmaximuml |
| ; RV32I-NEXT: lw a0, 40(sp) |
| ; RV32I-NEXT: lw a1, 44(sp) |
| ; RV32I-NEXT: lw a2, 48(sp) |
| ; RV32I-NEXT: lw a3, 52(sp) |
| ; RV32I-NEXT: sw a0, 0(s0) |
| ; RV32I-NEXT: sw a1, 4(s0) |
| ; RV32I-NEXT: sw a2, 8(s0) |
| ; RV32I-NEXT: sw a3, 12(s0) |
| ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: .cfi_restore ra |
| ; RV32I-NEXT: .cfi_restore s0 |
| ; RV32I-NEXT: addi sp, sp, 64 |
| ; RV32I-NEXT: .cfi_def_cfa_offset 0 |
| ; RV32I-NEXT: ret |
| %a = call fp128 @llvm.maximum.fp128(fp128 %x, fp128 %y) |
| ret fp128 %a |
| } |
| |
| define fp128 @fminimum(fp128 %x, fp128 %y) { |
| ; RV32I-LABEL: fminimum: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -64 |
| ; RV32I-NEXT: .cfi_def_cfa_offset 64 |
| ; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: .cfi_offset ra, -4 |
| ; RV32I-NEXT: .cfi_offset s0, -8 |
| ; RV32I-NEXT: lw a3, 0(a1) |
| ; RV32I-NEXT: lw a4, 4(a1) |
| ; RV32I-NEXT: lw a5, 8(a1) |
| ; RV32I-NEXT: lw a6, 12(a1) |
| ; RV32I-NEXT: lw a1, 0(a2) |
| ; RV32I-NEXT: lw a7, 4(a2) |
| ; RV32I-NEXT: lw t0, 8(a2) |
| ; RV32I-NEXT: lw a2, 12(a2) |
| ; RV32I-NEXT: mv s0, a0 |
| ; RV32I-NEXT: sw a1, 8(sp) |
| ; RV32I-NEXT: sw a7, 12(sp) |
| ; RV32I-NEXT: sw t0, 16(sp) |
| ; RV32I-NEXT: sw a2, 20(sp) |
| ; RV32I-NEXT: addi a0, sp, 40 |
| ; RV32I-NEXT: addi a1, sp, 24 |
| ; RV32I-NEXT: addi a2, sp, 8 |
| ; RV32I-NEXT: sw a3, 24(sp) |
| ; RV32I-NEXT: sw a4, 28(sp) |
| ; RV32I-NEXT: sw a5, 32(sp) |
| ; RV32I-NEXT: sw a6, 36(sp) |
| ; RV32I-NEXT: call fminimuml |
| ; RV32I-NEXT: lw a0, 40(sp) |
| ; RV32I-NEXT: lw a1, 44(sp) |
| ; RV32I-NEXT: lw a2, 48(sp) |
| ; RV32I-NEXT: lw a3, 52(sp) |
| ; RV32I-NEXT: sw a0, 0(s0) |
| ; RV32I-NEXT: sw a1, 4(s0) |
| ; RV32I-NEXT: sw a2, 8(s0) |
| ; RV32I-NEXT: sw a3, 12(s0) |
| ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: .cfi_restore ra |
| ; RV32I-NEXT: .cfi_restore s0 |
| ; RV32I-NEXT: addi sp, sp, 64 |
| ; RV32I-NEXT: .cfi_def_cfa_offset 0 |
| ; RV32I-NEXT: ret |
| %a = call fp128 @llvm.minimum.fp128(fp128 %x, fp128 %y) |
| ret fp128 %a |
| } |
| |
| define { fp128, fp128 } @modf(fp128 %a) nounwind { |
| ; RV32I-LABEL: modf: |
| ; RV32I: # %bb.0: |
| ; RV32I-NEXT: addi sp, sp, -64 |
| ; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: lw a3, 0(a1) |
| ; RV32I-NEXT: lw a4, 4(a1) |
| ; RV32I-NEXT: lw a5, 8(a1) |
| ; RV32I-NEXT: lw a6, 12(a1) |
| ; RV32I-NEXT: mv s0, a0 |
| ; RV32I-NEXT: addi a0, sp, 24 |
| ; RV32I-NEXT: addi a1, sp, 8 |
| ; RV32I-NEXT: addi a2, sp, 40 |
| ; RV32I-NEXT: sw a3, 8(sp) |
| ; RV32I-NEXT: sw a4, 12(sp) |
| ; RV32I-NEXT: sw a5, 16(sp) |
| ; RV32I-NEXT: sw a6, 20(sp) |
| ; RV32I-NEXT: call modfl |
| ; RV32I-NEXT: lw a0, 24(sp) |
| ; RV32I-NEXT: lw a1, 28(sp) |
| ; RV32I-NEXT: lw a2, 32(sp) |
| ; RV32I-NEXT: lw a3, 36(sp) |
| ; RV32I-NEXT: lw a4, 40(sp) |
| ; RV32I-NEXT: lw a5, 44(sp) |
| ; RV32I-NEXT: lw a6, 48(sp) |
| ; RV32I-NEXT: lw a7, 52(sp) |
| ; RV32I-NEXT: sw a4, 16(s0) |
| ; RV32I-NEXT: sw a5, 20(s0) |
| ; RV32I-NEXT: sw a6, 24(s0) |
| ; RV32I-NEXT: sw a7, 28(s0) |
| ; RV32I-NEXT: sw a0, 0(s0) |
| ; RV32I-NEXT: sw a1, 4(s0) |
| ; RV32I-NEXT: sw a2, 8(s0) |
| ; RV32I-NEXT: sw a3, 12(s0) |
| ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 64 |
| ; RV32I-NEXT: ret |
| %result = call { fp128, fp128 } @llvm.modf.f128(fp128 %a) |
| ret { fp128, fp128 } %result |
| } |
| |
| define i96 @fptosi_fp128_to_i96(fp128 %a) nounwind { |
| ; RV32I-LABEL: fptosi_fp128_to_i96: |
| ; RV32I: # %bb.0: # %fp-to-i-entry |
| ; RV32I-NEXT: addi sp, sp, -112 |
| ; RV32I-NEXT: sw ra, 108(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s0, 104(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s1, 100(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s2, 96(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s3, 92(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s4, 88(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s5, 84(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s6, 80(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s7, 76(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s8, 72(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s9, 68(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: sw s10, 64(sp) # 4-byte Folded Spill |
| ; RV32I-NEXT: lw a5, 12(a1) |
| ; RV32I-NEXT: lui a6, 4 |
| ; RV32I-NEXT: slli a2, a5, 1 |
| ; RV32I-NEXT: srli a2, a2, 17 |
| ; RV32I-NEXT: addi a3, a6, -1 |
| ; RV32I-NEXT: mv s0, a0 |
| ; RV32I-NEXT: bgeu a2, a3, .LBB5_2 |
| ; RV32I-NEXT: # %bb.1: |
| ; RV32I-NEXT: li s3, 0 |
| ; RV32I-NEXT: li s8, 0 |
| ; RV32I-NEXT: li a0, 0 |
| ; RV32I-NEXT: j .LBB5_5 |
| ; RV32I-NEXT: .LBB5_2: # %fp-to-i-if-check.exp.size |
| ; RV32I-NEXT: lw a4, 0(a1) |
| ; RV32I-NEXT: lw a3, 4(a1) |
| ; RV32I-NEXT: lw a0, 8(a1) |
| ; RV32I-NEXT: srai s1, a5, 31 |
| ; RV32I-NEXT: addi a1, a6, 110 |
| ; RV32I-NEXT: ori s2, s1, 1 |
| ; RV32I-NEXT: bltu a1, a2, .LBB5_4 |
| ; RV32I-NEXT: # %bb.3: # %fp-to-i-if-exp.small |
| ; RV32I-NEXT: slli a5, a5, 16 |
| ; RV32I-NEXT: lui a1, 16 |
| ; RV32I-NEXT: sw zero, 16(sp) |
| ; RV32I-NEXT: sw zero, 20(sp) |
| ; RV32I-NEXT: sw zero, 24(sp) |
| ; RV32I-NEXT: sw zero, 28(sp) |
| ; RV32I-NEXT: mv a7, sp |
| ; RV32I-NEXT: srli a5, a5, 16 |
| ; RV32I-NEXT: addi a6, a6, 111 |
| ; RV32I-NEXT: or a1, a5, a1 |
| ; RV32I-NEXT: sub a2, a6, a2 |
| ; RV32I-NEXT: sw a4, 0(sp) |
| ; RV32I-NEXT: sw a3, 4(sp) |
| ; RV32I-NEXT: sw a0, 8(sp) |
| ; RV32I-NEXT: sw a1, 12(sp) |
| ; RV32I-NEXT: srli a0, a2, 3 |
| ; RV32I-NEXT: andi a0, a0, 12 |
| ; RV32I-NEXT: add a0, a7, a0 |
| ; RV32I-NEXT: lw a1, 4(a0) |
| ; RV32I-NEXT: lw a3, 8(a0) |
| ; RV32I-NEXT: lw a4, 12(a0) |
| ; RV32I-NEXT: lw a0, 0(a0) |
| ; RV32I-NEXT: andi a5, a2, 31 |
| ; RV32I-NEXT: xori a5, a5, 31 |
| ; RV32I-NEXT: slli a6, a4, 1 |
| ; RV32I-NEXT: slli a7, a3, 1 |
| ; RV32I-NEXT: slli t0, a1, 1 |
| ; RV32I-NEXT: sll a6, a6, a5 |
| ; RV32I-NEXT: sll a7, a7, a5 |
| ; RV32I-NEXT: sll a5, t0, a5 |
| ; RV32I-NEXT: srl a3, a3, a2 |
| ; RV32I-NEXT: srl a1, a1, a2 |
| ; RV32I-NEXT: srl a0, a0, a2 |
| ; RV32I-NEXT: or s4, a3, a6 |
| ; RV32I-NEXT: or s5, a1, a7 |
| ; RV32I-NEXT: or s6, a0, a5 |
| ; RV32I-NEXT: srl s7, a4, a2 |
| ; RV32I-NEXT: mv a0, s6 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s2 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: mv s3, a0 |
| ; RV32I-NEXT: mv s8, a1 |
| ; RV32I-NEXT: mv a0, s5 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s2 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: add s8, a0, s8 |
| ; RV32I-NEXT: sltu a0, s8, a0 |
| ; RV32I-NEXT: add s9, a1, a0 |
| ; RV32I-NEXT: mv a0, s6 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s1 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: add s8, a0, s8 |
| ; RV32I-NEXT: sltu a0, s8, a0 |
| ; RV32I-NEXT: add s10, a1, a0 |
| ; RV32I-NEXT: mv a0, s5 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s1 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: add a0, a0, s9 |
| ; RV32I-NEXT: add s10, a0, s10 |
| ; RV32I-NEXT: mv a0, s1 |
| ; RV32I-NEXT: mv a2, s6 |
| ; RV32I-NEXT: mv a3, s5 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: mv s5, a0 |
| ; RV32I-NEXT: mv a0, s2 |
| ; RV32I-NEXT: mv a1, s1 |
| ; RV32I-NEXT: mv a2, s4 |
| ; RV32I-NEXT: mv a3, s7 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: add a0, s5, a0 |
| ; RV32I-NEXT: add a0, s10, a0 |
| ; RV32I-NEXT: j .LBB5_5 |
| ; RV32I-NEXT: .LBB5_4: # %fp-to-i-if-exp.large |
| ; RV32I-NEXT: sw zero, 32(sp) |
| ; RV32I-NEXT: sw zero, 36(sp) |
| ; RV32I-NEXT: sw zero, 40(sp) |
| ; RV32I-NEXT: sw zero, 44(sp) |
| ; RV32I-NEXT: sw a4, 48(sp) |
| ; RV32I-NEXT: sw a3, 52(sp) |
| ; RV32I-NEXT: sw a0, 56(sp) |
| ; RV32I-NEXT: lui a0, 1048572 |
| ; RV32I-NEXT: addi a1, sp, 48 |
| ; RV32I-NEXT: addi a0, a0, -111 |
| ; RV32I-NEXT: add a0, a2, a0 |
| ; RV32I-NEXT: srli a2, a0, 3 |
| ; RV32I-NEXT: andi a3, a0, 31 |
| ; RV32I-NEXT: andi a2, a2, 12 |
| ; RV32I-NEXT: xori a3, a3, 31 |
| ; RV32I-NEXT: sub a1, a1, a2 |
| ; RV32I-NEXT: lw a4, 0(a1) |
| ; RV32I-NEXT: lw a2, 4(a1) |
| ; RV32I-NEXT: lw a5, 8(a1) |
| ; RV32I-NEXT: lw a1, 12(a1) |
| ; RV32I-NEXT: srli a6, a4, 1 |
| ; RV32I-NEXT: srli a7, a2, 1 |
| ; RV32I-NEXT: srli t0, a5, 1 |
| ; RV32I-NEXT: srl a6, a6, a3 |
| ; RV32I-NEXT: srl a7, a7, a3 |
| ; RV32I-NEXT: srl a3, t0, a3 |
| ; RV32I-NEXT: sll a2, a2, a0 |
| ; RV32I-NEXT: sll a5, a5, a0 |
| ; RV32I-NEXT: sll a1, a1, a0 |
| ; RV32I-NEXT: or s4, a2, a6 |
| ; RV32I-NEXT: or a2, a5, a7 |
| ; RV32I-NEXT: or a3, a1, a3 |
| ; RV32I-NEXT: sll s5, a4, a0 |
| ; RV32I-NEXT: mv a0, s2 |
| ; RV32I-NEXT: mv a1, s1 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: mv s3, a0 |
| ; RV32I-NEXT: mv a0, s1 |
| ; RV32I-NEXT: mv a2, s5 |
| ; RV32I-NEXT: mv a3, s4 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: add s9, a0, s3 |
| ; RV32I-NEXT: mv a0, s4 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s2 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: mv s6, a0 |
| ; RV32I-NEXT: mv s7, a1 |
| ; RV32I-NEXT: mv a0, s5 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s2 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: mv s3, a0 |
| ; RV32I-NEXT: add s8, s6, a1 |
| ; RV32I-NEXT: sltu a0, s8, s6 |
| ; RV32I-NEXT: add s7, s7, a0 |
| ; RV32I-NEXT: mv a0, s5 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s1 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: add s8, a0, s8 |
| ; RV32I-NEXT: sltu a0, s8, a0 |
| ; RV32I-NEXT: add s2, a1, a0 |
| ; RV32I-NEXT: mv a0, s4 |
| ; RV32I-NEXT: li a1, 0 |
| ; RV32I-NEXT: mv a2, s1 |
| ; RV32I-NEXT: li a3, 0 |
| ; RV32I-NEXT: call __muldi3 |
| ; RV32I-NEXT: add a0, a0, s7 |
| ; RV32I-NEXT: add a0, a0, s2 |
| ; RV32I-NEXT: add a0, a0, s9 |
| ; RV32I-NEXT: .LBB5_5: # %fp-to-i-cleanup |
| ; RV32I-NEXT: sw s3, 0(s0) |
| ; RV32I-NEXT: sw s8, 4(s0) |
| ; RV32I-NEXT: sw a0, 8(s0) |
| ; RV32I-NEXT: lw ra, 108(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s0, 104(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s1, 100(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s2, 96(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s3, 92(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s4, 88(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s5, 84(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s6, 80(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s7, 76(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s8, 72(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s9, 68(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: lw s10, 64(sp) # 4-byte Folded Reload |
| ; RV32I-NEXT: addi sp, sp, 112 |
| ; RV32I-NEXT: ret |
| %result = fptosi fp128 %a to i96 |
| ret i96 %result |
| } |
