llvm/test/CodeGen/RISCV/cf-branch-isel.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 -stop-after=finalize-isel < %s \
; RUN:   | FileCheck %s --implicit-check-not=PseudoBRINDX7 \
; RUN:     --implicit-check-not=PseudoCALLIndirectX7 \
; RUN:     --implicit-check-not=PseudoTAILIndirectX7

; Test that with cf-protection-branch enabled, indirect branches/calls select
; the non-X7 variants to avoid using X7 for the target address.

@brind.arr = internal unnamed_addr constant [2 x ptr] [ptr blockaddress(@brind, %bb1), ptr blockaddress(@brind, %bb2)], align 8
@x = dso_local global i32 0, align 4

define void @brind(i32 noundef signext %0) {
  ; CHECK-LABEL: name: brind
  ; CHECK: PseudoBRIND killed %{{[0-9]+}}, 0
  %2 = sext i32 %0 to i64
  %3 = getelementptr inbounds [2 x ptr], ptr @brind.arr, i64 0, i64 %2
  %4 = load ptr, ptr %3, align 8
  indirectbr ptr %4, [label %bb1, label %bb2]

bb1:
  %5 = load i32, ptr @x, align 4
  %6 = add nsw i32 %5, 2
  store i32 %6, ptr @x, align 4
  br label %bb2

bb2:
  %7 = load i32, ptr @x, align 4
  %8 = add nsw i32 %7, 1
  store i32 %8, ptr @x, align 4
  ret void
}

define i32 @indirect_call(ptr %0) {
  ; CHECK-LABEL: name: indirect_call
  ; CHECK: PseudoCALLIndirect %{{[0-9]+}},
  call void %0()
  ret i32 0
}

define void @indirect_tail(ptr %0) {
  ; CHECK-LABEL: name: indirect_tail
  ; CHECK: PseudoTAILIndirect %{{[0-9]+}},
  tail call void %0()
  ret void
}

!llvm.module.flags = !{!0}
!0 = !{i32 8, !"cf-protection-branch", i32 1}