llvm/test/CodeGen/PowerPC/post-quantum-crypto.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN:   -mcpu=future < %s | FileCheck %s

; Test Post Quantum Cryptography Acceleration instructions

define <4 x i32> @test_xvadduwm(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_xvadduwm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvadduwm 34, 34, 35
; CHECK-NEXT:    blr
  %res = add <4 x i32> %a, %b
  ret <4 x i32> %res
}

define <8 x i16> @test_xvadduhm(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_xvadduhm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvadduhm 34, 34, 35
; CHECK-NEXT:    blr
  %res = add <8 x i16> %a, %b
  ret <8 x i16> %res
}

define <4 x i32> @test_xvsubuwm(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_xvsubuwm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvsubuwm 34, 34, 35
; CHECK-NEXT:    blr
  %res = sub <4 x i32> %a, %b
  ret <4 x i32> %res
}

define <8 x i16> @test_xvsubuhm(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_xvsubuhm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvsubuhm 34, 34, 35
; CHECK-NEXT:    blr
  %res = sub <8 x i16> %a, %b
  ret <8 x i16> %res
}

define <4 x i32> @test_xvmuluwm(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_xvmuluwm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvmuluwm 34, 34, 35
; CHECK-NEXT:    blr
  %res = mul <4 x i32> %a, %b
  ret <4 x i32> %res
}

define <8 x i16> @test_xvmuluhm(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_xvmuluhm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvmuluhm 34, 34, 35
; CHECK-NEXT:    blr
  %res = mul <8 x i16> %a, %b
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>)
define <4 x i32> @test_xvmulhsw(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_xvmulhsw:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvmulhsw 34, 34, 35
; CHECK-NEXT:    blr
  %res = call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b)
  ret <4 x i32> %res
}

declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>)
define <4 x i32> @test_xvmulhuw(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_xvmulhuw:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvmulhuw 34, 34, 35
; CHECK-NEXT:    blr
  %res = call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b)
  ret <4 x i32> %res
}

declare <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16>, <8 x i16>)
define <8 x i16> @test_xvmulhsh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_xvmulhsh:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvmulhsh 34, 34, 35
; CHECK-NEXT:    blr
  %res = call <8 x i16> @llvm.ppc.altivec.vmulhsh(<8 x i16> %a, <8 x i16> %b)
  ret <8 x i16> %res
}

declare <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16>, <8 x i16>)
define <8 x i16> @test_xvmulhuh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_xvmulhuh:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvmulhuh 34, 34, 35
; CHECK-NEXT:    blr
  %res = call <8 x i16> @llvm.ppc.altivec.vmulhuh(<8 x i16> %a, <8 x i16> %b)
  ret <8 x i16> %res
}