llvm/test/CodeGen/NVPTX/misched_func_call.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -O3 -mtriple=nvptx64 -enable-misched %s -o - | FileCheck %s

target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-nvidia-cuda"

define ptx_kernel void @wombat(i32 %arg, i32 %arg1, i32 %arg2) {
; CHECK-LABEL: wombat(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<8>;
; CHECK-NEXT:    .reg .b64 %rd<5>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0: // %bb
; CHECK-NEXT:    ld.param.b32 %r3, [wombat_param_2];
; CHECK-NEXT:    ld.param.b32 %r2, [wombat_param_1];
; CHECK-NEXT:    ld.param.b32 %r1, [wombat_param_0];
; CHECK-NEXT:    mov.b32 %r7, 0;
; CHECK-NEXT:  $L__BB0_1: // %bb3
; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    { // callseq 0, 0
; CHECK-NEXT:    .param .b64 param0;
; CHECK-NEXT:    .param .b64 retval0;
; CHECK-NEXT:    st.param.b64 [param0], 0;
; CHECK-NEXT:    call.uni (retval0), quux, (param0);
; CHECK-NEXT:    } // callseq 0
; CHECK-NEXT:    mul.lo.s32 %r4, %r7, %r2;
; CHECK-NEXT:    or.b32 %r5, %r3, %r4;
; CHECK-NEXT:    mul.lo.s32 %r6, %r1, %r5;
; CHECK-NEXT:    cvt.rn.f64.s32 %rd1, %r6;
; CHECK-NEXT:    cvt.rn.f64.u32 %rd2, %r7;
; CHECK-NEXT:    add.rn.f64 %rd3, %rd2, %rd1;
; CHECK-NEXT:    mov.b64 %rd4, 0;
; CHECK-NEXT:    st.global.b64 [%rd4], %rd3;
; CHECK-NEXT:    mov.b32 %r7, 1;
; CHECK-NEXT:    bra.uni $L__BB0_1;
bb:
  br label %bb3

bb3:                                              ; preds = %bb3, %bb
  %phi = phi i32 [ 0, %bb ], [ 1, %bb3 ]
  %call = tail call double @quux(double 0.000000e+00)
  %mul = mul i32 %phi, %arg1
  %or = or i32 %arg2, %mul
  %mul4 = mul i32 %arg, %or
  %sitofp = sitofp i32 %mul4 to double
  %uitofp = uitofp i32 %phi to double
  %fadd = fadd double %uitofp, %sitofp
  store double %fadd, ptr addrspace(1) null, align 8
  br label %bb3
}

declare double @quux(double)