llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s

---
name:            sgpr_spill_initial_insert_in_latch_moves_to_preheader
tracksRegLiveness: true
frameInfo:
  maxAlignment:    4
stack:
  - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
machineFunctionInfo:
  isEntryFunction: false
  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
  stackPtrOffsetReg: '$sgpr32'
  frameOffsetReg: '$sgpr33'
  hasSpilledSGPRs: true
body:             |
  ; SGPR-SPILL-LABEL: name: sgpr_spill_initial_insert_in_latch_moves_to_preheader
  ; SGPR-SPILL: bb.0:
  ; SGPR-SPILL-NEXT:   successors: %bb.1(0x80000000)
  ; SGPR-SPILL-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
  ; SGPR-SPILL-NEXT: {{  $}}
  ; SGPR-SPILL-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; SGPR-SPILL-NEXT:   S_BRANCH %bb.1
  ; SGPR-SPILL-NEXT: {{  $}}
  ; SGPR-SPILL-NEXT: bb.1:
  ; SGPR-SPILL-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; SGPR-SPILL-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
  ; SGPR-SPILL-NEXT: {{  $}}
  ; SGPR-SPILL-NEXT:   S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
  ; SGPR-SPILL-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit killed $scc
  ; SGPR-SPILL-NEXT:   S_BRANCH %bb.3
  ; SGPR-SPILL-NEXT: {{  $}}
  ; SGPR-SPILL-NEXT: bb.2:
  ; SGPR-SPILL-NEXT:   successors: %bb.1(0x80000000)
  ; SGPR-SPILL-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
  ; SGPR-SPILL-NEXT: {{  $}}
  ; SGPR-SPILL-NEXT:   $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
  ; SGPR-SPILL-NEXT:   $sgpr10 = S_MOV_B32 1
  ; SGPR-SPILL-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
  ; SGPR-SPILL-NEXT:   S_BRANCH %bb.1
  ; SGPR-SPILL-NEXT: {{  $}}
  ; SGPR-SPILL-NEXT: bb.3:
  ; SGPR-SPILL-NEXT:   liveins: $sgpr30_sgpr31
  ; SGPR-SPILL-NEXT: {{  $}}
  ; SGPR-SPILL-NEXT:   S_SETPC_B64 $sgpr30_sgpr31
  bb.0:
    liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
    S_BRANCH %bb.1
  bb.1:
    liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
    S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
    S_CBRANCH_SCC1 %bb.2, implicit killed $scc
    S_BRANCH %bb.3
  bb.2:
    liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
    renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
    $sgpr10 = S_MOV_B32 1
    SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
    S_BRANCH %bb.1
  bb.3:
    liveins: $sgpr30_sgpr31
    S_SETPC_B64 $sgpr30_sgpr31