llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s

---
name:              lcssa_phi
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: lcssa_phi
  ; GCN: bb.0:
  ; GCN-NEXT:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
  ; GCN-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   [[DEF2:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF [[DEF]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; GCN-NEXT:   S_BRANCH %bb.1
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.1:
  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %9, %bb.1
  ; GCN-NEXT:   [[PHI1:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_]], %bb.0, %5, %bb.1
  ; GCN-NEXT:   [[DEF3:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK [[DEF3]], [[PHI1]], implicit-def dead $scc
  ; GCN-NEXT:   [[DEF4:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   [[S_ANDN2_B64_:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[PHI]], $exec, implicit-def $scc
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY [[S_ANDN2_B64_]]
  ; GCN-NEXT:   SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; GCN-NEXT:   S_BRANCH %bb.2
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.2:
  ; GCN-NEXT:   successors: %bb.3(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.3:
  ; GCN-NEXT:   [[PHI2:%[0-9]+]]:sreg_64 = PHI [[DEF2]], %bb.0, [[S_ANDN2_B64_]], %bb.2
  ; GCN-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; GCN-NEXT:   S_ENDPGM 0
  bb.0:
    %0:sreg_64 = S_MOV_B64 0
    %8:vreg_1 = IMPLICIT_DEF
    %10:sreg_64 = IMPLICIT_DEF
    %11:sreg_64 = SI_IF %10, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %1:sreg_64 = PHI %0, %bb.0, %3, %bb.1
    %2:sreg_64 = IMPLICIT_DEF
    %3:sreg_64 = SI_IF_BREAK %2, %1, implicit-def dead $scc
    %4:sreg_64 = IMPLICIT_DEF
    %5:vreg_1 = COPY %4
    SI_LOOP %3, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.2

  bb.2:
    %6:vreg_1 = PHI %5, %bb.1
    SI_END_CF %3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec

  bb.3:
    %7:vreg_1 = PHI %6, %bb.2, %8, %bb.0
    SI_END_CF %11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0

...
---
name:            copy_observed_outside_loop
tracksRegLiveness: true
noPhis:          false

body:             |
  ; GCN-LABEL: name: copy_observed_outside_loop
  ; GCN: bb.0:
  ; GCN-NEXT:   successors: %bb.1(0x80000000)
  ; GCN-NEXT:   liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr31
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.1:
  ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %1, %bb.1, %5, %bb.3
  ; GCN-NEXT:   [[S_ANDN2_B64_:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[PHI]], $exec, implicit-def $scc
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY [[S_ANDN2_B64_]]
  ; GCN-NEXT:   SI_LOOP undef [[DEF]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; GCN-NEXT:   S_BRANCH %bb.2
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.2:
  ; GCN-NEXT:   successors: %bb.5(0x40000000), %bb.3(0x40000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_64 = COPY undef [[COPY]]
  ; GCN-NEXT:   [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF undef [[COPY1]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; GCN-NEXT:   S_BRANCH %bb.5
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.3:
  ; GCN-NEXT:   successors: %bb.4(0x40000000), %bb.1(0x40000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[DEF2:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   SI_LOOP undef [[SI_IF]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; GCN-NEXT:   S_BRANCH %bb.4
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.4:
  ; GCN-NEXT:   SI_RETURN
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.5:
  ; GCN-NEXT:   successors: %bb.3(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   S_BRANCH %bb.3
  bb.0:
    successors: %bb.1
    liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr31

    %42:sreg_64 = IMPLICIT_DEF

  bb.1:
    successors: %bb.2, %bb.1

    %2:vreg_1 = COPY undef %42
    SI_LOOP undef %42, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.2

  bb.2:
    successors: %bb.5, %bb.3

    %24:sreg_64 = COPY undef %2
    %4:sreg_64 = SI_IF undef %24, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.5

  bb.3:
    successors: %bb.4, %bb.1

    SI_LOOP undef %4, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.4

  bb.4:
    SI_RETURN

  bb.5:
    successors: %bb.3

    S_BRANCH %bb.3