| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s |
| ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s |
| ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s |
| ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s |
| |
| ; =================================================================================== |
| ; V_OR3_B32 |
| ; =================================================================================== |
| |
| define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) { |
| ; VI-LABEL: or3: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: ; return to shader part epilog |
| ; |
| ; GFX9-LABEL: or3: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 |
| ; GFX9-NEXT: ; return to shader part epilog |
| ; |
| ; GFX10-LABEL: or3: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 |
| ; GFX10-NEXT: ; return to shader part epilog |
| %x = or i32 %a, %b |
| %result = or i32 %x, %c |
| %bc = bitcast i32 %result to float |
| ret float %bc |
| } |
| |
| ; ThreeOp instruction variant not used due to Constant Bus Limitations |
| ; TODO: with reassociation it is possible to replace a v_or_b32_e32 with an s_or_b32 |
| define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) { |
| ; VI-LABEL: or3_vgpr_a: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: v_or_b32_e32 v0, s2, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, s3, v0 |
| ; VI-NEXT: ; return to shader part epilog |
| ; |
| ; GFX9-LABEL: or3_vgpr_a: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: v_or_b32_e32 v0, s2, v0 |
| ; GFX9-NEXT: v_or_b32_e32 v0, s3, v0 |
| ; GFX9-NEXT: ; return to shader part epilog |
| ; |
| ; GFX10-LABEL: or3_vgpr_a: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: v_or3_b32 v0, v0, s2, s3 |
| ; GFX10-NEXT: ; return to shader part epilog |
| %x = or i32 %a, %b |
| %result = or i32 %x, %c |
| %bc = bitcast i32 %result to float |
| ret float %bc |
| } |
| |
| define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) { |
| ; VI-LABEL: or3_vgpr_all2: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: ; return to shader part epilog |
| ; |
| ; GFX9-LABEL: or3_vgpr_all2: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0 |
| ; GFX9-NEXT: ; return to shader part epilog |
| ; |
| ; GFX10-LABEL: or3_vgpr_all2: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0 |
| ; GFX10-NEXT: ; return to shader part epilog |
| %x = or i32 %b, %c |
| %result = or i32 %a, %x |
| %bc = bitcast i32 %result to float |
| ret float %bc |
| } |
| |
| define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) { |
| ; VI-LABEL: or3_vgpr_bc: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: v_or_b32_e32 v0, s2, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: ; return to shader part epilog |
| ; |
| ; GFX9-LABEL: or3_vgpr_bc: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: v_or3_b32 v0, s2, v0, v1 |
| ; GFX9-NEXT: ; return to shader part epilog |
| ; |
| ; GFX10-LABEL: or3_vgpr_bc: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: v_or3_b32 v0, s2, v0, v1 |
| ; GFX10-NEXT: ; return to shader part epilog |
| %x = or i32 %a, %b |
| %result = or i32 %x, %c |
| %bc = bitcast i32 %result to float |
| ret float %bc |
| } |
| |
| define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) { |
| ; VI-LABEL: or3_vgpr_const: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, 64, v0 |
| ; VI-NEXT: ; return to shader part epilog |
| ; |
| ; GFX9-LABEL: or3_vgpr_const: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: v_or3_b32 v0, v1, v0, 64 |
| ; GFX9-NEXT: ; return to shader part epilog |
| ; |
| ; GFX10-LABEL: or3_vgpr_const: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: v_or3_b32 v0, v1, v0, 64 |
| ; GFX10-NEXT: ; return to shader part epilog |
| %x = or i32 64, %b |
| %result = or i32 %x, %a |
| %bc = bitcast i32 %result to float |
| ret float %bc |
| } |
| |
| define <2 x i32> @v_or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) { |
| ; VI-LABEL: v_or3_v2i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v5 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: v_or3_v2i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_or3_b32 v1, v1, v3, v5 |
| ; GFX9-NEXT: v_or3_b32 v0, v0, v2, v4 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: v_or3_v2i32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_or3_b32 v0, v0, v2, v4 |
| ; GFX10-NEXT: v_or3_b32 v1, v1, v3, v5 |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| %x = or <2 x i32> %a, %b |
| %result = or <2 x i32> %x, %c |
| ret <2 x i32> %result |
| } |
| |
| ; ThreeOp instruction variant not used due to Constant Bus Limitations |
| define <2 x i32> @v_or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) { |
| ; VI-LABEL: v_or3_v2i32_b: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_or_b32_e32 v1, s17, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, s16, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, s19, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, s18, v0 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: v_or3_v2i32_b: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_or_b32_e32 v1, s17, v1 |
| ; GFX9-NEXT: v_or_b32_e32 v0, s16, v0 |
| ; GFX9-NEXT: v_or_b32_e32 v1, s19, v1 |
| ; GFX9-NEXT: v_or_b32_e32 v0, s18, v0 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: v_or3_v2i32_b: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-DAG: v_or3_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}} |
| ; GFX10-DAG: v_or3_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}} |
| %x = or <2 x i32> %a, %b |
| %result = or <2 x i32> %x, %c |
| ret <2 x i32> %result |
| } |
| |
| define <2 x i32> @v_or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) { |
| ; VI-LABEL: v_or3_v2i32_ab: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, s17, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, s16, v0 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: v_or3_v2i32_ab: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_or3_b32 v1, v1, v3, s17 |
| ; GFX9-NEXT: v_or3_b32 v0, v0, v2, s16 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: v_or3_v2i32_ab: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-DAG: v_or3_b32 v0, v0, v2, s{{[0-9]+}} |
| ; GFX10-DAG: v_or3_b32 v1, v1, v3, s{{[0-9]+}} |
| %x = or <2 x i32> %a, %b |
| %result = or <2 x i32> %x, %c |
| ret <2 x i32> %result |
| } |
| |
| define <2 x i32> @v_or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) { |
| ; VI-LABEL: v_or3_v2i32_const: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, 16, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, 4, v0 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: v_or3_v2i32_const: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_or3_b32 v1, v1, v3, 16 |
| ; GFX9-NEXT: v_or3_b32 v0, v0, v2, 4 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: v_or3_v2i32_const: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_or3_b32 v0, v0, v2, 4 |
| ; GFX10-NEXT: v_or3_b32 v1, v1, v3, 16 |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| %x = or <2 x i32> %a, <i32 4, i32 16> |
| %result = or <2 x i32> %x, %b |
| ret <2 x i32> %result |
| } |
| |
| define <2 x i32> @v_or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) { |
| ; VI-LABEL: v_or3_v2i32_inline_const: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, 0x809, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, 0x808, v0 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: v_or3_v2i32_inline_const: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: s_movk_i32 s4, 0x809 |
| ; GFX9-NEXT: v_or3_b32 v1, v1, v3, s4 |
| ; GFX9-NEXT: s_movk_i32 s4, 0x808 |
| ; GFX9-NEXT: v_or3_b32 v0, v0, v2, s4 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: v_or3_v2i32_inline_const: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_or3_b32 v0, v0, v2, 0x808 |
| ; GFX10-NEXT: v_or3_b32 v1, v1, v3, 0x809 |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| %x = or <2 x i32> %a, <i32 2056, i32 2057> |
| %result = or <2 x i32> %x, %b |
| ret <2 x i32> %result |
| } |
| |
| define <2 x i32> @v_or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) { |
| ; VI-LABEL: v_or3_v2i32_multi_use: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v1, v5 |
| ; VI-NEXT: v_or_b32_e32 v3, v0, v4 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v3 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2 |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: v_or3_v2i32_multi_use: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; GFX9-NEXT: v_or_b32_e32 v2, v1, v5 |
| ; GFX9-NEXT: v_or_b32_e32 v3, v0, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: v_or3_v2i32_multi_use: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; GFX10-NEXT: v_or_b32_e32 v2, v0, v4 |
| ; GFX10-NEXT: v_or_b32_e32 v3, v1, v5 |
| ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 |
| ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| %x = or <2 x i32> %a, %b |
| %y = or <2 x i32> %x, %c |
| %result = add <2 x i32> %x, %y |
| ret <2 x i32> %result |
| } |
| |
| define amdgpu_ps <2 x i32> @s_or3_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) { |
| ; VI-LABEL: s_or3_v2i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] |
| ; VI-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7] |
| ; VI-NEXT: ; return to shader part epilog |
| ; |
| ; GFX9-LABEL: s_or3_v2i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] |
| ; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7] |
| ; GFX9-NEXT: ; return to shader part epilog |
| ; |
| ; GFX10-LABEL: s_or3_v2i32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] |
| ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7] |
| ; GFX10-NEXT: ; return to shader part epilog |
| %x = or <2 x i32> %a, %b |
| %result = or <2 x i32> %x, %c |
| ret <2 x i32> %result |
| } |
