llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6

# Ensure processing an IMPLICIT_DEF of a physreg updates all uses
# before removing the IMPLICIT_DEF.  -verify-machineinstrs will
# fail otherwise.

# RUN: llc -mtriple=amdgcn -mcpu=gfx802  -run-pass processimpdefs -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck %s

---

name: implicit_def_multiple_use
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: implicit_def_multiple_use
    ; CHECK: $vgpr1_lo16 = COPY undef $vgpr0_hi16
    ; CHECK-NEXT: $vgpr1_hi16 = COPY undef $vgpr0_lo16
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr0 = IMPLICIT_DEF
    $vgpr1_lo16 = COPY $vgpr0_hi16
    $vgpr1_hi16 = COPY $vgpr0_lo16
    S_ENDPGM 0
...

# IMPLICIT_DEF processing Will not search across basic-blocks for uses.  IMPLICIT_DEF must not be deleted.
---

name: implicit_def_cannot_find_all_uses
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: implicit_def_cannot_find_all_uses
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = IMPLICIT_DEF
  ; CHECK-NEXT:   $vgpr1_lo16 = COPY undef $vgpr0_hi16
  ; CHECK-NEXT:   $vgpr1_hi16 = COPY undef $vgpr0_lo16
  ; CHECK-NEXT:   $scc = IMPLICIT_DEF
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.0, implicit undef $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  bb.0:
    $vgpr0 = IMPLICIT_DEF
    $vgpr1_lo16 = COPY $vgpr0_hi16
    $vgpr1_hi16 = COPY $vgpr0_lo16
    $scc = IMPLICIT_DEF
    S_CBRANCH_SCC1 %bb.0, implicit $scc
  bb.1:
...