llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s

declare void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3))

define void @test_ds_atomic_async_barrier_arrive_b64(ptr addrspace(3) %bar) {
; GCN-LABEL: test_ds_atomic_async_barrier_arrive_b64:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
; GCN-NEXT:    ds_atomic_async_barrier_arrive_b64 v0
; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
; GCN-NEXT:    s_set_pc_i64 s[30:31]
entry:
  call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
  ret void
}

define void @test_ds_atomic_async_barrier_arrive_b64_off(ptr addrspace(3) %in) {
; GCN-LABEL: test_ds_atomic_async_barrier_arrive_b64_off:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
; GCN-NEXT:    ds_atomic_async_barrier_arrive_b64 v0 offset:8184
; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
; GCN-NEXT:    s_set_pc_i64 s[30:31]
entry:
  %bar = getelementptr i64, ptr addrspace(3) %in, i32 1023
  call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
  ret void
}

define amdgpu_ps void @test_ds_atomic_async_barrier_arrive_b64_s(ptr addrspace(3) inreg %bar) {
; GCN-LABEL: test_ds_atomic_async_barrier_arrive_b64_s:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GCN-NEXT:    v_mov_b32_e32 v0, s0
; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
; GCN-NEXT:    ds_atomic_async_barrier_arrive_b64 v0
; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
; GCN-NEXT:    s_endpgm
entry:
  call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
  ret void
}