llvm/test/CodeGen/AMDGPU/and_or.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s
;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s

; ===================================================================================
; V_AND_OR_B32
; ===================================================================================

define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
; VI-LABEL: and_or:
; VI:       ; %bb.0:
; VI-NEXT:    v_and_b32_e32 v0, v0, v1
; VI-NEXT:    v_or_b32_e32 v0, v0, v2
; VI-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: and_or:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, v2
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: and_or:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, v2
; GFX10-NEXT:    ; return to shader part epilog
  %x = and i32 %a, %b
  %result = or i32 %x, %c
  %bc = bitcast i32 %result to float
  ret float %bc
}

; ThreeOp instruction variant not used due to Constant Bus Limitations
define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
; VI-LABEL: and_or_vgpr_b:
; VI:       ; %bb.0:
; VI-NEXT:    v_and_b32_e32 v0, s2, v0
; VI-NEXT:    v_or_b32_e32 v0, s3, v0
; VI-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_b:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_b:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_and_or_b32 v0, s2, v0, s3
; GFX10-NEXT:    ; return to shader part epilog
  %x = and i32 %a, %b
  %result = or i32 %x, %c
  %bc = bitcast i32 %result to float
  ret float %bc
}

define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
; VI-LABEL: and_or_vgpr_ab:
; VI:       ; %bb.0:
; VI-NEXT:    v_and_b32_e32 v0, v0, v1
; VI-NEXT:    v_or_b32_e32 v0, s2, v0
; VI-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_ab:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, s2
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_ab:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, s2
; GFX10-NEXT:    ; return to shader part epilog
  %x = and i32 %a, %b
  %result = or i32 %x, %c
  %bc = bitcast i32 %result to float
  ret float %bc
}

define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
; VI-LABEL: and_or_vgpr_const:
; VI:       ; %bb.0:
; VI-NEXT:    v_and_b32_e32 v0, 4, v0
; VI-NEXT:    v_or_b32_e32 v0, v0, v1
; VI-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v1
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_const:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v1
; GFX10-NEXT:    ; return to shader part epilog
  %x = and i32 4, %a
  %result = or i32 %x, %b
  %bc = bitcast i32 %result to float
  ret float %bc
}

define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
; VI-LABEL: and_or_vgpr_const_inline_const:
; VI:       ; %bb.0:
; VI-NEXT:    v_and_b32_e32 v0, 20, v0
; VI-NEXT:    v_or_b32_e32 v0, 0x808, v0
; VI-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_const_inline_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x808
; GFX9-NEXT:    v_and_or_b32 v0, v0, 20, v1
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_const_inline_const:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_and_or_b32 v0, v0, 20, 0x808
; GFX10-NEXT:    ; return to shader part epilog
  %x = and i32 20, %a
  %result = or i32 %x, 2056
  %bc = bitcast i32 %result to float
  ret float %bc
}

define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
; VI-LABEL: and_or_vgpr_inline_const_x2:
; VI:       ; %bb.0:
; VI-NEXT:    v_and_b32_e32 v0, 4, v0
; VI-NEXT:    v_or_b32_e32 v0, 1, v0
; VI-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: and_or_vgpr_inline_const_x2:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, 1
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: and_or_vgpr_inline_const_x2:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, 1
; GFX10-NEXT:    ; return to shader part epilog
  %x = and i32 4, %a
  %result = or i32 %x, 1
  %bc = bitcast i32 %result to float
  ret float %bc
}

define <2 x i32> @v_and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; VI-LABEL: v_and_or_v2i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, v1, v3
; VI-NEXT:    v_and_b32_e32 v0, v0, v2
; VI-NEXT:    v_or_b32_e32 v1, v1, v5
; VI-NEXT:    v_or_b32_e32 v0, v0, v4
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, v5
; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_and_or_b32 v0, v0, v2, v4
; GFX10-NEXT:    v_and_or_b32 v1, v1, v3, v5
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %x = and <2 x i32> %a, %b
  %result = or <2 x i32> %x, %c
  ret <2 x i32> %result
}

; ThreeOp instruction variant not used due to Constant Bus Limitations
define <2 x i32> @v_and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
; VI-LABEL: v_and_or_v2i32_b:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, s17, v1
; VI-NEXT:    v_and_b32_e32 v0, s16, v0
; VI-NEXT:    v_or_b32_e32 v1, s19, v1
; VI-NEXT:    v_or_b32_e32 v0, s18, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_b:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, s17, v1
; GFX9-NEXT:    v_and_b32_e32 v0, s16, v0
; GFX9-NEXT:    v_or_b32_e32 v1, s19, v1
; GFX9-NEXT:    v_or_b32_e32 v0, s18, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_b:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-DAG:     v_and_or_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
; GFX10-DAG:     v_and_or_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %x = and <2 x i32> %a, %b
  %result = or <2 x i32> %x, %c
  ret <2 x i32> %result
}

define <2 x i32> @v_and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
; VI-LABEL: v_and_or_v2i32_ab:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, v1, v3
; VI-NEXT:    v_and_b32_e32 v0, v0, v2
; VI-NEXT:    v_or_b32_e32 v1, s17, v1
; VI-NEXT:    v_or_b32_e32 v0, s16, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_ab:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, s17
; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, s16
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_ab:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-DAG:     v_and_or_b32 v1, v1, v3, {{s[0-9]+}}
; GFX10-DAG:     v_and_or_b32 v0, v0, v2, {{s[0-9]+}}
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %x = and <2 x i32> %a, %b
  %result = or <2 x i32> %x, %c
  ret <2 x i32> %result
}

define <2 x i32> @v_and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
; VI-LABEL: v_and_or_v2i32_const:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, 16, v1
; VI-NEXT:    v_and_b32_e32 v0, 4, v0
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_or_b32_e32 v0, v0, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_or_b32 v1, v1, 16, v3
; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_const:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v2
; GFX10-NEXT:    v_and_or_b32 v1, v1, 16, v3
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %x = and <2 x i32> %a, <i32 4, i32 16>
  %result = or <2 x i32> %x, %b
  ret <2 x i32> %result
}

define <2 x i32> @v_and_or_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
; VI-LABEL: v_and_or_v2i32_inline_const:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
; VI-NEXT:    v_or_b32_e32 v1, v1, v3
; VI-NEXT:    v_or_b32_e32 v0, v0, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_inline_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_movk_i32 s4, 0x809
; GFX9-NEXT:    v_and_or_b32 v1, v1, s4, v3
; GFX9-NEXT:    s_movk_i32 s4, 0x808
; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_inline_const:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_and_or_b32 v0, 0x808, v0, v2
; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, v3
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %x = and <2 x i32> %a, <i32 2056, i32 2057>
  %result = or <2 x i32> %x, %b
  ret <2 x i32> %result
}

define <2 x i32> @v_and_or_v2i32_inline_const_x2(<2 x i32> %a) {
; VI-LABEL: v_and_or_v2i32_inline_const_x2:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
; VI-NEXT:    v_or_b32_e32 v1, 16, v1
; VI-NEXT:    v_or_b32_e32 v0, 4, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_inline_const_x2:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
; GFX9-NEXT:    v_or_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_or_b32_e32 v0, 4, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_inline_const_x2:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_and_or_b32 v0, 0x808, v0, 4
; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, 16
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %x = and <2 x i32> %a, <i32 2056, i32 2057>
  %result = or <2 x i32> %x, <i32 4, i32 16>
  ret <2 x i32> %result
}

define <2 x i32> @v_and_or_v2i32_inline_const_x3(<2 x i32> %a) {
; VI-LABEL: v_and_or_v2i32_inline_const_x3:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
; VI-NEXT:    v_or_b32_e32 v1, 16, v1
; VI-NEXT:    v_or_b32_e32 v0, 0x81, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_inline_const_x3:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
; GFX9-NEXT:    v_or_b32_e32 v1, 16, v1
; GFX9-NEXT:    v_or_b32_e32 v0, 0x81, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_inline_const_x3:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_movk_i32 [[SR:s[0-9]+]], 0x808
; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR]], 0x81
; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, 16
  %x = and <2 x i32> %a, <i32 2056, i32 2057>
  %result = or <2 x i32> %x, <i32 129, i32 16>
  ret <2 x i32> %result
}

define <2 x i32> @v_and_or_v2i32_inline_const_x4(<2 x i32> %a) {
; VI-LABEL: v_and_or_v2i32_inline_const_x4:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
; VI-NEXT:    v_or_b32_e32 v1, 0x101, v1
; VI-NEXT:    v_or_b32_e32 v0, 0x81, v0
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_inline_const_x4:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
; GFX9-NEXT:    v_or_b32_e32 v1, 0x101, v1
; GFX9-NEXT:    v_or_b32_e32 v0, 0x81, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_inline_const_x4:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-DAG:     s_movk_i32 [[SR0:s[0-9]+]], 0x808
; GFX10-DAG:     s_movk_i32 [[SR1:s[0-9]+]], 0x809
; GFX10-CHECK-NOT: {{.}}
; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR0]], 0x81
; GFX10-DAG:     v_and_or_b32 v1, v1, [[SR1]], 0x101
  %x = and <2 x i32> %a, <i32 2056, i32 2057>
  %result = or <2 x i32> %x, <i32 129, i32 257>
  ret <2 x i32> %result
}

define <2 x i32> @v_and_or_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; VI-LABEL: v_and_or_v2i32_multi_use:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_and_b32_e32 v1, v1, v3
; VI-NEXT:    v_and_b32_e32 v0, v0, v2
; VI-NEXT:    v_or_b32_e32 v2, v1, v5
; VI-NEXT:    v_or_b32_e32 v3, v0, v4
; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v3
; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_and_or_v2i32_multi_use:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_and_b32_e32 v0, v0, v2
; GFX9-NEXT:    v_or_b32_e32 v2, v1, v5
; GFX9-NEXT:    v_or_b32_e32 v3, v0, v4
; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_and_or_v2i32_multi_use:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_and_b32_e32 v0, v0, v2
; GFX10-NEXT:    v_and_b32_e32 v1, v1, v3
; GFX10-NEXT:    v_or_b32_e32 v2, v0, v4
; GFX10-NEXT:    v_or_b32_e32 v3, v1, v5
; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %x = and <2 x i32> %a, %b
  %y = or <2 x i32> %x, %c
  %result = add <2 x i32> %x, %y
  ret <2 x i32> %result
}

define amdgpu_ps <2 x i32> @s_and_or_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
; VI-LABEL: s_and_or_v2i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
; VI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
; VI-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: s_and_or_v2i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: s_and_or_v2i32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
; GFX10-NEXT:    ; return to shader part epilog
  %x = and <2 x i32> %a, %b
  %result = or <2 x i32> %x, %c
  ret <2 x i32> %result
}