llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple aarch64 | FileCheck %s --check-prefix CHECK-LE
; RUN: llc < %s -mtriple aarch64_be | FileCheck %s --check-prefix CHECK-BE

; Note: Currently, interleaved stores are only directly supported on AArch64 for 64 bit or 128 bit vector data.

; Representative tests for each store type class where STNP shouldn't be lowered
; when optimizing for size.

define void @test_stnp_interleaved_store2_v2i32_Os(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #0 {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Os:
; CHECK-LE:       // %bb.0: // %entry
; CHECK-LE-NEXT:    // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
; CHECK-LE-NEXT:    st2 { v0.2s, v1.2s }, [x0]
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Os:
; CHECK-BE:       // %bb.0: // %entry
; CHECK-BE-NEXT:    rev64 v2.2s, v1.2s
; CHECK-BE-NEXT:    rev64 v1.2s, v0.2s
; CHECK-BE-NEXT:    st2 { v1.2s, v2.2s }, [x0]
; CHECK-BE-NEXT:    ret
entry:
  %shuffle = shufflevector <2 x i32> %v0, <2 x i32> %v1,
                    <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  store <4 x i32> %shuffle, ptr %ptr, align 4, !nontemporal !0
  ret void
}

define void @test_stnp_interleaved_store2_v2i32_Oz(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #1 {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Oz:
; CHECK-LE:       // %bb.0: // %entry
; CHECK-LE-NEXT:    // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
; CHECK-LE-NEXT:    st2 { v0.2s, v1.2s }, [x0]
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Oz:
; CHECK-BE:       // %bb.0: // %entry
; CHECK-BE-NEXT:    rev64 v2.2s, v1.2s
; CHECK-BE-NEXT:    rev64 v1.2s, v0.2s
; CHECK-BE-NEXT:    st2 { v1.2s, v2.2s }, [x0]
; CHECK-BE-NEXT:    ret
entry:
  %shuffle = shufflevector <2 x i32> %v0, <2 x i32> %v1,
                    <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  store <4 x i32> %shuffle, ptr %ptr, align 4, !nontemporal !0
  ret void
}

define void @test_stnp_interleaved_store2_v2i64_Os(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #0 {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Os:
; CHECK-LE:       // %bb.0: // %entry
; CHECK-LE-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-LE-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-LE-NEXT:    st2 { v0.2d, v1.2d }, [x0]
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Os:
; CHECK-BE:       // %bb.0: // %entry
; CHECK-BE-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    st2 { v1.2d, v2.2d }, [x0]
; CHECK-BE-NEXT:    ret
entry:
  %shuffle = shufflevector <2 x i64> %v0, <2 x i64> %v1,
                    <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  store <4 x i64> %shuffle, ptr %ptr, align 8, !nontemporal !0
  ret void
}

define void @test_stnp_interleaved_store2_v2i64_Oz(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #1 {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Oz:
; CHECK-LE:       // %bb.0: // %entry
; CHECK-LE-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-LE-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-LE-NEXT:    st2 { v0.2d, v1.2d }, [x0]
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Oz:
; CHECK-BE:       // %bb.0: // %entry
; CHECK-BE-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT:    st2 { v1.2d, v2.2d }, [x0]
; CHECK-BE-NEXT:    ret
entry:
  %shuffle = shufflevector <2 x i64> %v0, <2 x i64> %v1,
                    <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  store <4 x i64> %shuffle, ptr %ptr, align 8, !nontemporal !0
  ret void
}

!0 = !{ i32 1 }

attributes #0 = { optsize }
attributes #1 = { minsize optsize }