[VPlan] Fix find last reductions not using frozen condition in select (#223962)
A find last reduction is something like:
(select c[n], x[n], (select c[n-1], x[n-1], (select ...)))
So even if previous iterations had poison for c[x], the top-level select
blocks it.
MaskSelect uses the non-frozen Cond, and that in turn is fed into
VPInstruction::ExtractLastActive, which in turn gets expanded to
vector.reduce.umax, which returns poison if any of the lanes were
poison.
So in the case e.g. c[n] = 1, c[n-1] = poison and VF=2, the scalar loop
returns x[n] whilst vector loop returns poison.
We're also introducing multiple uses of Cond which isn't sound for
undef, so for these reasons we need to use the frozen Cond.diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
index 8f462e9..1d591eb 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
@@ -1941,9 +1941,8 @@
if (HeaderMask)
Cond = Builder.createLogicalAnd(HeaderMask, Cond);
- VPValue *AnyOf =
- Builder.createNaryOp(VPInstruction::AnyOf, Builder.createFreeze(Cond));
- // FIXME: The Cond here needs to be frozen too.
+ Cond = Builder.createFreeze(Cond);
+ VPValue *AnyOf = Builder.createNaryOp(VPInstruction::AnyOf, Cond);
VPValue *MaskSelect = Builder.createSelect(AnyOf, Cond, MaskPHI);
MaskPHI->addIncoming(MaskSelect);
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
index 4515d33..4af15b5 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
@@ -26,7 +26,7 @@
; CHECK-NEXT: [[TMP8:%.*]] = select <vscale x 4 x i1> [[ACTIVE_LANE_MASK]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = freeze <vscale x 4 x i1> [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP9]])
-; CHECK-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP8]], <vscale x 4 x i1> [[TMP5]]
+; CHECK-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP12]] = select i1 [[TMP10]], <vscale x 4 x i32> [[WIDE_MASKED_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP1]]
; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_NEXT]], i64 [[N]])
@@ -94,7 +94,7 @@
; CHECK-NEXT: [[WIDE_MASKED_LOAD3:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP9]], <vscale x 4 x i1> [[TMP8]], <vscale x 4 x i32> poison)
; CHECK-NEXT: [[TMP11:%.*]] = freeze <vscale x 4 x i1> [[TMP8]]
; CHECK-NEXT: [[TMP12:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP11]])
-; CHECK-NEXT: [[TMP13]] = select i1 [[TMP12]], <vscale x 4 x i1> [[TMP8]], <vscale x 4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP13]] = select i1 [[TMP12]], <vscale x 4 x i1> [[TMP11]], <vscale x 4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP14]] = select i1 [[TMP12]], <vscale x 4 x i32> [[WIDE_MASKED_LOAD3]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP1]]
; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_NEXT]], i64 [[N]])
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
index d197d72..ecb7fff 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
@@ -45,7 +45,7 @@
; SVE-NEXT: [[TMP13:%.*]] = icmp slt <vscale x 4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; SVE-NEXT: [[TMP7:%.*]] = freeze <vscale x 4 x i1> [[TMP13]]
; SVE-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP7]])
-; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP4]]
; SVE-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -135,7 +135,7 @@
; SVE-NEXT: [[TMP7:%.*]] = icmp slt <vscale x 2 x i64> [[BROADCAST_SPLAT]], [[TMP6]]
; SVE-NEXT: [[TMP8:%.*]] = freeze <vscale x 2 x i1> [[TMP7]]
; SVE-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[TMP8]])
-; SVE-NEXT: [[TMP10]] = select i1 [[TMP9]], <vscale x 2 x i1> [[TMP7]], <vscale x 2 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP10]] = select i1 [[TMP9]], <vscale x 2 x i1> [[TMP8]], <vscale x 2 x i1> [[TMP4]]
; SVE-NEXT: [[TMP11]] = select i1 [[TMP9]], <vscale x 2 x ptr> [[WIDE_LOAD]], <vscale x 2 x ptr> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP1]]
; SVE-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -203,7 +203,7 @@
; NEON-NEXT: [[TMP2:%.*]] = fcmp olt <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; NEON-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP2]]
; NEON-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; NEON-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; NEON-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
; NEON-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x float> [[WIDE_LOAD]], <4 x float> [[VEC_PHI]]
; NEON-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; NEON-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -252,7 +252,7 @@
; SVE-NEXT: [[TMP6:%.*]] = fcmp olt <vscale x 4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; SVE-NEXT: [[TMP7:%.*]] = freeze <vscale x 4 x i1> [[TMP6]]
; SVE-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP7]])
-; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP4]]
; SVE-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x float> [[WIDE_LOAD]], <vscale x 4 x float> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP1]]
; SVE-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -410,7 +410,7 @@
; SVE-NEXT: [[TMP7:%.*]] = icmp slt <vscale x 4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; SVE-NEXT: [[TMP8:%.*]] = freeze <vscale x 4 x i1> [[TMP7]]
; SVE-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP8]])
-; SVE-NEXT: [[TMP10]] = select i1 [[TMP9]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP5]]
+; SVE-NEXT: [[TMP10]] = select i1 [[TMP9]], <vscale x 4 x i1> [[TMP8]], <vscale x 4 x i1> [[TMP5]]
; SVE-NEXT: [[TMP11]] = select i1 [[TMP9]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; SVE-NEXT: [[TMP12]] = select <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i64> [[VEC_IND]], <vscale x 4 x i64> [[VEC_PHI3]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP1]]
@@ -628,7 +628,7 @@
; NEON-NEXT: [[TMP7:%.*]] = icmp slt <4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; NEON-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]]
; NEON-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]])
-; NEON-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP7]], <4 x i1> [[TMP0]]
+; NEON-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP0]]
; NEON-NEXT: [[TMP11]] = select i1 [[TMP9]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; NEON-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; NEON-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -691,7 +691,7 @@
; SVE-NEXT: [[TMP11:%.*]] = icmp slt <vscale x 4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; SVE-NEXT: [[TMP12:%.*]] = freeze <vscale x 4 x i1> [[TMP11]]
; SVE-NEXT: [[TMP13:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP12]])
-; SVE-NEXT: [[TMP14]] = select i1 [[TMP13]], <vscale x 4 x i1> [[TMP11]], <vscale x 4 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP14]] = select i1 [[TMP13]], <vscale x 4 x i1> [[TMP12]], <vscale x 4 x i1> [[TMP4]]
; SVE-NEXT: [[TMP15]] = select i1 [[TMP13]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -791,7 +791,7 @@
; SVE-NEXT: [[TMP6:%.*]] = icmp slt <vscale x 16 x i8> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; SVE-NEXT: [[TMP7:%.*]] = freeze <vscale x 16 x i1> [[TMP6]]
; SVE-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> [[TMP7]])
-; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 16 x i1> [[TMP6]], <vscale x 16 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 16 x i1> [[TMP7]], <vscale x 16 x i1> [[TMP4]]
; SVE-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 16 x i8> [[WIDE_LOAD]], <vscale x 16 x i8> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -864,8 +864,8 @@
; NEON-NEXT: [[TMP12:%.*]] = freeze <4 x i1> [[TMP10]]
; NEON-NEXT: [[TMP14:%.*]] = or <4 x i1> [[TMP3]], [[TMP12]]
; NEON-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP14]])
-; NEON-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
-; NEON-NEXT: [[TMP11]] = select i1 [[TMP4]], <4 x i1> [[TMP10]], <4 x i1> [[TMP1]]
+; NEON-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
+; NEON-NEXT: [[TMP11]] = select i1 [[TMP4]], <4 x i1> [[TMP12]], <4 x i1> [[TMP1]]
; NEON-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; NEON-NEXT: [[TMP13]] = select i1 [[TMP4]], <4 x i32> [[WIDE_LOAD2]], <4 x i32> [[VEC_PHI1]]
; NEON-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8
@@ -924,8 +924,8 @@
; SVE-NEXT: [[TMP20:%.*]] = freeze <vscale x 4 x i1> [[TMP19]]
; SVE-NEXT: [[TMP13:%.*]] = or <vscale x 4 x i1> [[TMP7]], [[TMP20]]
; SVE-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP13]])
-; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP4]]
-; SVE-NEXT: [[TMP16]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP19]], <vscale x 4 x i1> [[TMP15]]
+; SVE-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP16]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP20]], <vscale x 4 x i1> [[TMP15]]
; SVE-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; SVE-NEXT: [[TMP18]] = select i1 [[TMP8]], <vscale x 4 x i32> [[WIDE_LOAD2]], <vscale x 4 x i32> [[VEC_PHI1]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
@@ -1031,7 +1031,7 @@
; SVE-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP7]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i32> poison)
; SVE-NEXT: [[TMP8:%.*]] = freeze <vscale x 4 x i1> [[TMP6]]
; SVE-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP8]])
-; SVE-NEXT: [[TMP10]] = select i1 [[TMP9]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP10]] = select i1 [[TMP9]], <vscale x 4 x i1> [[TMP8]], <vscale x 4 x i1> [[TMP4]]
; SVE-NEXT: [[TMP11]] = select i1 [[TMP9]], <vscale x 4 x i32> [[WIDE_MASKED_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -1147,7 +1147,7 @@
; SVE-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.masked.sdiv.nxv4i32(<vscale x 4 x i32> splat (i32 42), <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i1> [[TMP6]])
; SVE-NEXT: [[TMP9:%.*]] = freeze <vscale x 4 x i1> [[TMP6]]
; SVE-NEXT: [[TMP10:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP9]])
-; SVE-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i1> [[TMP4]]
; SVE-NEXT: [[TMP12]] = select i1 [[TMP10]], <vscale x 4 x i32> [[TMP8]], <vscale x 4 x i32> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -1273,7 +1273,7 @@
; SVE-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP10]], <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> poison)
; SVE-NEXT: [[TMP11:%.*]] = freeze <vscale x 4 x i1> [[TMP9]]
; SVE-NEXT: [[TMP12:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP11]])
-; SVE-NEXT: [[TMP13]] = select i1 [[TMP12]], <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i1> [[TMP5]]
+; SVE-NEXT: [[TMP13]] = select i1 [[TMP12]], <vscale x 4 x i1> [[TMP11]], <vscale x 4 x i1> [[TMP5]]
; SVE-NEXT: [[TMP14]] = select i1 [[TMP12]], <vscale x 4 x i32> [[WIDE_MASKED_LOAD5]], <vscale x 4 x i32> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT4]]
@@ -1798,7 +1798,7 @@
; SVE-NEXT: [[TMP11:%.*]] = add nuw nsw <vscale x 16 x i32> [[VEC_IND]], [[TMP10]]
; SVE-NEXT: [[TMP12:%.*]] = freeze <vscale x 16 x i1> [[TMP8]]
; SVE-NEXT: [[TMP13:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> [[TMP12]])
-; SVE-NEXT: [[TMP14]] = select i1 [[TMP13]], <vscale x 16 x i1> [[TMP8]], <vscale x 16 x i1> [[TMP6]]
+; SVE-NEXT: [[TMP14]] = select i1 [[TMP13]], <vscale x 16 x i1> [[TMP12]], <vscale x 16 x i1> [[TMP6]]
; SVE-NEXT: [[TMP15]] = select i1 [[TMP13]], <vscale x 16 x i32> [[TMP11]], <vscale x 16 x i32> [[VEC_PHI]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
@@ -1935,9 +1935,9 @@
; SVE-NEXT: [[TMP11:%.*]] = zext <vscale x 16 x i8> [[WIDE_MASKED_LOAD2]] to <vscale x 16 x i32>
; SVE-NEXT: [[TMP12:%.*]] = freeze <vscale x 16 x i1> [[TMP7]]
; SVE-NEXT: [[TMP13:%.*]] = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> [[TMP12]])
-; SVE-NEXT: [[TMP14]] = select i1 [[TMP13]], <vscale x 16 x i1> [[TMP7]], <vscale x 16 x i1> [[TMP4]]
+; SVE-NEXT: [[TMP14]] = select i1 [[TMP13]], <vscale x 16 x i1> [[TMP12]], <vscale x 16 x i1> [[TMP4]]
; SVE-NEXT: [[TMP15]] = select i1 [[TMP13]], <vscale x 16 x i32> [[TMP9]], <vscale x 16 x i32> [[VEC_PHI]]
-; SVE-NEXT: [[TMP16]] = select i1 [[TMP13]], <vscale x 16 x i1> [[TMP7]], <vscale x 16 x i1> [[TMP5]]
+; SVE-NEXT: [[TMP16]] = select i1 [[TMP13]], <vscale x 16 x i1> [[TMP12]], <vscale x 16 x i1> [[TMP5]]
; SVE-NEXT: [[TMP17]] = select i1 [[TMP13]], <vscale x 16 x i32> [[TMP11]], <vscale x 16 x i32> [[VEC_PHI1]]
; SVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; SVE-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll b/llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll
index 71d3eb6..3a8f7b9 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll
@@ -30,7 +30,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <vscale x 4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; CHECK-NEXT: [[TMP7:%.*]] = freeze <vscale x 4 x i1> [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP4]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x i32> [[WIDE_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
index 54b0d14..190de22 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
@@ -135,7 +135,7 @@
; CHECK-VF4IC1-NEXT: [[VEC_ICMP:%.*]] = icmp ne <vscale x 4 x i32> [[VEC_LOAD]], splat (i32 3)
; CHECK-VF4IC1-NEXT: [[VEC_ICMP_F:%.*]] = freeze <vscale x 4 x i1> [[VEC_ICMP]]
; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[VEC_ICMP_F]])
-; CHECK-VF4IC1-NEXT: [[VEC_SEL1:%.*]] = select i1 [[TMP8]], <vscale x 4 x i1> [[VEC_ICMP]], <vscale x 4 x i1> [[TMP4:%.*]]
+; CHECK-VF4IC1-NEXT: [[VEC_SEL1:%.*]] = select i1 [[TMP8]], <vscale x 4 x i1> [[VEC_ICMP_F]], <vscale x 4 x i1> [[TMP4:%.*]]
; CHECK-VF4IC1-NEXT: [[VEC_SEL2:%.*]] = select i1 [[TMP8]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> [[VEC_PHI]]
; CHECK-VF4IC1: middle.block:
; CHECK-VF4IC1-NEXT: [[OR_RDX:%.*]] = call float @llvm.experimental.vector.extract.last.active.nxv4f32(<vscale x 4 x float> [[VEC_SEL2]], <vscale x 4 x i1> [[VEC_SEL1]], float 3.000000e+00)
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll b/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
index 0e4e110..db4a5fb 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
@@ -22,7 +22,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i1> @llvm.vp.merge.nxv4i1(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i1> zeroinitializer, i32 [[TMP1]])
; CHECK-NEXT: [[TMP7:%.*]] = freeze <vscale x 4 x i1> [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP11]], [[IV]]
@@ -88,7 +88,7 @@
; CHECK-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP7]], <vscale x 4 x i1> [[TMP5]], i32 [[TMP1]])
; CHECK-NEXT: [[TMP9:%.*]] = freeze <vscale x 4 x i1> [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP9]])
-; CHECK-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP8]], <vscale x 4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP12]] = select i1 [[TMP10]], <vscale x 4 x i32> [[VP_OP_LOAD5]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP13]], [[IV]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll b/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
index d685a23..3be8a55 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
@@ -25,7 +25,7 @@
; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <vscale x 4 x i32> [[BROADCAST_SPLAT]], [[VP_OP_LOAD]]
; CHECK-NEXT: [[TMP7:%.*]] = freeze <vscale x 4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i1> [[TMP4]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP1]]
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -108,7 +108,7 @@
; CHECK-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP7]], <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i32> poison)
; CHECK-NEXT: [[TMP9:%.*]] = freeze <vscale x 4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP10:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP9]])
-; CHECK-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i1> [[TMP4]]
+; CHECK-NEXT: [[TMP11]] = select i1 [[TMP10]], <vscale x 4 x i1> [[TMP9]], <vscale x 4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP12]] = select i1 [[TMP10]], <vscale x 4 x i32> [[VP_OP_LOAD5]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP1]]
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll b/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
index afad205..1306b9a 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
@@ -26,7 +26,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i1> @llvm.vp.merge.nxv4i1(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i1> zeroinitializer, i32 [[TMP3]])
; CHECK-NEXT: [[TMP7:%.*]] = freeze <vscale x 4 x i1> [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x i32> [[VEC_IND]], <vscale x 4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP11]], [[TMP22]]
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
index fd283e9..e809611 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
@@ -259,7 +259,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i1> @llvm.vp.merge.nxv4i1(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i1> zeroinitializer, i32 [[TMP1]])
; CHECK-NEXT: [[TMP7:%.*]] = freeze <vscale x 4 x i1> [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP6]], <vscale x 4 x i1> [[TMP4]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <vscale x 4 x i1> [[TMP7]], <vscale x 4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> [[VEC_PHI]]
; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP11]], [[TMP0]]
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
index 2c304bc..e757165 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
@@ -42,7 +42,7 @@
; CHECK-NEXT: WIDEN ir<%select.cmp> = icmp slt ir<%a>, ir<%ld>
; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = freeze ir<%select.cmp>
; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = any-of vp<[[VP7]]>
-; CHECK-NEXT: EMIT vp<[[VP9]]> = select vp<[[VP8]]>, ir<%select.cmp>, vp<[[VP4]]>
+; CHECK-NEXT: EMIT vp<[[VP9]]> = select vp<[[VP8]]>, vp<[[VP7]]>, vp<[[VP4]]>
; CHECK-NEXT: EMIT vp<[[VP10]]> = select vp<[[VP8]]>, ir<%ld>, ir<%data.phi>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
@@ -106,7 +106,7 @@
; CHECK-TF-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = logical-and vp<[[VP8]]>, ir<%select.cmp>
; CHECK-TF-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = freeze vp<[[VP11]]>
; CHECK-TF-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = any-of vp<[[VP12]]>
-; CHECK-TF-NEXT: EMIT vp<[[VP14]]> = select vp<[[VP13]]>, vp<[[VP11]]>, vp<[[VP6]]>
+; CHECK-TF-NEXT: EMIT vp<[[VP14]]> = select vp<[[VP13]]>, vp<[[VP12]]>, vp<[[VP6]]>
; CHECK-TF-NEXT: EMIT vp<[[VP15]]> = select vp<[[VP13]]>, ir<%ld>, ir<%data.phi>
; CHECK-TF-NEXT: EMIT vp<%index.next> = add vp<[[VP4]]>, vp<[[VP1]]>
; CHECK-TF-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
@@ -210,7 +210,7 @@
; CHECK-NEXT: if.then.0:
; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = freeze ir<%if.cond>
; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = any-of vp<[[VP9]]>
-; CHECK-NEXT: EMIT vp<[[VP11]]> = select vp<[[VP10]]>, ir<%if.cond>, vp<[[VP4]]>
+; CHECK-NEXT: EMIT vp<[[VP11]]> = select vp<[[VP10]]>, vp<[[VP9]]>, vp<[[VP4]]>
; CHECK-NEXT: EMIT vp<[[VP12]]> = select vp<[[VP10]]>, vp<[[VP8]]>, ir<%data.phi>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
@@ -274,7 +274,7 @@
; CHECK-TF-NEXT: WIDEN ir<%ld.b> = load vp<[[VP12]]>, vp<[[VP11]]>
; CHECK-TF-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = freeze vp<[[VP11]]>
; CHECK-TF-NEXT: EMIT vp<[[VP14:%[0-9]+]]> = any-of vp<[[VP13]]>
-; CHECK-TF-NEXT: EMIT vp<[[VP15]]> = select vp<[[VP14]]>, vp<[[VP11]]>, vp<[[VP6]]>
+; CHECK-TF-NEXT: EMIT vp<[[VP15]]> = select vp<[[VP14]]>, vp<[[VP13]]>, vp<[[VP6]]>
; CHECK-TF-NEXT: EMIT vp<[[VP16]]> = select vp<[[VP14]]>, ir<%ld.b>, ir<%data.phi>
; CHECK-TF-NEXT: EMIT vp<%index.next> = add vp<[[VP4]]>, vp<[[VP1]]>
; CHECK-TF-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
index 0ad003f..3dc3557 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
@@ -45,8 +45,8 @@
; IC2-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = freeze ir<%select.cmp>
; IC2-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = freeze ir<%select.cmp>.1
; IC2-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = any-of vp<[[VP8]]>, vp<[[VP9]]>
-; IC2-NEXT: EMIT vp<[[VP11]]> = select vp<[[VP10]]>, ir<%select.cmp>, vp<[[VP5]]>
-; IC2-NEXT: EMIT vp<[[VP12]]> = select vp<[[VP10]]>, ir<%select.cmp>.1, vp<[[VP6]]>
+; IC2-NEXT: EMIT vp<[[VP11]]> = select vp<[[VP10]]>, vp<[[VP8]]>, vp<[[VP5]]>
+; IC2-NEXT: EMIT vp<[[VP12]]> = select vp<[[VP10]]>, vp<[[VP9]]>, vp<[[VP6]]>
; IC2-NEXT: EMIT vp<[[VP13]]> = select vp<[[VP10]]>, ir<%ld>, ir<%data.phi>
; IC2-NEXT: EMIT vp<[[VP14]]> = select vp<[[VP10]]>, ir<%ld>.1, ir<%data.phi>.1
; IC2-NEXT: EMIT vp<%index.next> = add nuw vp<%index>, ir<8>
@@ -122,8 +122,8 @@
; IC2-TF-NEXT: EMIT vp<[[VP16:%[0-9]+]]> = freeze vp<[[VP14]]>
; IC2-TF-NEXT: EMIT vp<[[VP17:%[0-9]+]]> = freeze vp<[[VP15]]>
; IC2-TF-NEXT: EMIT vp<[[VP18:%[0-9]+]]> = any-of vp<[[VP16]]>, vp<[[VP17]]>
-; IC2-TF-NEXT: EMIT vp<[[VP19]]> = select vp<[[VP18]]>, vp<[[VP14]]>, vp<[[VP5]]>
-; IC2-TF-NEXT: EMIT vp<[[VP20]]> = select vp<[[VP18]]>, vp<[[VP15]]>, vp<[[VP6]]>
+; IC2-TF-NEXT: EMIT vp<[[VP19]]> = select vp<[[VP18]]>, vp<[[VP16]]>, vp<[[VP5]]>
+; IC2-TF-NEXT: EMIT vp<[[VP20]]> = select vp<[[VP18]]>, vp<[[VP17]]>, vp<[[VP6]]>
; IC2-TF-NEXT: EMIT vp<[[VP21]]> = select vp<[[VP18]]>, ir<%ld>, ir<%data.phi>
; IC2-TF-NEXT: EMIT vp<[[VP22]]> = select vp<[[VP18]]>, ir<%ld>.1, ir<%data.phi>.1
; IC2-TF-NEXT: EMIT vp<%index.next> = add vp<%index>, ir<8>
diff --git a/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll b/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
index f5c51e4..4b0b5d1 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
@@ -26,7 +26,7 @@
; X86-NEXT: [[TMP2:%.*]] = icmp slt <4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; X86-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP2]]
; X86-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
; X86-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; X86-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; X86-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -73,7 +73,7 @@
; AVX512-NEXT: [[TMP2:%.*]] = icmp slt <16 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; AVX512-NEXT: [[TMP3:%.*]] = freeze <16 x i1> [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])
-; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP2]], <16 x i1> [[TMP0]]
+; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP3]], <16 x i1> [[TMP0]]
; AVX512-NEXT: [[TMP6]] = select i1 [[TMP4]], <16 x i32> [[WIDE_LOAD]], <16 x i32> [[VEC_PHI]]
; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
; AVX512-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -161,7 +161,7 @@
; AVX512-NEXT: [[TMP3:%.*]] = icmp slt <8 x i64> [[BROADCAST_SPLAT]], [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = freeze <8 x i1> [[TMP3]]
; AVX512-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP4]])
-; AVX512-NEXT: [[TMP6]] = select i1 [[TMP5]], <8 x i1> [[TMP3]], <8 x i1> [[TMP0]]
+; AVX512-NEXT: [[TMP6]] = select i1 [[TMP5]], <8 x i1> [[TMP4]], <8 x i1> [[TMP0]]
; AVX512-NEXT: [[TMP7]] = select i1 [[TMP5]], <8 x ptr> [[WIDE_LOAD]], <8 x ptr> [[VEC_PHI]]
; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8
; AVX512-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -229,7 +229,7 @@
; X86-NEXT: [[TMP2:%.*]] = fcmp olt <4 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; X86-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP2]]
; X86-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
; X86-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x float> [[WIDE_LOAD]], <4 x float> [[VEC_PHI]]
; X86-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; X86-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -276,7 +276,7 @@
; AVX512-NEXT: [[TMP2:%.*]] = fcmp olt <16 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; AVX512-NEXT: [[TMP3:%.*]] = freeze <16 x i1> [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])
-; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP2]], <16 x i1> [[TMP0]]
+; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP3]], <16 x i1> [[TMP0]]
; AVX512-NEXT: [[TMP6]] = select i1 [[TMP4]], <16 x float> [[WIDE_LOAD]], <16 x float> [[VEC_PHI]]
; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 16
; AVX512-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -429,7 +429,7 @@
; AVX512-NEXT: [[TMP2:%.*]] = icmp slt <8 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; AVX512-NEXT: [[TMP3:%.*]] = freeze <8 x i1> [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> [[TMP3]])
-; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <8 x i1> [[TMP2]], <8 x i1> [[TMP0]]
+; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <8 x i1> [[TMP3]], <8 x i1> [[TMP0]]
; AVX512-NEXT: [[TMP6]] = select i1 [[TMP4]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[VEC_PHI]]
; AVX512-NEXT: [[TMP7]] = select <8 x i1> [[TMP2]], <8 x i64> [[VEC_IND]], <8 x i64> [[VEC_PHI1]]
; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8
@@ -647,7 +647,7 @@
; X86-NEXT: [[TMP7:%.*]] = icmp slt <4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; X86-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]]
; X86-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]])
-; X86-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP7]], <4 x i1> [[TMP0]]
+; X86-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP0]]
; X86-NEXT: [[TMP11]] = select i1 [[TMP9]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; X86-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; X86-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -708,7 +708,7 @@
; AVX512-NEXT: [[TMP7:%.*]] = icmp slt <16 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; AVX512-NEXT: [[TMP8:%.*]] = freeze <16 x i1> [[TMP7]]
; AVX512-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP8]])
-; AVX512-NEXT: [[TMP10]] = select i1 [[TMP9]], <16 x i1> [[TMP7]], <16 x i1> [[TMP0]]
+; AVX512-NEXT: [[TMP10]] = select i1 [[TMP9]], <16 x i1> [[TMP8]], <16 x i1> [[TMP0]]
; AVX512-NEXT: [[TMP11]] = select i1 [[TMP9]], <16 x i32> [[WIDE_LOAD]], <16 x i32> [[VEC_PHI]]
; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
; AVX512-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -788,7 +788,7 @@
; X86-NEXT: [[TMP2:%.*]] = icmp slt <16 x i8> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; X86-NEXT: [[TMP3:%.*]] = freeze <16 x i1> [[TMP2]]
; X86-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])
-; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP2]], <16 x i1> [[TMP0]]
+; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP3]], <16 x i1> [[TMP0]]
; X86-NEXT: [[TMP6]] = select i1 [[TMP4]], <16 x i8> [[WIDE_LOAD]], <16 x i8> [[VEC_PHI]]
; X86-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 16
; X86-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -835,7 +835,7 @@
; AVX512-NEXT: [[TMP2:%.*]] = icmp slt <64 x i8> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
; AVX512-NEXT: [[TMP3:%.*]] = freeze <64 x i1> [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> [[TMP3]])
-; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <64 x i1> [[TMP2]], <64 x i1> [[TMP0]]
+; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <64 x i1> [[TMP3]], <64 x i1> [[TMP0]]
; AVX512-NEXT: [[TMP6]] = select i1 [[TMP4]], <64 x i8> [[WIDE_LOAD]], <64 x i8> [[VEC_PHI]]
; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64
; AVX512-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -908,8 +908,8 @@
; X86-NEXT: [[TMP12:%.*]] = freeze <4 x i1> [[TMP10]]
; X86-NEXT: [[TMP14:%.*]] = or <4 x i1> [[TMP3]], [[TMP12]]
; X86-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP14]])
-; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
-; X86-NEXT: [[TMP11]] = select i1 [[TMP4]], <4 x i1> [[TMP10]], <4 x i1> [[TMP1]]
+; X86-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
+; X86-NEXT: [[TMP11]] = select i1 [[TMP4]], <4 x i1> [[TMP12]], <4 x i1> [[TMP1]]
; X86-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; X86-NEXT: [[TMP13]] = select i1 [[TMP4]], <4 x i32> [[WIDE_LOAD2]], <4 x i32> [[VEC_PHI1]]
; X86-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8
@@ -965,8 +965,8 @@
; AVX512-NEXT: [[TMP14:%.*]] = freeze <16 x i1> [[TMP12]]
; AVX512-NEXT: [[TMP15:%.*]] = or <16 x i1> [[TMP3]], [[TMP14]]
; AVX512-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP15]])
-; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP2]], <16 x i1> [[TMP0]]
-; AVX512-NEXT: [[TMP11]] = select i1 [[TMP4]], <16 x i1> [[TMP12]], <16 x i1> [[TMP9]]
+; AVX512-NEXT: [[TMP5]] = select i1 [[TMP4]], <16 x i1> [[TMP3]], <16 x i1> [[TMP0]]
+; AVX512-NEXT: [[TMP11]] = select i1 [[TMP4]], <16 x i1> [[TMP14]], <16 x i1> [[TMP9]]
; AVX512-NEXT: [[TMP6]] = select i1 [[TMP4]], <16 x i32> [[WIDE_LOAD]], <16 x i32> [[VEC_PHI]]
; AVX512-NEXT: [[TMP13]] = select i1 [[TMP4]], <16 x i32> [[WIDE_LOAD2]], <16 x i32> [[VEC_PHI1]]
; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask.ll b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
index 47e2cd8..09d796b 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
@@ -464,7 +464,7 @@
; CHECK-NEXT: [[TMP14:%.*]] = select <4 x i1> [[CLAMPED_HEADER_MASK]], <4 x i1> [[TMP13]], <4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP15:%.*]] = freeze <4 x i1> [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP15]])
-; CHECK-NEXT: [[TMP17]] = select i1 [[TMP16]], <4 x i1> [[TMP14]], <4 x i1> [[TMP6]]
+; CHECK-NEXT: [[TMP17]] = select i1 [[TMP16]], <4 x i1> [[TMP15]], <4 x i1> [[TMP6]]
; CHECK-NEXT: [[TMP18]] = select i1 [[TMP16]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[NUM_ACTIVE_LANES]]
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT4]]
diff --git a/llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll b/llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll
index 2f2468f..c3ee580 100644
--- a/llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll
+++ b/llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll
@@ -29,8 +29,8 @@
; CHECK-NEXT: [[TMP9:%.*]] = freeze i1 [[TMP7]]
; CHECK-NEXT: [[TMP10:%.*]] = freeze i1 [[TMP8]]
; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP9]], [[TMP10]]
-; CHECK-NEXT: [[TMP12]] = select i1 [[TMP11]], i1 [[TMP7]], i1 [[TMP0]]
-; CHECK-NEXT: [[TMP13]] = select i1 [[TMP11]], i1 [[TMP8]], i1 [[TMP3]]
+; CHECK-NEXT: [[TMP12]] = select i1 [[TMP11]], i1 [[TMP9]], i1 [[TMP0]]
+; CHECK-NEXT: [[TMP13]] = select i1 [[TMP11]], i1 [[TMP10]], i1 [[TMP3]]
; CHECK-NEXT: [[TMP14]] = select i1 [[TMP11]], i32 [[TMP5]], i32 [[VEC_PHI]]
; CHECK-NEXT: [[TMP19]] = select i1 [[TMP11]], i32 [[TMP21]], i32 [[VEC_PHI1]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
index 0edba19..6becee9 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
@@ -300,7 +300,7 @@
; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP3]], <4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
-; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP5]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP6]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP9]] = select i1 [[TMP7]], <4 x i32> [[TMP4]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <4 x i32> [[VEC_IND1]], splat (i32 4)
@@ -376,7 +376,7 @@
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP3]], <4 x i1> [[TMP5]], <4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = freeze <4 x i1> [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP10]])
-; CHECK-NEXT: [[TMP12]] = select i1 [[TMP11]], <4 x i1> [[TMP9]], <4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP12]] = select i1 [[TMP11]], <4 x i1> [[TMP10]], <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP13]] = select i1 [[TMP11]], <4 x i32> [[TMP8]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -463,7 +463,7 @@
; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP4]], <4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]])
-; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP7]], <4 x i1> [[TMP1]]
+; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP1]]
; CHECK-NEXT: [[TMP11]] = select i1 [[TMP9]], <4 x i64> [[TMP6]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -723,7 +723,7 @@
; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP4]], <4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]])
-; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP7]], <4 x i1> [[TMP1]]
+; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP1]]
; CHECK-NEXT: [[TMP11]] = select i1 [[TMP9]], <4 x i64> [[TMP6]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -785,7 +785,7 @@
; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP4]], <4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]])
-; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP7]], <4 x i1> [[TMP1]]
+; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP1]]
; CHECK-NEXT: [[TMP11]] = select i1 [[TMP9]], <4 x i64> [[TMP6]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
diff --git a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
index db0cbf8..5b8e09b 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
@@ -163,7 +163,7 @@
; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i64> [[VEC_IND]], [[WIDE_LOAD1]]
; CHECK-NEXT: [[TMP5:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
-; CHECK-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP5]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP8]] = select i1 [[TMP6]], <4 x i64> [[TMP4]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -396,7 +396,7 @@
; CHECK-NEXT: [[TMP3:%.*]] = shl <4 x i32> [[VEC_IND]], splat (i32 2)
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i32> [[TMP3]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
@@ -484,7 +484,7 @@
; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i32> [[VEC_IND2]], splat (i32 100)
; CHECK-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]])
-; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP4]], <4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP10]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP11]] = select i1 [[TMP9]], <4 x i32> [[TMP7]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -569,7 +569,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = sdiv <4 x i64> splat (i64 100), [[VEC_IND]]
; CHECK-NEXT: [[TMP7:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP5]], <4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP7]], <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <4 x i64> [[TMP6]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -641,7 +641,7 @@
; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i8> [[VEC_IND]], splat (i8 10)
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i8> [[TMP3]], <4 x i8> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
@@ -949,7 +949,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = udiv <4 x i64> splat (i64 100), [[VEC_IND]]
; CHECK-NEXT: [[TMP7:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP5]], <4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP7]], <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <4 x i64> [[TMP6]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -1022,7 +1022,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = srem <4 x i64> splat (i64 100), [[VEC_IND]]
; CHECK-NEXT: [[TMP7:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP5]], <4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP7]], <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <4 x i64> [[TMP6]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -1149,7 +1149,7 @@
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], splat (i32 42)
; CHECK-NEXT: [[TMP5:%.*]] = freeze <4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
-; CHECK-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP4]], <4 x i1> [[TMP2]]
+; CHECK-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP5]], <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP8]] = select i1 [[TMP6]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
diff --git a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll
index a689c6b..5b6d0ee 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll
@@ -22,7 +22,7 @@
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i64> [[WIDE_LOAD1]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -92,7 +92,7 @@
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i64> [[WIDE_LOAD1]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr [[TMP3]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
@@ -163,7 +163,7 @@
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 42)
; CHECK-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; CHECK-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i64> [[WIDE_LOAD]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -232,7 +232,7 @@
; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i64> [[WIDE_LOAD1]], [[WIDE_LOAD2]]
; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
-; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP6]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP9]] = select i1 [[TMP7]], <4 x i64> [[TMP5]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -324,7 +324,7 @@
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i64> [[TMP18]], i64 [[TMP15]], i64 3
; CHECK-NEXT: [[TMP20:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP21:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP20]])
-; CHECK-NEXT: [[TMP22]] = select i1 [[TMP21]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP22]] = select i1 [[TMP21]], <4 x i1> [[TMP20]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP23]] = select i1 [[TMP21]], <4 x i64> [[TMP19]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -398,7 +398,7 @@
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8
; CHECK-NEXT: [[TMP5:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
-; CHECK-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP5]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP8]] = select i1 [[TMP6]], <4 x i64> [[WIDE_LOAD1]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -471,7 +471,7 @@
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 42)
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i64> [[BROADCAST_SPLAT]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -555,7 +555,7 @@
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i64> [[TMP18]], i64 [[TMP15]], i64 3
; CHECK-NEXT: [[TMP20:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP21:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP20]])
-; CHECK-NEXT: [[TMP22]] = select i1 [[TMP21]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP22]] = select i1 [[TMP21]], <4 x i1> [[TMP20]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP23]] = select i1 [[TMP21]], <4 x i64> [[TMP19]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -629,7 +629,7 @@
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i64> [[WIDE_LOAD1]], <4 x i64> [[VEC_PHI]]
; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], splat (i64 100)
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP8]], i64 0
diff --git a/llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll b/llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
index 8154525..6033922 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
@@ -27,7 +27,7 @@
; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
-; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP5]], <4 x i1> [[TMP3]]
+; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP6]], <4 x i1> [[TMP3]]
; CHECK-NEXT: [[TMP9]] = select i1 [[TMP7]], <4 x ptr> [[VECTOR_GEP]], <4 x ptr> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 16
@@ -103,7 +103,7 @@
; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
-; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP5]], <4 x i1> [[TMP3]]
+; CHECK-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP6]], <4 x i1> [[TMP3]]
; CHECK-NEXT: [[TMP9]] = select i1 [[TMP7]], <4 x ptr> [[VECTOR_GEP]], <4 x ptr> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 96
@@ -175,7 +175,7 @@
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x ptr> [[WIDE_LOAD]], splat (ptr null)
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP1]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP1]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x ptr> [[WIDE_LOAD]], <4 x ptr> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -293,7 +293,7 @@
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-NEXT: [[TMP7:%.*]] = freeze <4 x i1> [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])
-; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP6]], <4 x i1> [[TMP4]]
+; CHECK-NEXT: [[TMP9]] = select i1 [[TMP8]], <4 x i1> [[TMP7]], <4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP10]] = select i1 [[TMP8]], <4 x ptr addrspace(1)> [[VECTOR_GEP]], <4 x ptr addrspace(1)> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr addrspace(1) [[POINTER_PHI]], i32 16
diff --git a/llvm/test/Transforms/LoopVectorize/find-last.ll b/llvm/test/Transforms/LoopVectorize/find-last.ll
index 691980d..bfde15e 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last.ll
@@ -21,7 +21,7 @@
; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]]
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 500
@@ -70,7 +70,7 @@
; CHECK-NEXT: [[TMP3:%.*]] = icmp sle <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]]
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 500
@@ -119,7 +119,7 @@
; CHECK-NEXT: [[TMP3:%.*]] = icmp uge <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]]
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 500
@@ -168,7 +168,7 @@
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]]
; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
+; CHECK-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP0]]
; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 500
@@ -226,7 +226,7 @@
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[TMP6:%.*]] = phi <4 x i1> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP6]]
+; CHECK-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP6]]
; CHECK-NEXT: [[TMP8]] = select i1 [[TMP5]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
@@ -280,7 +280,7 @@
; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP1]])
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
-; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], <4 x i1> [[TMP1]], <4 x i1> zeroinitializer
; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]
; CHECK: middle.block:
; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.experimental.vector.extract.last.active.v4p0(<4 x ptr> splat (ptr null), <4 x i1> [[TMP3]], ptr null)
diff --git a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
index 21b9c3f..05e7df4 100644
--- a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
@@ -28,7 +28,7 @@
; CHECK-NEXT: [[TMP28:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP27]], <4 x i1> zeroinitializer
; CHECK-NEXT: [[TMP29:%.*]] = freeze <4 x i1> [[TMP28]]
; CHECK-NEXT: [[TMP30:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP29]])
-; CHECK-NEXT: [[TMP31]] = select i1 [[TMP30]], <4 x i1> [[TMP28]], <4 x i1> [[TMP1]]
+; CHECK-NEXT: [[TMP31]] = select i1 [[TMP30]], <4 x i1> [[TMP29]], <4 x i1> [[TMP1]]
; CHECK-NEXT: [[TMP32]] = select i1 [[TMP30]], <4 x i32> [[VEC_IND1]], <4 x i32> [[VEC_PHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[TMP22]], 4
; CHECK-NEXT: [[VEC_IND_NEXT8]] = add <4 x i32> [[VEC_IND1]], splat (i32 4)
diff --git a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
index ad84f30..48fa114 100644
--- a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
@@ -290,7 +290,7 @@
; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = freeze <4 x i1> [[TMP4]]
; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
-; CHECK-VF4IC1-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP4]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC1-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP5]], <4 x i1> [[LAST_ACTIVE_MASK]]
; CHECK-VF4IC1-NEXT: [[TMP8]] = select i1 [[TMP6]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
@@ -378,10 +378,10 @@
; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = or <4 x i1> [[TMP38]], [[TMP18]]
; CHECK-VF4IC4-NEXT: [[TMP21:%.*]] = or <4 x i1> [[TMP19]], [[TMP20]]
; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP21]])
-; CHECK-VF4IC4-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP4]], <4 x i1> [[LAST_ACTIVE_MASK]]
-; CHECK-VF4IC4-NEXT: [[TMP24]] = select i1 [[TMP6]], <4 x i1> [[TMP33]], <4 x i1> [[TMP15]]
-; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP6]], <4 x i1> [[TMP37]], <4 x i1> [[TMP22]]
-; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP6]], <4 x i1> [[TMP14]], <4 x i1> [[TMP23]]
+; CHECK-VF4IC4-NEXT: [[TMP7]] = select i1 [[TMP6]], <4 x i1> [[TMP5]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC4-NEXT: [[TMP24]] = select i1 [[TMP6]], <4 x i1> [[TMP16]], <4 x i1> [[TMP15]]
+; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP6]], <4 x i1> [[TMP18]], <4 x i1> [[TMP22]]
+; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP6]], <4 x i1> [[TMP20]], <4 x i1> [[TMP23]]
; CHECK-VF4IC4-NEXT: [[TMP8]] = select i1 [[TMP6]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP28]] = select i1 [[TMP6]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI3]]
; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP6]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI4]]
@@ -473,10 +473,10 @@
; CHECK-VF1IC4-NEXT: [[TMP49:%.*]] = or i1 [[TMP27]], [[TMP28]]
; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = or i1 [[TMP49]], [[TMP30]]
; CHECK-VF1IC4-NEXT: [[TMP33:%.*]] = or i1 [[TMP31]], [[TMP32]]
-; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP33]], i1 [[CMP1]], i1 [[TMP3]]
-; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP33]], i1 [[TMP24]], i1 [[TMP4]]
-; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP33]], i1 [[TMP25]], i1 [[TMP5]]
-; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP33]], i1 [[TMP26]], i1 [[TMP6]]
+; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP33]], i1 [[TMP27]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP33]], i1 [[TMP28]], i1 [[TMP4]]
+; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP33]], i1 [[TMP30]], i1 [[TMP5]]
+; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP33]], i1 [[TMP32]], i1 [[TMP6]]
; CHECK-VF1IC4-NEXT: [[TMP38]] = select i1 [[TMP33]], i32 [[TMP11]], i32 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP33]], i32 [[TMP12]], i32 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP33]], i32 [[TMP13]], i32 [[VEC_PHI2]]
diff --git a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
index c0dfbbb..966db6b 100644
--- a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
@@ -705,7 +705,7 @@
; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = freeze <4 x i1> [[TMP8]]
; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP2]])
-; CHECK-VF4IC1-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP8]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC1-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]]
; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
@@ -783,10 +783,10 @@
; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP34]], [[TMP15]]
; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP17]]
; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP18]])
-; CHECK-VF4IC4-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP1]], <4 x i1> [[LAST_ACTIVE_MASK]]
-; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP3]], <4 x i1> [[TMP33]], <4 x i1> [[TMP12]]
-; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP3]], <4 x i1> [[TMP10]], <4 x i1> [[TMP19]]
-; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP3]], <4 x i1> [[TMP11]], <4 x i1> [[TMP20]]
+; CHECK-VF4IC4-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP3]], <4 x i1> [[TMP13]], <4 x i1> [[TMP12]]
+; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP3]], <4 x i1> [[TMP15]], <4 x i1> [[TMP19]]
+; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP3]], <4 x i1> [[TMP17]], <4 x i1> [[TMP20]]
; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]]
@@ -873,10 +873,10 @@
; CHECK-VF1IC4-NEXT: [[TMP46:%.*]] = or i1 [[TMP24]], [[TMP25]]
; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = or i1 [[TMP46]], [[TMP27]]
; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = or i1 [[TMP28]], [[TMP29]]
-; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP30]], i1 [[CMP]], i1 [[TMP12]]
-; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP30]], i1 [[TMP21]], i1 [[TMP1]]
-; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP30]], i1 [[TMP22]], i1 [[TMP2]]
-; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP30]], i1 [[TMP23]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP30]], i1 [[TMP24]], i1 [[TMP12]]
+; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP30]], i1 [[TMP25]], i1 [[TMP1]]
+; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP30]], i1 [[TMP27]], i1 [[TMP2]]
+; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP30]], i1 [[TMP29]], i1 [[TMP3]]
; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP30]], i32 [[TMP8]], i32 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP30]], i32 [[TMP9]], i32 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP30]], i32 [[TMP10]], i32 [[VEC_PHI2]]
@@ -1222,7 +1222,7 @@
; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = freeze <4 x i1> [[TMP1]]
; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP2]])
-; CHECK-VF4IC1-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP1]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC1-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]]
; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
@@ -1275,10 +1275,10 @@
; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP29]], [[TMP15]]
; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP17]]
; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP18]])
-; CHECK-VF4IC4-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP1]], <4 x i1> [[LAST_ACTIVE_MASK]]
-; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP3]], <4 x i1> [[TMP9]], <4 x i1> [[TMP8]]
-; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP3]], <4 x i1> [[TMP10]], <4 x i1> [[TMP12]]
-; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP3]], <4 x i1> [[TMP11]], <4 x i1> [[TMP19]]
+; CHECK-VF4IC4-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP3]], <4 x i1> [[TMP13]], <4 x i1> [[TMP8]]
+; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP3]], <4 x i1> [[TMP15]], <4 x i1> [[TMP12]]
+; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP3]], <4 x i1> [[TMP17]], <4 x i1> [[TMP19]]
; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]]
@@ -1340,10 +1340,10 @@
; CHECK-VF1IC4-NEXT: [[TMP43:%.*]] = or i1 [[TMP24]], [[TMP25]]
; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = or i1 [[TMP43]], [[TMP27]]
; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = or i1 [[TMP28]], [[TMP29]]
-; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP30]], i1 [[CMP]], i1 [[TMP12]]
-; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP30]], i1 [[TMP21]], i1 [[TMP1]]
-; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP30]], i1 [[TMP22]], i1 [[TMP2]]
-; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP30]], i1 [[TMP23]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP30]], i1 [[TMP24]], i1 [[TMP12]]
+; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP30]], i1 [[TMP25]], i1 [[TMP1]]
+; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP30]], i1 [[TMP27]], i1 [[TMP2]]
+; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP30]], i1 [[TMP29]], i1 [[TMP3]]
; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP30]], i32 [[TMP8]], i32 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP30]], i32 [[TMP9]], i32 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP30]], i32 [[TMP10]], i32 [[VEC_PHI2]]
@@ -1406,7 +1406,7 @@
; CHECK-VF4IC1-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]]
; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP11]]
; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP11]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]]
; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
@@ -1491,10 +1491,10 @@
; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = or <4 x i1> [[TMP39]], [[TMP19]]
; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = or <4 x i1> [[TMP20]], [[TMP21]]
; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP22]])
-; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP11]], <4 x i1> [[LAST_ACTIVE_MASK]]
-; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP4]], <4 x i1> [[TMP13]], <4 x i1> [[TMP12]]
-; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP4]], <4 x i1> [[TMP14]], <4 x i1> [[TMP16]]
-; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP4]], <4 x i1> [[TMP15]], <4 x i1> [[TMP23]]
+; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP4]], <4 x i1> [[TMP17]], <4 x i1> [[TMP12]]
+; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP4]], <4 x i1> [[TMP19]], <4 x i1> [[TMP16]]
+; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP4]], <4 x i1> [[TMP21]], <4 x i1> [[TMP23]]
; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP4]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP30]] = select i1 [[TMP4]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]]
@@ -1586,10 +1586,10 @@
; CHECK-VF1IC4-NEXT: [[TMP55:%.*]] = or i1 [[TMP32]], [[TMP33]]
; CHECK-VF1IC4-NEXT: [[TMP36:%.*]] = or i1 [[TMP55]], [[TMP35]]
; CHECK-VF1IC4-NEXT: [[TMP38:%.*]] = or i1 [[TMP36]], [[TMP37]]
-; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP38]], i1 [[CMP]], i1 [[TMP12]]
-; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP38]], i1 [[TMP29]], i1 [[TMP16]]
-; CHECK-VF1IC4-NEXT: [[TMP41]] = select i1 [[TMP38]], i1 [[TMP30]], i1 [[TMP2]]
-; CHECK-VF1IC4-NEXT: [[TMP42]] = select i1 [[TMP38]], i1 [[TMP31]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP38]], i1 [[TMP32]], i1 [[TMP12]]
+; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP38]], i1 [[TMP33]], i1 [[TMP16]]
+; CHECK-VF1IC4-NEXT: [[TMP41]] = select i1 [[TMP38]], i1 [[TMP35]], i1 [[TMP2]]
+; CHECK-VF1IC4-NEXT: [[TMP42]] = select i1 [[TMP38]], i1 [[TMP37]], i1 [[TMP3]]
; CHECK-VF1IC4-NEXT: [[TMP43]] = select i1 [[TMP38]], i32 [[TMP8]], i32 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP44]] = select i1 [[TMP38]], i32 [[TMP9]], i32 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP45]] = select i1 [[TMP38]], i32 [[TMP10]], i32 [[VEC_PHI2]]
@@ -1891,7 +1891,7 @@
; CHECK-VF4IC1-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]]
; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP11]]
; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP11]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]]
; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i16> [[VEC_IND]], <4 x i16> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[VEC_IND]], splat (i16 4)
@@ -1982,10 +1982,10 @@
; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = or <4 x i1> [[TMP39]], [[TMP19]]
; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = or <4 x i1> [[TMP20]], [[TMP21]]
; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP22]])
-; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP11]], <4 x i1> [[LAST_ACTIVE_MASK]]
-; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP4]], <4 x i1> [[TMP13]], <4 x i1> [[TMP12]]
-; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP4]], <4 x i1> [[TMP14]], <4 x i1> [[TMP16]]
-; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP4]], <4 x i1> [[TMP15]], <4 x i1> [[TMP23]]
+; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP4]], <4 x i1> [[TMP17]], <4 x i1> [[TMP12]]
+; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP4]], <4 x i1> [[TMP19]], <4 x i1> [[TMP16]]
+; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP4]], <4 x i1> [[TMP21]], <4 x i1> [[TMP23]]
; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i16> [[VEC_IND]], <4 x i16> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP4]], <4 x i16> [[STEP_ADD]], <4 x i16> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP30]] = select i1 [[TMP4]], <4 x i16> [[STEP_ADD_2]], <4 x i16> [[VEC_PHI2]]
@@ -2083,10 +2083,10 @@
; CHECK-VF1IC4-NEXT: [[TMP55:%.*]] = or i1 [[TMP32]], [[TMP33]]
; CHECK-VF1IC4-NEXT: [[TMP36:%.*]] = or i1 [[TMP55]], [[TMP35]]
; CHECK-VF1IC4-NEXT: [[TMP38:%.*]] = or i1 [[TMP36]], [[TMP37]]
-; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP38]], i1 [[CMP3]], i1 [[TMP12]]
-; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP38]], i1 [[TMP29]], i1 [[TMP16]]
-; CHECK-VF1IC4-NEXT: [[TMP41]] = select i1 [[TMP38]], i1 [[TMP30]], i1 [[TMP2]]
-; CHECK-VF1IC4-NEXT: [[TMP42]] = select i1 [[TMP38]], i1 [[TMP31]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP38]], i1 [[TMP32]], i1 [[TMP12]]
+; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP38]], i1 [[TMP33]], i1 [[TMP16]]
+; CHECK-VF1IC4-NEXT: [[TMP41]] = select i1 [[TMP38]], i1 [[TMP35]], i1 [[TMP2]]
+; CHECK-VF1IC4-NEXT: [[TMP42]] = select i1 [[TMP38]], i1 [[TMP37]], i1 [[TMP3]]
; CHECK-VF1IC4-NEXT: [[TMP43]] = select i1 [[TMP38]], i16 [[TMP8]], i16 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP44]] = select i1 [[TMP38]], i16 [[TMP9]], i16 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP45]] = select i1 [[TMP38]], i16 [[TMP10]], i16 [[VEC_PHI2]]
@@ -2198,7 +2198,7 @@
; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[VEC_IND]], zeroinitializer
; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]]
; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]])
-; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP2]]
+; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP2]]
; CHECK-VF4IC1-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i1> [[VEC_PHI]], <4 x i1> [[VEC_IND1]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
@@ -2269,10 +2269,10 @@
; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = or <4 x i1> [[TMP19]], [[TMP13]]
; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP14]], [[TMP15]]
; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP16]])
-; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP3]], <4 x i1> [[TMP2]]
-; CHECK-VF4IC4-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i1> [[VEC_PHI]], <4 x i1> [[VEC_IND1]]
-; CHECK-VF4IC4-NEXT: [[TMP20]] = select i1 [[TMP5]], <4 x i1> [[TMP18]], <4 x i1> [[TMP10]]
-; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP5]], <4 x i1> [[TMP9]], <4 x i1> [[TMP17]]
+; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP2]]
+; CHECK-VF4IC4-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i1> [[TMP11]], <4 x i1> [[VEC_IND1]]
+; CHECK-VF4IC4-NEXT: [[TMP20]] = select i1 [[TMP5]], <4 x i1> [[TMP13]], <4 x i1> [[TMP10]]
+; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP5]], <4 x i1> [[TMP15]], <4 x i1> [[TMP17]]
; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP5]], <4 x i1> [[VEC_IND4]], <4 x i1> [[VEC_PHI4]]
; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP5]], <4 x i1> [[VEC_IND4]], <4 x i1> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP24]] = select i1 [[TMP5]], <4 x i1> [[VEC_IND4]], <4 x i1> [[VEC_PHI2]]
@@ -2349,10 +2349,10 @@
; CHECK-VF1IC4-NEXT: [[TMP38:%.*]] = or i1 [[TMP18]], [[TMP19]]
; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = or i1 [[TMP38]], [[TMP21]]
; CHECK-VF1IC4-NEXT: [[TMP24:%.*]] = or i1 [[TMP22]], [[TMP23]]
-; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP24]], i1 [[TMP14]], i1 [[TMP2]]
-; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP24]], i1 [[TMP15]], i1 [[TMP3]]
-; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP24]], i1 [[TMP16]], i1 [[TMP4]]
-; CHECK-VF1IC4-NEXT: [[TMP28]] = select i1 [[TMP24]], i1 [[TMP17]], i1 [[TMP5]]
+; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP24]], i1 [[TMP18]], i1 [[TMP2]]
+; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP24]], i1 [[TMP19]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP24]], i1 [[TMP21]], i1 [[TMP4]]
+; CHECK-VF1IC4-NEXT: [[TMP28]] = select i1 [[TMP24]], i1 [[TMP23]], i1 [[TMP5]]
; CHECK-VF1IC4-NEXT: [[TMP29]] = select i1 [[TMP24]], i1 [[TMP10]], i1 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP30]] = select i1 [[TMP24]], i1 [[TMP11]], i1 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP24]], i1 [[TMP12]], i1 [[VEC_PHI2]]
@@ -2428,7 +2428,7 @@
; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]])
-; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP9]], <4 x i1> [[TMP2]], <4 x i1> [[TMP3]]
+; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP3]]
; CHECK-VF4IC1-NEXT: [[TMP7]] = select i1 [[TMP9]], <4 x i32> [[VEC_IND1]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDEX]]
; CHECK-VF4IC1-NEXT: store <4 x i64> [[VEC_IND]], ptr [[TMP4]], align 8
@@ -2509,10 +2509,10 @@
; CHECK-VF4IC4-NEXT: [[TMP33:%.*]] = or <4 x i1> [[TMP31]], [[TMP32]]
; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = or <4 x i1> [[TMP33]], [[TMP18]]
; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP19]])
-; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP20]], <4 x i1> [[TMP5]], <4 x i1> [[TMP9]]
-; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP20]], <4 x i1> [[TMP6]], <4 x i1> [[TMP10]]
-; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP20]], <4 x i1> [[TMP7]], <4 x i1> [[TMP11]]
-; CHECK-VF4IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], <4 x i1> [[TMP8]], <4 x i1> [[TMP12]]
+; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP20]], <4 x i1> [[TMP29]], <4 x i1> [[TMP9]]
+; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP20]], <4 x i1> [[TMP30]], <4 x i1> [[TMP10]]
+; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP20]], <4 x i1> [[TMP32]], <4 x i1> [[TMP11]]
+; CHECK-VF4IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], <4 x i1> [[TMP18]], <4 x i1> [[TMP12]]
; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP20]], <4 x i32> [[VEC_IND4]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP20]], <4 x i32> [[STEP_ADD5]], <4 x i32> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP20]], <4 x i32> [[STEP_ADD_26]], <4 x i32> [[VEC_PHI2]]
@@ -2604,10 +2604,10 @@
; CHECK-VF1IC4-NEXT: [[TMP49:%.*]] = or i1 [[TMP44]], [[TMP26]]
; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = or i1 [[TMP49]], [[TMP28]]
; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = or i1 [[TMP29]], [[TMP30]]
-; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP31]], i1 [[TMP13]], i1 [[TMP1]]
-; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP31]], i1 [[TMP14]], i1 [[TMP17]]
-; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP31]], i1 [[TMP15]], i1 [[TMP18]]
-; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP31]], i1 [[TMP16]], i1 [[TMP19]]
+; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP31]], i1 [[TMP44]], i1 [[TMP1]]
+; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP31]], i1 [[TMP26]], i1 [[TMP17]]
+; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP31]], i1 [[TMP28]], i1 [[TMP18]]
+; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP31]], i1 [[TMP30]], i1 [[TMP19]]
; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP31]], i32 [[TMP21]], i32 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP31]], i32 [[TMP41]], i32 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP38]] = select i1 [[TMP31]], i32 [[TMP42]], i32 [[VEC_PHI2]]
diff --git a/llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll b/llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
index c9c4615..afceae5 100644
--- a/llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
@@ -1885,7 +1885,7 @@
; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD1]]
; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
-; CHECK-VF4IC1-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP5]], <4 x i1> [[TMP2]]
+; CHECK-VF4IC1-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP6]], <4 x i1> [[TMP2]]
; CHECK-VF4IC1-NEXT: [[TMP9]] = select i1 [[TMP7]], <4 x float> [[VEC_IND]], <4 x float> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4
; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = fadd <4 x float> [[VEC_IND]], splat (float 4.000000e+00)
@@ -1974,10 +1974,10 @@
; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = or <4 x i1> [[TMP41]], [[TMP21]]
; CHECK-VF4IC4-NEXT: [[TMP24:%.*]] = or <4 x i1> [[TMP22]], [[TMP23]]
; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP24]])
-; CHECK-VF4IC4-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP5]], <4 x i1> [[TMP2]]
-; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP7]], <4 x i1> [[TMP15]], <4 x i1> [[TMP14]]
-; CHECK-VF4IC4-NEXT: [[TMP28]] = select i1 [[TMP7]], <4 x i1> [[TMP16]], <4 x i1> [[TMP18]]
-; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP7]], <4 x i1> [[TMP17]], <4 x i1> [[TMP25]]
+; CHECK-VF4IC4-NEXT: [[TMP8]] = select i1 [[TMP7]], <4 x i1> [[TMP6]], <4 x i1> [[TMP2]]
+; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP7]], <4 x i1> [[TMP19]], <4 x i1> [[TMP14]]
+; CHECK-VF4IC4-NEXT: [[TMP28]] = select i1 [[TMP7]], <4 x i1> [[TMP21]], <4 x i1> [[TMP18]]
+; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP7]], <4 x i1> [[TMP23]], <4 x i1> [[TMP25]]
; CHECK-VF4IC4-NEXT: [[TMP9]] = select i1 [[TMP7]], <4 x float> [[VEC_IND]], <4 x float> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP31]] = select i1 [[TMP7]], <4 x float> [[STEP_ADD]], <4 x float> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP32]] = select i1 [[TMP7]], <4 x float> [[STEP_ADD_2]], <4 x float> [[VEC_PHI2]]
diff --git a/llvm/test/Transforms/LoopVectorize/select-cmp.ll b/llvm/test/Transforms/LoopVectorize/select-cmp.ll
index 00bf931..c9bfced 100644
--- a/llvm/test/Transforms/LoopVectorize/select-cmp.ll
+++ b/llvm/test/Transforms/LoopVectorize/select-cmp.ll
@@ -1107,7 +1107,7 @@
; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
+; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x float> splat (float 7.000000e+00), <4 x float> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -1173,10 +1173,10 @@
; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP33]], [[TMP15]]
; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP17]]
; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP18]])
-; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[TMP0]]
-; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP4]], <4 x i1> [[TMP9]], <4 x i1> [[TMP12]]
-; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP4]], <4 x i1> [[TMP10]], <4 x i1> [[TMP19]]
-; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP4]], <4 x i1> [[TMP11]], <4 x i1> [[TMP20]]
+; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[TMP0]]
+; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP4]], <4 x i1> [[TMP13]], <4 x i1> [[TMP12]]
+; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP4]], <4 x i1> [[TMP15]], <4 x i1> [[TMP19]]
+; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP4]], <4 x i1> [[TMP17]], <4 x i1> [[TMP20]]
; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x float> splat (float 7.000000e+00), <4 x float> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP4]], <4 x float> splat (float 7.000000e+00), <4 x float> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP4]], <4 x float> splat (float 7.000000e+00), <4 x float> [[VEC_PHI2]]
@@ -1250,10 +1250,10 @@
; CHECK-VF1IC4-NEXT: [[TMP39:%.*]] = or i1 [[TMP19]], [[TMP20]]
; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = or i1 [[TMP39]], [[TMP22]]
; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
-; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP25]], i1 [[TMP15]], i1 [[TMP0]]
-; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP25]], i1 [[TMP16]], i1 [[TMP1]]
-; CHECK-VF1IC4-NEXT: [[TMP28]] = select i1 [[TMP25]], i1 [[TMP17]], i1 [[TMP2]]
-; CHECK-VF1IC4-NEXT: [[TMP29]] = select i1 [[TMP25]], i1 [[TMP18]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP25]], i1 [[TMP19]], i1 [[TMP0]]
+; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP25]], i1 [[TMP20]], i1 [[TMP1]]
+; CHECK-VF1IC4-NEXT: [[TMP28]] = select i1 [[TMP25]], i1 [[TMP22]], i1 [[TMP2]]
+; CHECK-VF1IC4-NEXT: [[TMP29]] = select i1 [[TMP25]], i1 [[TMP24]], i1 [[TMP3]]
; CHECK-VF1IC4-NEXT: [[TMP30]] = select i1 [[TMP25]], float 7.000000e+00, float [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP25]], float 7.000000e+00, float [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP25]], float 7.000000e+00, float [[VEC_PHI2]]
@@ -1325,7 +1325,7 @@
; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[WIDE_LOAD]], splat (i32 3)
; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
-; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]]
; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[WIDE_LOAD1]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
@@ -1401,10 +1401,10 @@
; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = or <4 x i1> [[TMP37]], [[TMP33]]
; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = or <4 x i1> [[TMP20]], [[TMP21]]
; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP22]])
-; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP19]], <4 x i1> [[TMP11]], <4 x i1> [[LAST_ACTIVE_MASK]]
-; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP19]], <4 x i1> [[TMP13]], <4 x i1> [[TMP1]]
-; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP19]], <4 x i1> [[TMP14]], <4 x i1> [[TMP2]]
-; CHECK-VF4IC4-NEXT: [[TMP32]] = select i1 [[TMP19]], <4 x i1> [[TMP15]], <4 x i1> [[TMP3]]
+; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP19]], <4 x i1> [[TMP17]], <4 x i1> [[LAST_ACTIVE_MASK]]
+; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP19]], <4 x i1> [[TMP24]], <4 x i1> [[TMP1]]
+; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP19]], <4 x i1> [[TMP33]], <4 x i1> [[TMP2]]
+; CHECK-VF4IC4-NEXT: [[TMP32]] = select i1 [[TMP19]], <4 x i1> [[TMP21]], <4 x i1> [[TMP3]]
; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP19]], <4 x i32> [[WIDE_LOAD13]], <4 x i32> [[VEC_PHI]]
; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP19]], <4 x i32> [[WIDE_LOAD8]], <4 x i32> [[VEC_PHI1]]
; CHECK-VF4IC4-NEXT: [[TMP30]] = select i1 [[TMP19]], <4 x i32> [[WIDE_LOAD11]], <4 x i32> [[VEC_PHI2]]
@@ -1488,10 +1488,10 @@
; CHECK-VF1IC4-NEXT: [[TMP47:%.*]] = or i1 [[TMP27]], [[TMP28]]
; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = or i1 [[TMP47]], [[TMP30]]
; CHECK-VF1IC4-NEXT: [[TMP33:%.*]] = or i1 [[TMP31]], [[TMP32]]
-; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP33]], i1 [[TMP23]], i1 [[TMP0]]
-; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP33]], i1 [[TMP24]], i1 [[TMP1]]
-; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP33]], i1 [[TMP25]], i1 [[TMP2]]
-; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP33]], i1 [[TMP26]], i1 [[TMP3]]
+; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP33]], i1 [[TMP27]], i1 [[TMP0]]
+; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP33]], i1 [[TMP28]], i1 [[TMP1]]
+; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP33]], i1 [[TMP30]], i1 [[TMP2]]
+; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP33]], i1 [[TMP32]], i1 [[TMP3]]
; CHECK-VF1IC4-NEXT: [[TMP38]] = select i1 [[TMP33]], i32 [[LOAD_V2_IV]], i32 [[VEC_PHI]]
; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP33]], i32 [[TMP20]], i32 [[VEC_PHI1]]
; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP33]], i32 [[TMP21]], i32 [[VEC_PHI2]]
