[AArch64] C1-Ultra Scheduling model (#182251)
This patch adds the C1-Ultra scheduling model. This model is largely
based on the Neoverse V3 scheduling model with appropriate changes made
based on information available in the software optimization guide for
this core.
https://developer.arm.com/documentation/111079/3-0
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index db3b19f..1d6cea3 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -119,6 +119,7 @@
include "AArch64SchedA55.td"
include "AArch64SchedA510.td"
include "AArch64SchedA57.td"
+include "AArch64SchedC1Ultra.td"
include "AArch64SchedCyclone.td"
include "AArch64SchedFalkor.td"
include "AArch64SchedKryo.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 129e49f..ab30474 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3274,7 +3274,6 @@
def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
logical_imm64:$imm), 0>;
-
// (register)
defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
defm BICS : LogicalRegS<0b11, 1, "bics",
@@ -3346,7 +3345,6 @@
def : Pat<(i64 (and GPR64:$Rn, 0xffffffff)),
(SUBREG_TO_REG (ORRWrr WZR, (EXTRACT_SUBREG GPR64:$Rn, sub_32)), sub_32)>;
-
//===----------------------------------------------------------------------===//
// One operand data processing instructions.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 94617ca..74b2700 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1489,7 +1489,7 @@
[TuneX925]>;
def : ProcessorModel<"c1-premium", NeoverseV3Model,
ProcessorFeatures.C1Premium, [TuneC1Premium]>;
-def : ProcessorModel<"c1-ultra", NeoverseV3Model,
+def : ProcessorModel<"c1-ultra", C1UltraModel,
ProcessorFeatures.C1Ultra, [TuneC1Ultra]>;
def : ProcessorModel<"gb10", NeoverseV3Model, ProcessorFeatures.GB10,
[TuneX925]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
new file mode 100644
index 0000000..1d2f960
--- /dev/null
+++ b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
@@ -0,0 +1,2459 @@
+//=- AArch64SchedC1Ultra.td - C1 Ultra Scheduling Defs --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the scheduling model for the C1 Ultra processors.
+// Information is taken from the C1 Ultra Software Optimization Guide
+//
+// https://developer.arm.com/documentation/111079/3-0
+//
+//===----------------------------------------------------------------------===//
+
+def C1UltraModel : SchedMachineModel {
+ let IssueWidth = 10;
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V3
+ let LoadLatency = 4; // Optimistic load latency. NOTE: Copied from Neoverse-V3
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N3.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasCPA, HasCSSC]);
+}
+
+//===----------------------------------------------------------------------===//
+// Define each kind of processor resource and number available on C1 Ultra.
+// Instructions are first fetched and then decoded into internal macro-ops
+// (MOPs). From there, the MOPs proceed through register renaming and dispatch
+// stages. A MOP can be split into two micro-ops further down the pipeline
+// after the decode stage.
+
+let SchedModel = C1UltraModel in {
+
+// Define the issue ports.
+def C1UUnitB : ProcResource<3>; // Branch 0/1/2
+def C1UUnitS0 : ProcResource<1>; // Integer single-cycle 0
+def C1UUnitS1 : ProcResource<1>; // Integer single-cycle 1
+def C1UUnitS2 : ProcResource<1>; // Integer single-cycle 2
+def C1UUnitS3 : ProcResource<1>; // Integer single-cycle 3
+def C1UUnitS4 : ProcResource<1>; // Integer single-cycle 4
+def C1UUnitS5 : ProcResource<1>; // Integer single-cycle 5
+def C1UUnitM0 : ProcResource<1>; // Integer single/multicycle 0
+def C1UUnitM1 : ProcResource<1>; // Integer single/multicycle 1
+def C1UUnitV0 : ProcResource<1>; // FP/ASIMD 0
+def C1UUnitV1 : ProcResource<1>; // FP/ASIMD 1
+def C1UUnitV2 : ProcResource<1>; // FP/ASIMD 2
+def C1UUnitV3 : ProcResource<1>; // FP/ASIMD 3
+def C1UUnitV4 : ProcResource<1>; // FP/ASIMD 4
+def C1UUnitV5 : ProcResource<1>; // FP/ASIMD 5
+def C1UUnitLS0 : ProcResource<1>; // Load/Store 0
+def C1UUnitLS1 : ProcResource<1>; // Load/Store 1
+def C1UUnitL23 : ProcResource<2>; // Load 2/3
+def C1UUnitD : ProcResource<2>; // Store data 0/1
+def C1UUnitCME : ProcResource<1>; // CME operations block
+def C1UUnitFlg : ProcResource<4>; // Flags
+
+def C1UUnitS : ProcResGroup<[C1UUnitS0, C1UUnitS1, C1UUnitS2, C1UUnitS3,
+ C1UUnitS4, C1UUnitS5]>;
+def C1UUnitI : ProcResGroup<[C1UUnitS0, C1UUnitS1, C1UUnitS2, C1UUnitS3,
+ C1UUnitS4, C1UUnitS5, C1UUnitM0, C1UUnitM1]>;
+def C1UUnitI4 : ProcResGroup<[C1UUnitS0, C1UUnitS2, C1UUnitS4, C1UUnitM0]>;
+def C1UUnitM : ProcResGroup<[C1UUnitM0, C1UUnitM1]>;
+def C1UUnitL : ProcResGroup<[C1UUnitLS0, C1UUnitLS1, C1UUnitL23]>;
+def C1UUnitSA : ProcResGroup<[C1UUnitLS0, C1UUnitLS1]>;
+def C1UUnitV : ProcResGroup<[C1UUnitV0, C1UUnitV1, C1UUnitV2,
+ C1UUnitV3, C1UUnitV4, C1UUnitV5]>;
+def C1UUnitV01 : ProcResGroup<[C1UUnitV0, C1UUnitV1]>;
+def C1UUnitV02 : ProcResGroup<[C1UUnitV0, C1UUnitV2]>;
+def C1UUnitV13 : ProcResGroup<[C1UUnitV1, C1UUnitV3]>;
+def C1UUnitV0123 : ProcResGroup<[C1UUnitV0, C1UUnitV1,
+ C1UUnitV2, C1UUnitV3]>;
+def C1UUnitV0134 : ProcResGroup<[C1UUnitV0, C1UUnitV1, C1UUnitV3, C1UUnitV4]>;
+
+// Define commonly used read types.
+def : ReadAdvance<ReadI, 0>;
+def : ReadAdvance<ReadISReg, 0>;
+def : ReadAdvance<ReadIEReg, 0>;
+def : ReadAdvance<ReadIM, 0>;
+def : ReadAdvance<ReadIMA, 0>;
+def : ReadAdvance<ReadID, 0>;
+def : ReadAdvance<ReadExtrHi, 0>;
+def : ReadAdvance<ReadAdrBase, 0>;
+def : ReadAdvance<ReadST, 0>;
+def : ReadAdvance<ReadVLD, 0>;
+
+def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
+def : WriteRes<WriteBarrier, []> { let Latency = 1; }
+def : WriteRes<WriteHint, []> { let Latency = 1; }
+def : WriteRes<WriteLDHi, []> { let Latency = 4; }
+
+//===----------------------------------------------------------------------===//
+// Define customized scheduler read/write types specific to C1 Ultra.
+//===----------------------------------------------------------------------===//
+
+// Define generic 0 micro-op types.
+def C1UWrite_0c : SchedWriteRes<[]> { let Latency = 0; }
+
+// Define a small set of generic 1 micro-op types as placeholders.
+def C1UWrite_1c_1B : SchedWriteRes<[C1UUnitB]> { let Latency = 1; }
+def C1UWrite_2c_1B : SchedWriteRes<[C1UUnitB]> { let Latency = 2; }
+def C1UWrite_1c_1I : SchedWriteRes<[C1UUnitI]> { let Latency = 1; }
+def C1UWrite_1c_2I : SchedWriteRes<[C1UUnitI, C1UUnitI]> { let Latency = 1; }
+def C1UWrite_2c_1I : SchedWriteRes<[C1UUnitI]> { let Latency = 2; }
+def C1UWrite_2c_2I : SchedWriteRes<[C1UUnitI, C1UUnitI]> { let Latency = 2; }
+def C1UWrite_3c_1I : SchedWriteRes<[C1UUnitI]> { let Latency = 3; }
+def C1UWrite_2c_1I4 : SchedWriteRes<[C1UUnitI4]> { let Latency = 2; }
+def C1UWrite_1c_1M : SchedWriteRes<[C1UUnitM]> { let Latency = 1; }
+def C1UWrite_1c_2M : SchedWriteRes<[C1UUnitM, C1UUnitM]> { let Latency = 1; }
+def C1UWrite_2c_1M : SchedWriteRes<[C1UUnitM]> { let Latency = 2; }
+def C1UWrite_2c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 2; }
+def C1UWrite_3c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 3; }
+def C1UWrite_4c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 4; }
+def C1UWrite_12c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 12;
+ let ReleaseAtCycles = [12]; }
+def C1UWrite_20c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 20;
+ let ReleaseAtCycles = [20]; }
+def C1UWrite_1c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 1; }
+def C1UWrite_2c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 2; }
+def C1UWrite_2c_3V : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 2; }
+def C1UWrite_3c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 3; }
+def C1UWrite_4c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1UWrite_4c_2V : SchedWriteRes<[C1UUnitV, C1UUnitV]> { let Latency = 4; }
+def C1UWrite_4c_3V : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 4; }
+def C1UWrite_6c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 6; }
+def C1UWrite_6c_3V : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 6; }
+def C1UWrite_6c_5V : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 6; }
+def C1UWrite_8c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 8; }
+def C1UWrite_8c_4V : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 8; }
+def C1UWrite_1c_1V0 : SchedWriteRes<[C1UUnitV0]> { let Latency = 1; }
+def C1UWrite_2c_1V0 : SchedWriteRes<[C1UUnitV0]> { let Latency = 2; }
+def C1UWrite_4c_1V0 : SchedWriteRes<[C1UUnitV0]> { let Latency = 4; }
+def C1UWrite_6c_1V0 : SchedWriteRes<[C1UUnitV0]> { let Latency = 6; }
+def C1UWrite_6c_6V0 : SchedWriteRes<[C1UUnitV0, C1UUnitV0, C1UUnitV0,
+ C1UUnitV0, C1UUnitV0, C1UUnitV0, ]> { let Latency = 6; }
+def C1UWrite_10c_1V0 : SchedWriteRes<[C1UUnitV0]> { let Latency = 10;}
+def C1UWrite_10c_10V0 : SchedWriteRes<[C1UUnitV0, C1UUnitV0, C1UUnitV0,
+ C1UUnitV0, C1UUnitV0, C1UUnitV0,
+ C1UUnitV0, C1UUnitV0, C1UUnitV0, C1UUnitV0
+ ]> { let Latency = 10;}
+def C1UWrite_12c_1V0 : SchedWriteRes<[C1UUnitV0]> { let Latency = 12; }
+def C1UWrite_12c_7V0 : SchedWriteRes<[C1UUnitV0, C1UUnitV0, C1UUnitV0, C1UUnitV0,
+ C1UUnitV0, C1UUnitV0, C1UUnitV0]> { let Latency = 12; }
+def C1UWrite_20c_1V0 : SchedWriteRes<[C1UUnitV0]> { let Latency = 20; }
+def C1UWrite_20c_7V0 : SchedWriteRes<[C1UUnitV0, C1UUnitV0, C1UUnitV0, C1UUnitV0,
+ C1UUnitV0, C1UUnitV0, C1UUnitV0]> { let Latency = 20; }
+def C1UWrite_3c_1V1 : SchedWriteRes<[C1UUnitV1]> { let Latency = 3; }
+def C1UWrite_5c_1V1 : SchedWriteRes<[C1UUnitV1]> { let Latency = 5; }
+def C1UWrite_8c_1V1 : SchedWriteRes<[C1UUnitV1]> { let Latency = 8; }
+def C1UWrite_12c_1V1 : SchedWriteRes<[C1UUnitV1]> { let Latency = 12; }
+def C1UWrite_2c_1V01 : SchedWriteRes<[C1UUnitV01]> { let Latency = 2; }
+def C1UWrite_3c_1V01 : SchedWriteRes<[C1UUnitV01]> { let Latency = 3; }
+def C1UWrite_2c_1V0134 : SchedWriteRes<[C1UUnitV0134 ]> { let Latency = 2; }
+def C1UWrite_3c_1V0134 : SchedWriteRes<[C1UUnitV0134]> { let Latency = 3; }
+def C1UWrite_3c_2V0134 : SchedWriteRes<[C1UUnitV0134, C1UUnitV0134]> { let Latency = 3; }
+def C1UWrite_4c_1V0134 : SchedWriteRes<[C1UUnitV0134]> { let Latency = 4; }
+def C1UWrite_4c_2V0134 : SchedWriteRes<[C1UUnitV0134, C1UUnitV0134]> { let Latency = 4; }
+def C1UWrite_6c_1V0134 : SchedWriteRes<[C1UUnitV0134]> { let Latency = 6; }
+def C1UWrite_6c_4V0134 : SchedWriteRes<[C1UUnitV0134, C1UUnitV0134, C1UUnitV0134, C1UUnitV0134]> { let Latency = 6;}
+def C1UWrite_1c_1L : SchedWriteRes<[C1UUnitL]> { let Latency = 1; }
+def C1UWrite_4c_1L : SchedWriteRes<[C1UUnitL]> { let Latency = 4; }
+def C1UWrite_6c_1L : SchedWriteRes<[C1UUnitL]> { let Latency = 6; }
+def C1UWrite_1c_1SA : SchedWriteRes<[C1UUnitSA]> { let Latency = 1; }
+
+def C1UWrite_2c_1B_1S : SchedWriteRes<[C1UUnitB, C1UUnitS]> { let Latency = 2; }
+
+def C1UWrite_1c_1I_1Flg : SchedWriteRes<[C1UUnitI, C1UUnitFlg]> { let Latency = 1; }
+def C1UWrite_1c_2I_2Flg : SchedWriteRes<[C1UUnitI, C1UUnitI, C1UUnitFlg, C1UUnitFlg]> { let Latency = 1; }
+def C1UWrite_2c_1I_1Flg : SchedWriteRes<[C1UUnitI, C1UUnitFlg]> { let Latency = 2; }
+
+def C1UWrite_1c_1SA_1D : SchedWriteRes<[C1UUnitSA, C1UUnitD]> { let Latency = 1; }
+
+def C1UWrite_1c_1SA_1D_1I : SchedWriteRes<[C1UUnitSA, C1UUnitD, C1UUnitI]> { let Latency = 1; }
+
+def C1UWrite_2c_1SA_1V01 : SchedWriteRes<[C1UUnitSA, C1UUnitV01]> { let Latency = 2; }
+def C1UWrite_2c_2SA_2V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitV01, C1UUnitV01]> { let Latency = 2; }
+def C1UWrite_2c_3SA_3V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01]> { let Latency = 2; }
+def C1UWrite_2c_4SA_4V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01]> { let Latency = 2; }
+def C1UWrite_2c_3SA_6V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01]> { let Latency = 2; }
+def C1UWrite_2c_1SA_1V01_1I : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitI]> { let Latency = 2; }
+
+def C1UWrite_2c_1I_1M : SchedWriteRes<[C1UUnitI, C1UUnitM]> { let Latency = 2; }
+
+def C1UWrite_2c_1L_1I : SchedWriteRes<[C1UUnitL, C1UUnitI]> { let Latency = 2; }
+
+def C1UWrite_3c_1I_1M : SchedWriteRes<[C1UUnitI, C1UUnitM]> {
+ let Latency = 3;
+}
+
+def C1UWrite_4c_2L : SchedWriteRes<[C1UUnitL, C1UUnitL]> { let Latency = 4; }
+def C1UWrite_4c_2L_1I : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitI]> { let Latency = 4; }
+
+def C1UWrite_5c_1L_1I : SchedWriteRes<[C1UUnitL, C1UUnitI]> {
+ let Latency = 5;
+}
+
+def C1UWrite_5c_2L_1I : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitI]> { let Latency = 5; }
+
+def C1UWrite_6c_1L_1I : SchedWriteRes<[C1UUnitL, C1UUnitI]> {
+ let Latency = 6;
+}
+
+def C1UWrite_6c_2L_1I : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitI]> { let Latency = 6; }
+
+def C1UWrite_7c_1L_1I : SchedWriteRes<[C1UUnitL, C1UUnitI]> {
+ let Latency = 7;
+}
+
+def C1UWrite_5c_1M0_1V : SchedWriteRes<[C1UUnitM0, C1UUnitV]> {
+ let Latency = 5;
+}
+def C1UWrite_2c_1M0_1V : SchedWriteRes<[C1UUnitM0, C1UUnitV]> {
+ let Latency = 2;
+}
+def C1UWrite_3c_1M0_1V : SchedWriteRes<[C1UUnitM0, C1UUnitV]> {
+ let Latency = 3;
+}
+
+def C1UWrite_4c_1V0134_1V : SchedWriteRes<[C1UUnitV0134, C1UUnitV]> { let Latency = 4; }
+
+def C1UWrite_8c_1V1_4rc : SchedWriteRes<[C1UUnitV1]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [4];
+}
+
+def C1UWrite_9c_1V1_2rc : SchedWriteRes<[C1UUnitV1]> {
+ let Latency = 9;
+ let ReleaseAtCycles = [2];
+}
+
+def C1UWrite_6c_1M0_1B : SchedWriteRes<[C1UUnitM0, C1UUnitB]> {
+ let Latency = 6;
+}
+
+def C1UWrite_6c_1M0_1B_1I : SchedWriteRes<[C1UUnitM0, C1UUnitB, C1UUnitI]> {
+ let Latency = 6;
+}
+
+def C1UWrite_9c_1M0_1L : SchedWriteRes<[C1UUnitM0, C1UUnitL]> {
+ let Latency = 9;
+}
+
+def C1UWrite_6c_2L : SchedWriteRes<[C1UUnitL, C1UUnitL]> {
+ let Latency = 6;
+}
+
+
+def C1UWrite_6c_3L : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL]> {
+ let Latency = 6;
+}
+
+def C1UWrite_6c_4L : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL, C1UUnitL]> {
+ let Latency = 6;
+}
+
+def C1UWrite_7c_4L : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL, C1UUnitL]> {
+ let Latency = 7;
+}
+
+def C1UWrite_8c_1L_1V : SchedWriteRes<[C1UUnitL, C1UUnitV]> {
+ let Latency = 8;
+}
+
+def C1UWrite_6c_1L_1V : SchedWriteRes<[C1UUnitL, C1UUnitV]> {
+ let Latency = 6;
+}
+
+def C1UWrite_8c_1L_2V : SchedWriteRes<[C1UUnitL, C1UUnitV, C1UUnitV]> {
+ let Latency = 8;
+}
+
+def C1UWrite_8c_2L_2V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitV, C1UUnitV]> {
+ let Latency = 8;
+}
+def C1UWrite_9c_2L_2V_1I : SchedWriteRes<[C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV,
+ C1UUnitI]> {
+ let Latency = 9;
+}
+
+def C1UWrite_8c_2L_3V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitV, C1UUnitV,
+ C1UUnitV]> {
+ let Latency = 8;
+}
+def C1UWrite_9c_2L_3V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitV, C1UUnitV,
+ C1UUnitV]> {
+ let Latency = 9;
+}
+
+def C1UWrite_8c_3L_3V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV]> {
+ let Latency = 8;
+}
+
+def C1UWrite_9c_3L_3V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV]> {
+ let Latency = 9;
+}
+
+def C1UWrite_9c_3L_3V_1I : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV,
+ C1UUnitI]> {
+ let Latency = 9;
+}
+def C1UWrite_10c_4L_8V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> {
+ let Latency = 10;
+}
+def C1UWrite_11c_4L_8V_1I : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV,
+ C1UUnitI]> {
+ let Latency = 11;
+}
+
+def C1UWrite_9c_6L_4V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitL, C1UUnitL, C1UUnitV, C1UUnitV,
+ C1UUnitV, C1UUnitV]> {
+ let Latency = 9;
+}
+
+def C1UWrite_9c_4L_8V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> {
+ let Latency = 9;
+}
+
+def C1UWrite_8c_3L_4V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> {
+ let Latency = 8;
+}
+
+def C1UWrite_8c_2L_4V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> {
+ let Latency = 8;
+}
+
+
+def C1UWrite_8c_4L_4V : SchedWriteRes<[C1UUnitL, C1UUnitL, C1UUnitL, C1UUnitL,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> {
+ let Latency = 8;
+}
+
+def C1UWrite_4c_1SA_1V01_1V : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitV]> { let Latency = 4; }
+def C1UWrite_4c_2SA_2V01_2V : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitV01, C1UUnitV01,
+ C1UUnitV, C1UUnitV]> { let Latency = 4; }
+def C1UWrite_5c_1SA_1V01_1V : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitV]> { let Latency = 5; }
+def C1UWrite_5c_5SA_5V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01]> {
+ let Latency = 5;
+}
+def C1UWrite_5c_4SA_4V01_4V : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 5; }
+
+def C1UWrite_6c_1SA_1V01_1V: SchedWriteRes<[C1UUnitSA,C1UUnitV01, C1UUnitV]> { let Latency = 6; }
+
+
+def C1UWrite_6c_6SA_6V01_6V: SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitV, C1UUnitV, C1UUnitV,
+ C1UUnitV, C1UUnitV, C1UUnitV ]> { let Latency = 6; }
+
+def C1UWrite_6c_8SA_8V01_8V: SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV,
+ C1UUnitV, C1UUnitV, C1UUnitV, C1UUnitV ]> { let Latency = 6; }
+
+
+def C1UWrite_7c_5SA_5V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01]> {
+ let Latency = 7;
+}
+
+def C1UWrite_7c_1SA_1V01_1V: SchedWriteRes<[
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+]> {
+ let Latency = 7;
+}
+
+def C1UWrite_7c_12SA_12V01_12V: SchedWriteRes<[
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV,
+ C1UUnitSA, C1UUnitV01, C1UUnitV
+]> {
+ let Latency = 7;
+}
+
+def C1UWrite_7c_1M_1M0_1V : SchedWriteRes<[C1UUnitM, C1UUnitM0, C1UUnitV]> { let Latency = 7; }
+
+def C1UWrite_6c_2V1 : SchedWriteRes<[C1UUnitV1, C1UUnitV1]> { let Latency = 6; }
+
+def C1UWrite_8c_1M0_1V1_1V01 : SchedWriteRes<[C1UUnitM0, C1UUnitV1, C1UUnitV01]> { let Latency = 8; }
+
+def C1UWrite_6c_1V1_1V01 : SchedWriteRes<[C1UUnitV1, C1UUnitV01]> { let Latency = 6; }
+def C1UWrite_5c_1V1_1V01 : SchedWriteRes<[C1UUnitV1, C1UUnitV01]> { let Latency = 5; }
+
+def C1UWrite_7c_1M0_1V0134 : SchedWriteRes<[C1UUnitM0, C1UUnitV0134]> { let Latency = 7; }
+
+def C1UWrite_5c_1V_1M0 : SchedWriteRes<[C1UUnitV, C1UUnitM0]> { let Latency = 5; }
+
+def C1UWrite_8c_1V_3V0134 : SchedWriteRes<[C1UUnitV, C1UUnitV0134, C1UUnitV0134, C1UUnitV0134]> { let Latency = 8; }
+
+def C1UWrite_6c_1V_2V0134 : SchedWriteRes<[C1UUnitV, C1UUnitV0134, C1UUnitV0134]> { let Latency = 6; }
+
+def C1UWrite_6c_2V_1V0134 : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV0134]> { let Latency = 6; }
+
+def C1UWrite_4c_1V_1V0134 : SchedWriteRes<[C1UUnitV, C1UUnitV0134]> { let Latency = 4; }
+
+def C1UWrite_12c_1V0_8rc : SchedWriteRes<[C1UUnitV0]> {
+ let Latency = 12;
+ let ReleaseAtCycles = [8];
+}
+
+def C1UWrite_11c_1V0_4rc : SchedWriteRes<[C1UUnitV0]> {
+ let Latency = 11;
+ let ReleaseAtCycles = [4];
+}
+
+def C1UWrite_13c_1V0_2rc : SchedWriteRes<[C1UUnitV0]> {
+ let Latency = 13;
+ let ReleaseAtCycles = [2];
+}
+
+def C1UWrite_12c_1V1_8rc : SchedWriteRes<[C1UUnitV1]> {
+ let Latency = 12;
+ let ReleaseAtCycles = [8];
+}
+
+def C1UWrite_11c_1V1_4rc : SchedWriteRes<[C1UUnitV1]> {
+ let Latency = 11;
+ let ReleaseAtCycles = [4];
+}
+
+def C1UWrite_13c_1V1_2rc : SchedWriteRes<[C1UUnitV1]> {
+ let Latency = 13;
+ let ReleaseAtCycles = [2];
+}
+
+def C1UWrite_6c_1L_1M : SchedWriteRes<[C1UUnitL, C1UUnitM]> {
+ let Latency = 6;
+}
+
+def C1UWrite_9c_1V01_1L : SchedWriteRes<[C1UUnitV01, C1UUnitL]> {
+ let Latency = 9;
+}
+
+def C1UWrite_9c_1I_1L_1V : SchedWriteRes<[C1UUnitI, C1UUnitL, C1UUnitV]> {
+ let Latency = 9;
+}
+
+def C1UWrite_10c_1L_1V : SchedWriteRes<[C1UUnitL, C1UUnitV]> {
+ let Latency = 10;
+}
+
+def C1UWrite_11c_1I_1L_1V : SchedWriteRes<[C1UUnitI, C1UUnitL, C1UUnitV]> {
+ let Latency = 11;
+}
+
+
+def C1UWrite_4c_1I_1V_1SA_V : SchedWriteRes<[C1UUnitI, C1UUnitV, C1UUnitSA, C1UUnitV]> {
+ let Latency = 4;
+}
+
+
+def C1UWrite_5c_1I_1V_1SA_V : SchedWriteRes<[C1UUnitI, C1UUnitV, C1UUnitSA, C1UUnitV]> {
+ let Latency = 5;
+}
+
+def C1UWrite_7c_1I_1V_1SA_V : SchedWriteRes<[C1UUnitI, C1UUnitV, C1UUnitSA, C1UUnitV]> {
+ let Latency = 7;
+}
+
+def C1UWrite_2c_1SA_2V01 : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitV01]> {
+ let Latency = 2;
+}
+def C1UWrite_4c_2SA_2V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01]> {
+ let Latency = 4;
+}
+def C1UWrite_4c_2SA_2V01_1I : SchedWriteRes<[C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01,
+ C1UUnitI]> {
+ let Latency = 4;
+}
+def C1UWrite_5c_3SA_3V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01]> {
+ let Latency = 5;
+}
+def C1UWrite_5c_3SA_3V01_1I : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitI]> {
+ let Latency = 5;
+}
+def C1UWrite_7c_4SA_4V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01]> {
+ let Latency = 7;
+}
+def C1UWrite_7c_4SA_4V01_1I : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitI]> {
+ let Latency = 7;
+}
+
+def C1UWrite_4c_1SA_1V01 : SchedWriteRes<[C1UUnitSA, C1UUnitV01]> { let Latency = 4; }
+def C1UWrite_4c_1SA_2V01 : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitV01]> { let Latency = 4; }
+def C1UWrite_4c_3SA_3V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01]> { let Latency = 4; }
+def C1UWrite_4c_3SA_6V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01]> { let Latency = 4; }
+
+def C1UWrite_5c_1SA_2V01 : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitV01]> { let Latency = 5; }
+def C1UWrite_5c_3SA_6V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01]> { let Latency = 5; }
+
+def C1UWrite_6c_1SA_2V01 : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitV01]> { let Latency = 6; }
+def C1UWrite_6c_3SA_3V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01, C1UUnitV01]> { let Latency = 6; }
+
+def C1UWrite_7c_1SA_2V01 : SchedWriteRes<[C1UUnitSA, C1UUnitV01, C1UUnitV01]> { let Latency = 7; }
+def C1UWrite_7c_3SA_6V01 : SchedWriteRes<[C1UUnitSA, C1UUnitSA, C1UUnitSA,
+ C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01,
+ C1UUnitV01, C1UUnitV01]> { let Latency = 7;}
+
+def C1UWrite_3c_1M0_1M : SchedWriteRes<[C1UUnitM0, C1UUnitM]> { let Latency = 3; }
+
+def C1UWrite_4c_1M0_1M : SchedWriteRes<[C1UUnitM0, C1UUnitM]> { let Latency = 4; }
+
+// Forwarded types
+def C1UWr_FMA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_FMA : SchedReadAdvance<2, [WriteFMul, C1UWr_FMA]>;
+
+def C1UWR_VA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_VA : SchedReadAdvance<3, [C1UWR_VA]>;
+
+def C1UWR_VDOT : SchedWriteRes<[C1UUnitV]> { let Latency = 3; }
+def C1URd_VDOT : SchedReadAdvance<2, [C1UWR_VDOT]>;
+
+def C1UWR_VMMA : SchedWriteRes<[C1UUnitV]> { let Latency = 3; }
+def C1URd_VMMA : SchedReadAdvance<2, [C1UWR_VMMA]>;
+
+def C1UWr_MA : SchedWriteRes<[C1UUnitI4]> { let Latency = 3; }
+def C1URd_MA : SchedReadAdvance<2, [C1UWr_MA]>;
+def C1UWrite_MAOrMul : SchedWriteVariant<[
+ SchedVar<IsReg3ZeroPred, [C1UWrite_2c_1I4]>,
+ SchedVar<NoSchedPred, [C1UWr_MA]>]>;
+
+def C1UWR_VMA : SchedWriteRes<[C1UUnitV0134]> { let Latency = 4; }
+def C1URd_VMA : SchedReadAdvance<3, [C1UWR_VMA]>;
+
+def C1UWR_VMAH : SchedWriteRes<[C1UUnitV0134]> { let Latency = 4; }
+def C1URd_VMAH : SchedReadAdvance<2, [C1UWR_VMAH]>;
+
+def C1UWR_VPA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_VPA : SchedReadAdvance<3, [C1UWR_VPA]>;
+
+def C1UWR_VSA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_VSA : SchedReadAdvance<3, [C1UWR_VSA]>;
+
+def C1UWR_VFCMA : SchedWriteRes<[C1UUnitV]> { let Latency = 5; }
+def C1URd_VFCMA : SchedReadAdvance<3, [C1UWR_VFCMA]>;
+
+def C1UWR_VFMA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_VFMA : SchedReadAdvance<2, [C1UWR_VFMA]>;
+
+def C1UWR_VBFDOT : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_VBFDOT : SchedReadAdvance<2, [C1UWR_VBFDOT]>;
+
+def C1UWR_VBFMMA : SchedWriteRes<[C1UUnitV]> { let Latency = 5; }
+def C1URd_VBFMMA : SchedReadAdvance<1, [C1UWR_VBFMMA]>;
+
+def C1UWR_VBFMAL : SchedWriteRes<[C1UUnitV]> { let Latency = 5; }
+def C1URd_VBFMAL : SchedReadAdvance<3, [C1UWR_VBFMAL]>;
+
+def C1UWr_ZA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_ZA : SchedReadAdvance<3, [C1UWr_ZA]>;
+def C1UWr_ZPA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_ZPA : SchedReadAdvance<3, [C1UWr_ZPA]>;
+def C1UWr_ZSA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_ZSA : SchedReadAdvance<3, [C1UWr_ZSA]>;
+
+def C1UWr_ZDOTB : SchedWriteRes<[C1UUnitV]> { let Latency = 3; }
+def C1URd_ZDOTB : SchedReadAdvance<2, [C1UWr_ZDOTB]>;
+def C1UWr_ZDOTH : SchedWriteRes<[C1UUnitV0134]> { let Latency = 3; }
+def C1URd_ZDOTH : SchedReadAdvance<2, [C1UWr_ZDOTH]>;
+
+def C1UWr_ZCMABHS : SchedWriteRes<[C1UUnitV0134]> { let Latency = 4; }
+def C1URd_ZCMABHS : SchedReadAdvance<3, [C1UWr_ZCMABHS]>;
+
+def C1UWr_ZMMA : SchedWriteRes<[C1UUnitV]> { let Latency = 3; }
+def C1URd_ZMMA : SchedReadAdvance<2, [C1UWr_ZMMA]>;
+
+def C1UWr_ZMA : SchedWriteRes<[C1UUnitV0134]> { let Latency = 4; }
+def C1URd_ZMA : SchedReadAdvance<3, [C1UWr_ZMA]>;
+
+def C1UWr_ZMASQL : SchedWriteRes<[C1UUnitV0134]> { let Latency = 4; }
+def C1URd_ZMASQL : SchedReadAdvance<2, [C1UWr_ZMASQL]>;
+
+def C1UWr_ZFCMA : SchedWriteRes<[C1UUnitV]> { let Latency = 5; }
+def C1URd_ZFCMA : SchedReadAdvance<3, [C1UWr_ZFCMA]>;
+
+def C1UWr_ZFMA : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_ZFMA : SchedReadAdvance<2, [C1UWr_ZFMA]>;
+
+def C1UWr_ZFMAL : SchedWriteRes<[C1UUnitV]> { let Latency = 5; }
+def C1URd_ZFMAL : SchedReadAdvance<3, [C1UWr_ZFMAL]>;
+
+
+def C1UWr_ZBFDOT : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
+def C1URd_ZBFDOT : SchedReadAdvance<2, [C1UWr_ZBFDOT]>;
+def C1UWr_ZBFMMA : SchedWriteRes<[C1UUnitV]> { let Latency = 5; }
+def C1URd_ZBFMMA : SchedReadAdvance<2, [C1UWr_ZBFMMA]>;
+def C1UWr_ZBFMAL : SchedWriteRes<[C1UUnitV]> { let Latency = 5; }
+def C1URd_ZBFMAL : SchedReadAdvance<3, [C1UWr_ZBFMAL]>;
+
+def C1UWr_Pred : SchedWriteRes<[C1UUnitM, C1UUnitM]> { let Latency = 2; }
+def C1URd_Pred : SchedReadAdvance<1, [C1UWr_Pred]>;
+
+// Predicate controlled types
+def C1UWrite_ArithI : SchedWriteVariant<[
+ SchedVar<IsCheapLSL, [C1UWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_1I]>]>;
+
+def C1UWrite_Extr : SchedWriteVariant<[
+ SchedVar<IsRORImmIdiomPred, [C1UWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1UWrite_3c_1I]>]>;
+
+def C1UWrite_LdrQ : SchedWriteVariant<[
+ SchedVar<FPIsQForm, [C1UWrite_7c_1L_1I]>,
+ SchedVar<NoSchedPred, [C1UWrite_6c_1L]>]>;
+
+def C1UWrite_StrQ : SchedWriteVariant<[
+ SchedVar<FPIsQForm, [C1UWrite_2c_1SA_1V01_1I]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_1SA_1V01]>]>;
+
+def C1UWrite_1or2c_1I : SchedWriteVariant<[
+ SchedVar<IsXOrWDest, [C1UWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_1I]>]>;
+
+def C1UWrite_1or2c_1I_1Flg : SchedWriteVariant<[
+ SchedVar<IsXOrWDest, [C1UWrite_1c_1I_1Flg]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_1I_1Flg]>]>;
+
+
+def C1UWrite_2or3c_1V0 : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [C1UWrite_1c_1V0]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_1V0]>]>;
+
+def C1UWrite_2or4c_1SA_1V01 : SchedWriteVariant<[
+ SchedVar<SameZRegDstSrcPred, [C1UWrite_4c_1SA_1V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_1SA_1V01]>]>;
+
+def C1UWrite_2or4c_3SA_6V01 : SchedWriteVariant<[
+ SchedVar<SameZRegDstSrcPred, [C1UWrite_4c_3SA_6V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_3SA_6V01]>]>;
+
+def C1UWrite_4or6c_1SA_2V01 : SchedWriteVariant<[
+ SchedVar<SameZRegDstSrcPred, [C1UWrite_6c_1SA_2V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_4c_1SA_2V01]>]>;
+
+def C1UWrite_4or6c_3SA_3V01 : SchedWriteVariant<[
+ SchedVar<SameZRegDstSrcPred, [C1UWrite_6c_3SA_3V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_4c_3SA_3V01]>]>;
+
+def C1UWrite_5or7c_1SA_2V01 : SchedWriteVariant<[
+ SchedVar<SameZRegDstSrcPred, [C1UWrite_7c_1SA_2V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_5c_1SA_2V01]>]>;
+
+def C1UWrite_5or7c_3SA_6V01 : SchedWriteVariant<[
+ SchedVar<SameZRegDstSrcPred, [C1UWrite_7c_3SA_6V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_5c_3SA_6V01]>]>;
+
+
+def C1UWrite_5or7c_5SA_5V01 : SchedWriteVariant<[
+ SchedVar<SameZRegDstSrcPred, [C1UWrite_7c_5SA_5V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_5c_5SA_5V01]>]>;
+
+def C1UWrite_3or4c_1M0_1M : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [C1UWrite_4c_1M0_1M]>,
+ SchedVar<NoSchedPred, [C1UWrite_3c_1M0_1M]>]>;
+
+
+// Miscellaneous
+// -----------------------------------------------------------------------------
+
+def : InstRW<[WriteI], (instrs COPY)>;
+
+
+//===----------------------------------------------------------------------===//
+// Instruction scheduling classes.
+//===----------------------------------------------------------------------===//
+
+// Branch instructions
+// -----------------------------------------------------------------------------
+
+// Branch, immed
+// Compare and branch
+def : SchedAlias<WriteBr, C1UWrite_2c_1B>;
+
+// Branch, register
+def : SchedAlias<WriteBrReg, C1UWrite_2c_1B>;
+
+// Branch and link, immed
+// Branch and link, register
+def : InstRW<[C1UWrite_2c_1B_1S], (instrs BL, BLR)>;
+
+
+// Arithmetic and logical operations
+// -----------------------------------------------------------------------------
+
+// ALU, basic
+def : SchedAlias<WriteI, C1UWrite_1c_1I>;
+
+// ALU, basic, flagset
+def : InstRW<[C1UWrite_1c_1I_1Flg],
+ (instregex "^(ADC|SBC)S[WX]r$",
+ "^ANDS[WX]ri$",
+ "^(AND|BIC)S[WX]rr$")>;
+
+// ALU, extend and shift
+def : SchedAlias<WriteIEReg, C1UWrite_1or2c_1I>;
+
+// ALU, extend and shift, flagset
+def : InstRW<[C1UWrite_1or2c_1I_1Flg],
+ (instregex "^(ADD|SUB)S[WX]r[irx]$",
+ "^(ADD|SUB)SXrx64$")>;
+def : InstRW<[C1UWrite_2c_1I_1Flg],
+ (instregex "^(ADD|SUB)S[WX]rs$")>;
+
+// Arithmetic, LSL shift, shift <= 4
+// Arithmetic, flagset, LSL shift, shift <= 4
+// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
+def : SchedAlias<WriteISReg, C1UWrite_ArithI>;
+
+// Arithmetic, immediate to logical address tag
+def : InstRW<[C1UWrite_2c_1I], (instrs ADDG, SUBG)>;
+
+// Conditional compare
+def : InstRW<[C1UWrite_1c_1I_1Flg], (instregex "^CCM[NP][WX][ir]")>;
+
+// Conditional select
+def : InstRW<[C1UWrite_1c_1I],
+ (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)[ir]")>;
+
+// Convert floating-point condition flags
+// Flag manipulation instructions
+def : WriteRes<WriteSys, []> { let Latency = 1; }
+def : InstRW<[C1UWrite_1c_1I], (instrs AXFLAG, XAFLAG)>;
+
+// Insert Random Tags
+def : InstRW<[C1UWrite_2c_1M], (instrs IRG, IRGstack)>;
+
+// Insert Tag Mask
+// Subtract Pointer
+def : InstRW<[C1UWrite_1c_1I], (instrs GMI, SUBP)>;
+
+// Subtract Pointer, flagset
+def : InstRW<[C1UWrite_1c_1I_1Flg], (instrs SUBPS)>;
+
+// Logical, shift, no flagset
+def : InstRW<[C1UWrite_1c_1I],
+ (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs",
+ "^ORR[WX]rs$")>;
+
+// Logical, shift, flagset
+def : InstRW<[C1UWrite_1c_1I_1Flg], (instregex "^(AND|BIC)S[WX]rs$")>;
+
+// Move and shift instructions
+// -----------------------------------------------------------------------------
+
+def : SchedAlias<WriteImm, C1UWrite_1c_1I>;
+
+// Divide and multiply instructions
+// -----------------------------------------------------------------------------
+
+// SDIV, UDIV
+def : SchedAlias<WriteID32, C1UWrite_12c_1M0>;
+def : SchedAlias<WriteID64, C1UWrite_20c_1M0>;
+
+def : SchedAlias<WriteIM32, C1UWrite_2c_1I4>;
+def : SchedAlias<WriteIM64, C1UWrite_2c_1I4>;
+
+// Multiply accumulate, W-form
+// Multiply accumulate, X-form
+def : InstRW<[C1UWrite_MAOrMul, ReadIM, ReadIM, C1URd_MA],
+ (instregex "^M(ADD|SUB)[WX]rrr$")>;
+
+// Multiply accumulate long
+def : InstRW<[C1UWrite_MAOrMul, ReadIM, ReadIM, C1URd_MA],
+ (instregex "^(S|U)M(ADD|SUB)Lrrr$")>;
+
+// Multiply high
+def : InstRW<[C1UWrite_2c_1I4], (instrs SMULHrr, UMULHrr)>;
+
+// Pointer Authentication Instructions (v8.3 PAC)
+// -----------------------------------------------------------------------------
+
+// Authenticate data address
+// Authenticate instruction address
+// Compute pointer authentication code for data address
+// Compute pointer authentication code, using generic key
+// Compute pointer authentication code for instruction address
+def : InstRW<[C1UWrite_4c_1M0], (instregex "^AUT", "^PAC")>;
+
+// Branch and link, register, with pointer authentication
+def : InstRW<[C1UWrite_6c_1M0_1B_1I], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ)>;
+
+// Branch, register, with pointer authentication
+// Branch, return, with pointer authentication
+def : InstRW<[C1UWrite_6c_1M0_1B], (instrs BRAA, BRAAZ, BRAB, BRABZ,
+ RETAA, RETAB, ERETAA, ERETAB)>;
+
+
+// Load register, with pointer authentication
+def : InstRW<[C1UWrite_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
+
+// Strip pointer authentication code
+def : InstRW<[C1UWrite_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;
+
+// Miscellaneous data-processing instructions
+// -----------------------------------------------------------------------------
+
+// Address generation
+def : InstRW<[C1UWrite_1c_1I], (instrs ADR, ADRP)>;
+
+// Bitfield extract, one reg
+// Bitfield extract, two regs
+def : SchedAlias<WriteExtr, C1UWrite_Extr>;
+def : InstRW<[C1UWrite_Extr], (instrs EXTRWrri, EXTRXrri)>;
+
+// Bitfield move, basic
+def : SchedAlias<WriteIS, C1UWrite_1c_1I>;
+
+// Bitfield move, insert
+def : InstRW<[C1UWrite_2c_1I], (instregex "^BFM[WX]ri$")>;
+
+// Count leading
+// Move immed
+// Reverse bits/bytes
+// Variable shift
+def : InstRW<[C1UWrite_1c_1I],
+ (instregex "^(CLS|CLZ)(W|X)r",
+ "^(MOVN|MOVK|MOVZ)(W|X)i",
+ "^(RBIT|REV(16|32)?)(W|X)r",
+ "^(ASRV|LSLV|LSRV|RORV)(W|X)r")>;
+// Load instructions
+// -----------------------------------------------------------------------------
+
+def : SchedAlias<WriteLD, C1UWrite_4c_1L>;
+def : SchedAlias<WriteLDIdx, C1UWrite_4c_1L>;
+
+// Load register, literal
+def : InstRW<[C1UWrite_5c_1L_1I], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;
+
+// Load pair, signed immed offset, normal X form
+// Load pair, signed immed post-index or immed pre-index, normal X form
+def : InstRW<[C1UWrite_4c_2L], (instrs LDPXi, LDNPXi)>;
+def : InstRW<[C1UWrite_4c_2L_1I], (instrs LDPXpre, LDPXpost)>;
+
+// Load pair, signed immed offset, signed words
+def : InstRW<[C1UWrite_5c_2L_1I, WriteLDHi], (instrs LDPSWi)>;
+
+// Load pair, immed post-index or immed pre-index, signed words
+def : InstRW<[WriteAdr, C1UWrite_5c_2L_1I, WriteLDHi],
+ (instregex "^LDPSW(post|pre)$")>;
+
+// Store instructions
+// -----------------------------------------------------------------------------
+
+def : SchedAlias<WriteST, C1UWrite_1c_1SA_1D>;
+def : SchedAlias<WriteSTIdx, C1UWrite_1c_1SA_1D_1I>;
+def : SchedAlias<WriteSTP, C1UWrite_1c_1SA_1D>;
+def : SchedAlias<WriteAdr, C1UWrite_1c_1I>;
+
+// Tag load instructions
+// -----------------------------------------------------------------------------
+
+// Load allocation tag
+// Load multiple allocation tags
+def : InstRW<[C1UWrite_4c_1L], (instrs LDG, LDGM)>;
+
+// Tag store instructions
+// -----------------------------------------------------------------------------
+
+// Store allocation tags to one or two granules, post-index
+// Store allocation tags to one or two granules, pre-index
+// Store allocation tag to one or two granules, zeroing, post-index
+// Store Allocation Tag to one or two granules, zeroing, pre-index
+// Store allocation tag and reg pair to memory, post-Index
+// Store allocation tag and reg pair to memory, pre-Index
+def : InstRW<[C1UWrite_1c_1SA_1D_1I], (instrs STGPreIndex, STGPostIndex,
+ ST2GPreIndex, ST2GPostIndex,
+ STZGPreIndex, STZGPostIndex,
+ STZ2GPreIndex, STZ2GPostIndex,
+ STGPpre, STGPpost)>;
+
+// Store allocation tags to one or two granules, signed offset
+// Store allocation tag to two granules, zeroing, signed offset
+// Store allocation tag and reg pair to memory, signed offset
+// Store multiple allocation tags
+def : InstRW<[C1UWrite_1c_1SA_1D], (instrs STGi, ST2Gi, STZGi,
+ STZ2Gi, STGPi, STGM, STZGM)>;
+
+// FP data processing instructions
+// -----------------------------------------------------------------------------
+
+// FP absolute value
+// FP arithmetic
+// FP min/max
+// FP negate
+// FP select
+def : SchedAlias<WriteF, C1UWrite_2c_1V>;
+
+// FP compare
+def : SchedAlias<WriteFCmp, C1UWrite_2c_1V01>;
+
+// FP divide
+def : SchedAlias<WriteFDiv, C1UWrite_5c_1V1>;
+
+// FP divide, H-form
+def : InstRW<[C1UWrite_5c_1V1], (instrs FDIVHrr)>;
+// FP divide, S-form
+def : InstRW<[C1UWrite_8c_1V1], (instrs FDIVSrr)>;
+// FP divide, D-form
+def : InstRW<[C1UWrite_12c_1V1], (instrs FDIVDrr)>;
+
+// FP square root, H-form
+def : InstRW<[C1UWrite_5c_1V1], (instrs FSQRTHr)>;
+// FP square root, S-form
+def : InstRW<[C1UWrite_8c_1V1], (instrs FSQRTSr)>;
+// FP square root, D-form
+def : InstRW<[C1UWrite_12c_1V1], (instrs FSQRTDr)>;
+
+// FP multiply
+def : WriteRes<WriteFMul, [C1UUnitV]> { let Latency = 3; }
+
+// FP multiply accumulate
+def : InstRW<[C1UWr_FMA, ReadDefault, ReadDefault, C1URd_FMA],
+ (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;
+
+// FP round to integral
+def : InstRW<[C1UWrite_2c_1V0134], (instregex "^FRINT[AIMNPXZ][HSD]r$",
+ "^FRINT(32|64)[XZ][SD]r$")>;
+
+
+// FP miscellaneous instructions
+// -----------------------------------------------------------------------------
+
+// FP convert, from gen to vec reg
+def : InstRW<[C1UWrite_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
+
+// FP convert, from vec to gen reg
+def : InstRW<[C1UWrite_3c_1V01],
+ (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;
+
+// FP convert, Javascript from vec to gen reg
+def : SchedAlias<WriteFCvt, C1UWrite_3c_1V01>;
+
+// FP convert, from vec to vec reg
+def : InstRW<[C1UWrite_3c_1V0134], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,
+ FCVTHDr, FCVTSDr, FCVTXNv1i64)>;
+
+// FP move, immed
+// FP move, register
+def : SchedAlias<WriteFImm, C1UWrite_2c_1V>;
+
+// FP transfer, from gen to low half of vec reg
+def : InstRW<[C1UWrite_3c_1M0],
+ (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
+
+// FP transfer, from gen to high half of vec reg
+def : InstRW<[C1UWrite_5c_1M0_1V], (instrs FMOVXDHighr)>;
+
+// FP transfer, from vec to gen reg
+def : SchedAlias<WriteFCopy, C1UWrite_2c_1V01>;
+
+// FP load instructions
+// -----------------------------------------------------------------------------
+
+// Load vector reg, literal, S/D/Q forms
+def : InstRW<[C1UWrite_7c_1L_1I], (instregex "^LDR[SDQ]l$")>;
+
+// Load vector reg, unscaled immed
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LDUR[BHSDQ]i$")>;
+
+// Load vector reg, immed post-index
+// Load vector reg, immed pre-index
+def : InstRW<[WriteAdr, C1UWrite_6c_1L_1I],
+ (instregex "^LDR[BHSDQ](pre|post)$")>;
+
+// Load vector reg, unsigned immed
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;
+
+// Load vector reg, register offset, basic
+// Load vector reg, register offset, scale, S/D-form
+// Load vector reg, register offset, scale, H/Q-form
+// Load vector reg, register offset, extend
+// Load vector reg, register offset, extend, scale, S/D-form
+// Load vector reg, register offset, extend, scale, H/Q-form
+def : InstRW<[C1UWrite_LdrQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>;
+
+// Load vector pair, immed offset, S/D-form
+// Load vector pair, immed offset, Q-form
+def : InstRW<[C1UWrite_6c_1L, WriteLDHi], (instregex "^LDN?P[SDQ]i$")>;
+
+// Load vector pair, immed post-index, S/D-form
+// Load vector pair, immed pre-index, S/D-form
+def : InstRW<[WriteAdr, C1UWrite_6c_1L_1I, WriteLDHi],
+ (instregex "^LDP[SD](pre|post)$")>;
+
+// Load vector pair, immed post-index, Q-form
+// Load vector pair, immed pre-index, Q-form
+def : InstRW<[WriteAdr, C1UWrite_6c_2L_1I, WriteLDHi],
+ (instregex "^LDPQ(pre|post)$")>;
+
+// FP store instructions
+// -----------------------------------------------------------------------------
+
+// Store vector reg, unscaled immed, B/H/S/D-form
+// Store vector reg, unscaled immed, Q-form
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "^STUR[BHSDQ]i$")>;
+
+// Store vector reg, immed post-index, B/H/S/D-form
+// Store vector reg, immed post-index, Q-form
+// Store vector reg, immed pre-index, B/H/S/D-form
+// Store vector reg, immed pre-index, Q-form
+def : InstRW<[WriteAdr, C1UWrite_2c_1SA_1V01_1I],
+ (instregex "^STR[BHSDQ](pre|post)$")>;
+
+// Store vector reg, unsigned immed, B/H/S/D-form
+// Store vector reg, unsigned immed, Q-form
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "^STR[BHSDQ]ui$")>;
+
+// Store vector reg, register offset, basic, B/H/S/D-form
+// Store vector reg, register offset, basic, Q-form
+// Store vector reg, register offset, scale, H-form
+// Store vector reg, register offset, scale, S/D-form
+// Store vector reg, register offset, scale, Q-form
+// Store vector reg, register offset, extend, B/H/S/D-form
+// Store vector reg, register offset, extend, Q-form
+// Store vector reg, register offset, extend, scale, H-form
+// Store vector reg, register offset, extend, scale, S/D-form
+// Store vector reg, register offset, extend, scale, Q-form
+def : InstRW<[C1UWrite_StrQ, ReadAdrBase],
+ (instregex "^STR[BHSDQ]ro[WX]$")>;
+
+// Store vector pair, immed offset, S-form
+// Store vector pair, immed offset, D-form
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "^STN?P[SD]i$")>;
+
+// Store vector pair, immed offset, Q-form
+def : InstRW<[C1UWrite_2c_2SA_2V01], (instregex "^STN?PQi$")>;
+
+// Store vector pair, immed post-index, S-form
+// Store vector pair, immed post-index, D-form
+// Store vector pair, immed pre-index, S-form
+// Store vector pair, immed pre-index, D-form
+def : InstRW<[WriteAdr, C1UWrite_2c_1SA_1V01_1I],
+ (instregex "^STP[SD](pre|post)$")>;
+
+// Store vector pair, immed post-index, Q-form
+// Store vector pair, immed pre-index, Q-form
+def : InstRW<[C1UWrite_2c_2SA_2V01], (instregex "^STPQ(post|pre)")>;
+
+// ASIMD integer instructions
+// -----------------------------------------------------------------------------
+
+// ASIMD absolute diff
+// ASIMD absolute diff long
+// ASIMD arith, basic
+// ASIMD arith, complex
+// ASIMD arith, pair-wise
+// ASIMD compare
+// ASIMD logical
+def : SchedAlias<WriteVd, C1UWrite_2c_1V>;
+def : SchedAlias<WriteVq, C1UWrite_2c_1V>;
+
+// ASIMD absolute diff accum
+// ASIMD absolute diff accum long
+def : InstRW<[C1UWR_VA, C1URd_VA, C1URd_VA], (instregex "^[SU]ABAL?v")>;
+
+// ASIMD arith, reduce, 4H/4S
+def : InstRW<[C1UWrite_2c_1V0134], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;
+
+// ASIMD arith, reduce, 8B/8H
+def : InstRW<[C1UWrite_4c_1V0134],
+ (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;
+
+// ASIMD arith, reduce, 16B
+def : InstRW<[C1UWrite_4c_2V0134], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>;
+
+// ASIMD dot product
+// ASIMD dot product using signed and unsigned integers
+def : InstRW<[C1UWR_VDOT, C1URd_VDOT],
+ (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;
+
+// ASIMD matrix multiply-accumulate
+def : InstRW<[C1UWR_VMMA, C1URd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;
+
+// ASIMD max/min, basic and pair-wise
+def : InstRW<[C1UWrite_2c_1V], (instregex "^[SU](MAX|MIN)P?(v16|v8)i8")>;
+
+// ASIMD max/min, reduce, 4H/4S
+def : InstRW<[C1UWrite_2c_1V0134], (instregex "^[SU](MAX|MIN)Vv4i16v$",
+ "^[SU](MAX|MIN)Vv4i32v$")>;
+
+// ASIMD max/min, reduce, 8B/8H
+def : InstRW<[C1UWrite_4c_1V0134_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",
+ "^[SU](MAX|MIN)Vv8i16v$")>;
+
+// ASIMD max/min, reduce, 16B
+def : InstRW<[C1UWrite_4c_2V0134], (instregex "[SU](MAX|MIN)Vv16i8v")>;
+// ASIMD multiply
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^MULv", "^SQ(R)?DMULHv")>;
+
+// ASIMD multiply accumulate
+// ASIMD multiply accumulate long
+def : InstRW<[C1UWR_VMA, C1URd_VMA, C1URd_VMA], (instregex "^MLAv", "^MLSv",
+ "^[SU]MLALv", "^[SU]MLSLv")>;
+
+// ASIMD multiply accumulate high
+def : InstRW<[C1UWR_VMAH, C1URd_VMAH, C1URd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;
+
+// ASIMD multiply accumulate saturating long
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^SQDML[AS]L[iv]")>;
+
+// ASIMD multiply/multiply long (8x8) polynomial, D-form
+// ASIMD multiply/multiply long (8x8) polynomial, Q-form
+def : InstRW<[C1UWrite_2c_1V0134], (instregex "^PMULL?(v8i8|v16i8)$")>;
+
+// ASIMD multiply long
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>;
+
+// ASIMD pairwise add and accumulate long
+def : InstRW<[C1UWR_VPA, C1URd_VPA, C1URd_VPA], (instregex "^[SU]ADALPv")>;
+
+// ASIMD shift accumulate
+def : InstRW<[C1UWR_VSA, C1URd_VSA], (instregex "^[SU]SRA[dv]", "^[SU]RSRA[dv]")>;
+
+// ASIMD shift by immed, basic
+def : InstRW<[C1UWrite_2c_1V], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv",
+ "^SSHLLv", "^SSHR[dv]", "^USHLLv",
+ "^USHR[dv]")>;
+
+// ASIMD shift by immed and insert, basic
+def : InstRW<[C1UWrite_2c_1V], (instregex "^SLI[dv]", "^SRI[dv]")>;
+
+// ASIMD shift by immed, complex
+// ASIMD shift by register, complex
+def : InstRW<[C1UWrite_4c_1V],
+ (instregex "^RSHRNv", "^SQRSHRU?N[bhsv]", "^(SQSHLU?|UQSHL)[bhsd]$",
+ "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",
+ "^SQSHRU?N[bhsv]", "^SRSHR[dv]", "^UQRSHRN[bhsv]",
+ "^UQSHRN[bhsv]", "^URSHR[dv]",
+ "^[SU]RSHLv", "^[SU]QRSHLv",
+ "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;
+
+// ASIMD shift by register, basic
+def : InstRW<[C1UWrite_2c_1V], (instregex "^[SU]SHLv")>;
+
+// ASIMD floating-point instructions
+// -----------------------------------------------------------------------------
+
+// ASIMD FP absolute value/difference
+// ASIMD FP arith, normal
+// ASIMD FP compare
+// ASIMD FP max/min, normal
+// ASIMD FP negate
+// Handled by SchedAlias<WriteV[dq], ...>
+
+// ASIMD FP complex add
+// ASIMD FP max/min, pairwise
+def : InstRW<[C1UWrite_3c_1V], (instregex "^FCADDv",
+ "^(FMAXP|FMAXNMP|FMINP|FMINNMP)v")>;
+
+// ASIMD FP complex multiply add
+def : InstRW<[C1UWR_VFCMA, C1URd_VFCMA, C1URd_VFCMA], (instregex "^FCMLAv")>;
+
+// ASIMD FP convert, long (F16 to F32)
+// ASIMD FP convert, long (F32 to F64)
+// ASIMD FP convert, narrow (F32 to F16)
+// ASIMD FP convert, narrow (F64 to F32)
+// ASIMD FP convert, other, D-form F32 and Q-form F64
+// ASIMD FP convert, other, D-form F16 and Q-form F32
+// ASIMD FP convert, other, Q-form F16
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FCVTL(v4|v8)(i16|i32)",
+ "^FCVTLv2i32",
+ "^FCVTN(v4|v8)i16",
+ "^FCVTN(v2|v4)i32",
+ "^FCVTXN(v2|v4)f32",
+ "^FCVT[AMNPZ][SU]v2f(32|64)$",
+ "^FCVT[AMNPZ][SU]v2i(32|64)_shift$",
+ "^FCVT[AMNPZ][SU]v1i64$",
+ "^FCVTZ[SU]d$",
+ "^[SU]CVTFv2f(32|64)$",
+ "^[SU]CVTFv2i(32|64)_shift$",
+ "^[SU]CVTFv1i64$",
+ "^[SU]CVTFd$",
+ "^FCVT[AMNPZ][SU]v4f(16|32)$",
+ "^FCVT[AMNPZ][SU]v4i(16|32)_shift$",
+ "^FCVT[AMNPZ][SU]v1i32$",
+ "^FCVTZ[SU]s$",
+ "^[SU]CVTFv4f(16|32)$",
+ "^[SU]CVTFv4i(16|32)_shift$",
+ "^[SU]CVTFv1i32$",
+ "^[SU]CVTFs$",
+ "^FCVT[AMNPZ][SU]v8f16$",
+ "^FCVT[AMNPZ][SU]v8i16_shift$",
+ "^FCVT[AMNPZ][SU]v1f16$",
+ "^FCVTZ[SU]h$",
+ "^[SU]CVTFv8f16$",
+ "^[SU]CVTFv8i16_shift$",
+ "^[SU]CVTFv1i16$",
+ "^[SU]CVTFh$")>;
+
+// ASIMD FP divide, D-form, F16
+def : InstRW<[C1UWrite_8c_1V1_4rc], (instrs FDIVv4f16)>;
+
+// ASIMD FP divide, D-form, F32
+def : InstRW<[C1UWrite_9c_1V1_2rc], (instrs FDIVv2f32)>;
+
+// ASIMD FP divide, Q-form, F16
+def : InstRW<[C1UWrite_12c_1V1_8rc], (instrs FDIVv8f16)>;
+
+// ASIMD FP divide, Q-form, F32
+def : InstRW<[C1UWrite_11c_1V1_4rc], (instrs FDIVv4f32)>;
+
+// ASIMD FP divide, Q-form, F64
+def : InstRW<[C1UWrite_13c_1V1_2rc], (instrs FDIVv2f64)>;
+
+// ASIMD FP max/min, reduce, F32 and D-form F16
+def : InstRW<[C1UWrite_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
+
+// ASIMD FP max/min, reduce, Q-form F16
+def : InstRW<[C1UWrite_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
+
+// ASIMD FP multiply
+def : InstRW<[C1UWrite_3c_1V], (instregex "^FMULv", "^FMULXv")>;
+def : InstRW<[C1UWrite_3c_1V], (instrs FMULX16, FMULX32, FMULX64)>;
+
+// ASIMD FP multiply accumulate
+// ASIMD FP multiply accumulate long
+def : InstRW<[C1UWR_VFMA, C1URd_VFMA, C1URd_VFMA], (instregex "^FMLAv", "^FMLSv",
+ "^FML[AS]L2?(lane)?v")>;
+
+// ASIMD FP round, D-form F32 and Q-form F64
+def : InstRW<[C1UWrite_3c_1V0134],
+ (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",
+ "^FRINT(32|64)[XZ]v2f(32|64)$")>;
+
+// ASIMD FP round, D-form F16 and Q-form F32
+def : InstRW<[C1UWrite_3c_1V0134],
+ (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",
+ "^FRINT(32|64)[XZ]v4f32$")>;
+
+// ASIMD FP round, Q-form F16
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
+
+// ASIMD FP square root, D-form, F16
+def : InstRW<[C1UWrite_8c_1V1_4rc], (instrs FSQRTv4f16)>;
+
+// ASIMD FP square root, D-form, F32
+def : InstRW<[C1UWrite_9c_1V1_2rc], (instrs FSQRTv2f32)>;
+
+// ASIMD FP square root, Q-form, F16
+def : InstRW<[C1UWrite_12c_1V1_8rc], (instrs FSQRTv8f16)>;
+
+// ASIMD FP square root, Q-form, F32
+def : InstRW<[C1UWrite_11c_1V1_4rc], (instrs FSQRTv4f32)>;
+
+// ASIMD FP square root, Q-form, F64
+def : InstRW<[C1UWrite_13c_1V1_2rc], (instrs FSQRTv2f64)>;
+
+// ASIMD BFloat16 (BF16) instructions
+// -----------------------------------------------------------------------------
+
+// ASIMD convert, F32 to BF16
+// Scalar convert, F32 to BF16
+def : InstRW<[C1UWrite_3c_1V0134], (instrs BFCVTN, BFCVTN2, BFCVT)>;
+
+// ASIMD dot product
+def : InstRW<[C1UWR_VBFDOT, C1URd_VBFDOT, C1URd_VBFDOT],
+ (instregex "^BFDOTv[48]bf16$",
+ "^BF16DOTlanev[48]bf16$")>;
+
+// ASIMD matrix multiply accumulate
+def : InstRW<[C1UWR_VBFMMA, C1URd_VBFMMA, C1URd_VBFMMA], (instrs BFMMLA)>;
+
+// ASIMD multiply accumulate long
+def : InstRW<[C1UWR_VBFMAL, C1URd_VBFMAL, C1URd_VBFMAL], (instrs BFMLALB, BFMLALBIdx, BFMLALT,
+ BFMLALTIdx)>;
+
+// ASIMD miscellaneous instructions
+// -----------------------------------------------------------------------------
+
+// ASIMD bit reverse
+// ASIMD bitwise insert
+// ASIMD count
+// ASIMD duplicate, element
+// ASIMD extract
+// ASIMD extract narrow
+// ASIMD insert, element to element
+// ASIMD move, FP immed
+// ASIMD move, integer immed
+// ASIMD reverse
+// ASIMD table lookup extension, 1 table reg
+// ASIMD transpose
+// ASIMD unzip/zip
+// Handled by SchedAlias<WriteV[dq], ...>
+
+// ASIMD duplicate, gen reg
+def : InstRW<[C1UWrite_3c_1M0], (instregex "^DUPv.+gpr")>;
+
+// ASIMD extract narrow, saturating
+def : InstRW<[C1UWrite_4c_1V], (instregex "^[SU]QXTNv", "^SQXTUNv")>;
+
+// ASIMD reciprocal and square root estimate, D-form U32
+def : InstRW<[C1UWrite_4c_2V0134], (instrs URECPEv2i32, URSQRTEv2i32)>;
+
+// ASIMD reciprocal and square root estimate, Q-form U32
+def : InstRW<[C1UWrite_4c_2V0134], (instrs URECPEv4i32, URSQRTEv4i32)>;
+
+// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms
+def : InstRW<[C1UWrite_3c_1V0134], (instrs FRECPEv1f16, FRECPEv1i32,
+ FRECPEv1i64, FRECPEv2f32, FRECPEv2f64,
+ FRSQRTEv1f16, FRSQRTEv1i32,
+ FRSQRTEv1i64, FRSQRTEv2f32, FRSQRTEv2f64)>;
+
+// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32
+def : InstRW<[C1UWrite_4c_2V0134], (instrs FRECPEv4f16, FRECPEv4f32,
+ FRSQRTEv4f16, FRSQRTEv4f32)>;
+
+// ASIMD reciprocal and square root estimate, Q-form F16
+def : InstRW<[C1UWrite_6c_4V0134], (instrs FRECPEv8f16, FRSQRTEv8f16)>;
+
+// ASIMD reciprocal exponent
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FRECPXv")>;
+
+// ASIMD reciprocal step
+def : InstRW<[C1UWrite_4c_1V], (instregex "^FRECPS(16|32|64|v)",
+ "^FRSQRTS(16|32|64|v)")>;
+
+// ASIMD table lookup, 1 or 2 table regs
+def : InstRW<[C1UWrite_2c_1V], (instrs TBLv8i8One, TBLv16i8One,
+ TBLv8i8Two, TBLv16i8Two)>;
+
+// ASIMD table lookup, 3 table regs
+def : InstRW<[C1UWrite_4c_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;
+
+// ASIMD table lookup, 4 table regs
+def : InstRW<[C1UWrite_4c_3V], (instrs TBLv8i8Four, TBLv16i8Four)>;
+
+// ASIMD table lookup extension, 2 table reg
+def : InstRW<[C1UWrite_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;
+
+// ASIMD table lookup extension, 3 table reg
+def : InstRW<[C1UWrite_6c_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;
+
+// ASIMD table lookup extension, 4 table reg
+def : InstRW<[C1UWrite_6c_5V], (instrs TBXv8i8Four, TBXv16i8Four)>;
+
+// ASIMD transfer, element to gen reg
+def : InstRW<[C1UWrite_2c_3V], (instregex "^SMOVv")>;
+def : InstRW<[C1UWrite_2c_3V], (instregex "^UMOVvi(8|16)(_idx0)?$")>;
+def : InstRW<[C1UWrite_2c_1V], (instregex "^UMOVvi(32|64)$")>;
+
+// ASIMD transfer, gen reg to element
+def : InstRW<[C1UWrite_2c_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
+
+// ASIMD load instructions
+// -----------------------------------------------------------------------------
+
+// ASIMD load, 1 element, multiple, 1 reg, D-form
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_1L],
+ (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 1 element, multiple, 1 reg, Q-form
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_1L],
+ (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 1 element, multiple, 2 reg, D-form
+def : InstRW<[C1UWrite_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_2L],
+ (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 1 element, multiple, 2 reg, Q-form
+def : InstRW<[C1UWrite_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_2L],
+ (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 1 element, multiple, 3 reg, D-form
+def : InstRW<[C1UWrite_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_3L],
+ (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 1 element, multiple, 3 reg, Q-form
+def : InstRW<[C1UWrite_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_3L],
+ (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 1 element, multiple, 4 reg, D-form
+def : InstRW<[C1UWrite_6c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_7c_4L],
+ (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 1 element, multiple, 4 reg, Q-form
+def : InstRW<[C1UWrite_6c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_7c_4L],
+ (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 1 element, one lane, B/H/S
+// ASIMD load, 1 element, one lane, D
+def : InstRW<[C1UWrite_6c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;
+
+// ASIMD load, 1 element, all lanes, D-form, B/H/S
+// ASIMD load, 1 element, all lanes, D-form, D
+def : InstRW<[C1UWrite_6c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 1 element, all lanes, Q-form
+def : InstRW<[C1UWrite_6c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 2 element, multiple, D-form, B/H/S
+def : InstRW<[C1UWrite_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
+
+// ASIMD load, 2 element, multiple, Q-form, B/H/S
+// ASIMD load, 2 element, multiple, Q-form, D
+def : InstRW<[C1UWrite_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 2 element, one lane, B/H
+// ASIMD load, 2 element, one lane, S
+// ASIMD load, 2 element, one lane, D
+def : InstRW<[C1UWrite_8c_1L_2V], (instregex "LD2i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;
+
+// ASIMD load, 2 element, all lanes, D-form, B/H/S
+// ASIMD load, 2 element, all lanes, D-form, D
+def : InstRW<[C1UWrite_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 2 element, all lanes, Q-form
+def : InstRW<[C1UWrite_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 3 element, multiple, D-form, B/H/S
+def : InstRW<[C1UWrite_9c_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, C1UWrite_9c_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
+
+// ASIMD load, 3 element, multiple, Q-form, B/H/S
+// ASIMD load, 3 element, multiple, Q-form, D
+def : InstRW<[C1UWrite_9c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_9c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 3 element, one lane, B/H
+// ASIMD load, 3 element, one lane, S
+// ASIMD load, 3 element, one lane, D
+def : InstRW<[C1UWrite_9c_2L_3V], (instregex "LD3i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_9c_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;
+
+// ASIMD load, 3 element, all lanes, D-form, B/H/S
+// ASIMD load, 3 element, all lanes, D-form, D
+def : InstRW<[C1UWrite_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 3 element, all lanes, Q-form, B/H/S
+// ASIMD load, 3 element, all lanes, Q-form, D
+def : InstRW<[C1UWrite_8c_2L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_2L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 4 element, multiple, D-form, B/H/S
+def : InstRW<[C1UWrite_8c_2L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_2L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
+
+// ASIMD load, 4 element, multiple, Q-form, B/H/S
+// ASIMD load, 4 element, multiple, Q-form, D
+def : InstRW<[C1UWrite_9c_4L_8V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_9c_4L_8V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD load, 4 element, one lane, B/H
+// ASIMD load, 4 element, one lane, S
+// ASIMD load, 4 element, one lane, D
+def : InstRW<[C1UWrite_8c_2L_4V], (instregex "LD4i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_2L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;
+
+// ASIMD load, 4 element, all lanes, D-form, B/H/S
+// ASIMD load, 4 element, all lanes, D-form, D
+def : InstRW<[C1UWrite_8c_2L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_2L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD load, 4 element, all lanes, Q-form, B/H/S
+// ASIMD load, 4 element, all lanes, Q-form, D
+def : InstRW<[C1UWrite_8c_2L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_8c_2L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD store instructions
+// -----------------------------------------------------------------------------
+
+// ASIMD store, 1 element, multiple, 1 reg, D-form
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_1SA_1V01], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD store, 1 element, multiple, 1 reg, Q-form
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_1SA_1V01], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD store, 1 element, multiple, 2 reg, D-form
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_1SA_1V01], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD store, 1 element, multiple, 2 reg, Q-form
+def : InstRW<[C1UWrite_2c_2SA_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_2SA_2V01], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD store, 1 element, multiple, 3 reg, D-form
+def : InstRW<[C1UWrite_2c_2SA_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_2SA_2V01], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD store, 1 element, multiple, 3 reg, Q-form
+def : InstRW<[C1UWrite_2c_3SA_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_3SA_3V01], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD store, 1 element, multiple, 4 reg, D-form
+def : InstRW<[C1UWrite_2c_2SA_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_2SA_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
+
+// ASIMD store, 1 element, multiple, 4 reg, Q-form
+def : InstRW<[C1UWrite_2c_4SA_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_2c_4SA_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD store, 1 element, one lane, B/H/S
+// ASIMD store, 1 element, one lane, D
+def : InstRW<[C1UWrite_4c_1SA_1V01_1V], (instregex "ST1i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_4c_1SA_1V01_1V], (instregex "ST1i(8|16|32|64)_POST$")>;
+
+// ASIMD store, 2 element, multiple, D-form, B/H/S
+def : InstRW<[C1UWrite_4c_2SA_2V01_2V], (instregex "ST2Twov(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, C1UWrite_4c_2SA_2V01_2V], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
+
+// ASIMD store, 2 element, multiple, Q-form, B/H/S
+// ASIMD store, 2 element, multiple, Q-form, D
+def : InstRW<[C1UWrite_4c_2SA_2V01_2V], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_4c_2SA_2V01_2V], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD store, 2 element, one lane, B/H/S
+// ASIMD store, 2 element, one lane, D
+def : InstRW<[C1UWrite_4c_1SA_1V01_1V], (instregex "ST2i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_4c_1SA_1V01_1V], (instregex "ST2i(8|16|32|64)_POST$")>;
+
+// ASIMD store, 3 element, multiple, D-form, B/H/S
+def : InstRW<[C1UWrite_4c_2SA_2V01_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, C1UWrite_4c_2SA_2V01_2V], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
+
+// ASIMD store, 3 element, multiple, Q-form, B/H/S
+// ASIMD store, 3 element, multiple, Q-form, D
+def : InstRW<[C1UWrite_5c_4SA_4V01_4V], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_5c_4SA_4V01_4V], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
+
+// ASIMD store, 3 element, one lane, B/H
+// ASIMD store, 3 element, one lane, S
+// ASIMD store, 3 element, one lane, D
+def : InstRW<[C1UWrite_4c_2SA_2V01_2V], (instregex "ST3i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_4c_2SA_2V01_2V], (instregex "ST3i(8|16|32|64)_POST$")>;
+
+// ASIMD store, 4 element, multiple, D-form, B/H/S
+def : InstRW<[C1UWrite_6c_6SA_6V01_6V], (instregex "ST4Fourv(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_6SA_6V01_6V], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
+
+// ASIMD store, 4 element, multiple, Q-form, B/H/S
+def : InstRW<[C1UWrite_7c_12SA_12V01_12V], (instregex "ST4Fourv(16b|8h|4s)$")>;
+def : InstRW<[WriteAdr, C1UWrite_7c_12SA_12V01_12V], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
+
+// ASIMD store, 4 element, multiple, Q-form, D
+def : InstRW<[C1UWrite_6c_8SA_8V01_8V], (instregex "ST4Fourv(2d)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_8SA_8V01_8V], (instregex "ST4Fourv(2d)_POST$")>;
+
+// ASIMD store, 4 element, one lane, B/H/S
+def : InstRW<[C1UWrite_6c_1SA_1V01_1V], (instregex "ST4i(8|16|32)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_1SA_1V01_1V], (instregex "ST4i(8|16|32)_POST$")>;
+
+// ASIMD store, 4 element, one lane, D
+def : InstRW<[C1UWrite_6c_1SA_1V01_1V], (instregex "ST4i(64)$")>;
+def : InstRW<[WriteAdr, C1UWrite_6c_1SA_1V01_1V], (instregex "ST4i(64)_POST$")>;
+
+// Cryptography extensions
+// -----------------------------------------------------------------------------
+
+// Crypto AES ops
+def : InstRW<[C1UWrite_2c_1V0134], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;
+
+// Crypto polynomial (64x64) multiply long
+def : InstRW<[C1UWrite_2c_1V0134], (instrs PMULLv1i64, PMULLv2i64)>;
+
+// Crypto SHA1 hash acceleration op
+// Crypto SHA1 hash acceleration ops
+// Crypto SHA1 schedule acceleration ops
+def : InstRW<[C1UWrite_2c_1V0], (instregex "^SHA1(H|SU0|SU1|C|M|P)")>;
+
+// Crypto SHA256 hash acceleration ops
+def : InstRW<[C1UWrite_4c_1V0], (instregex "^SHA256H2?")>;
+
+// Crypto SHA256 schedule acceleration ops
+def : InstRW<[C1UWrite_2c_1V0], (instregex "^SHA256SU[01]")>;
+
+// Crypto SHA512 hash acceleration ops
+def : InstRW<[C1UWrite_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;
+
+// Crypto SHA3 ops
+def : InstRW<[C1UWrite_2c_1V], (instrs BCAX, EOR3, RAX1, XAR)>;
+
+// Crypto SM3 ops
+def : InstRW<[C1UWrite_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",
+ "^SM3TT[12][AB]$")>;
+
+// Crypto SM4 ops
+def : InstRW<[C1UWrite_4c_1V0], (instrs SM4E, SM4ENCKEY)>;
+
+// CRC
+// -----------------------------------------------------------------------------
+
+def : InstRW<[C1UWrite_2c_1M], (instregex "^CRC32")>;
+
+// SVE Predicate instructions
+// -----------------------------------------------------------------------------
+
+// Loop control, based on predicate
+def : InstRW<[C1UWrite_1c_1M], (instrs BRKA_PPmP, BRKA_PPzP,
+ BRKB_PPmP, BRKB_PPzP)>;
+
+// Loop control, based on predicate and flag setting
+def : InstRW<[C1UWrite_1c_1M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;
+
+// Loop control, propagating
+def : InstRW<[C1UWr_Pred, C1URd_Pred, C1URd_Pred, C1URd_Pred], (instrs BRKN_PPzP, BRKPA_PPzPP,
+ BRKPB_PPzPP)>;
+
+// Loop control, propagating and flag setting
+def : InstRW<[C1UWr_Pred, C1URd_Pred, C1URd_Pred, C1URd_Pred], (instrs BRKNS_PPzP, BRKPAS_PPzPP,
+ BRKPBS_PPzPP)>;
+
+// Loop control, based on GPR
+def : InstRW<[C1UWrite_1c_1M],
+ (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]")>;
+def : InstRW<[C1UWrite_2c_1M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>;
+
+// Loop terminate
+def : InstRW<[C1UWrite_1c_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;
+
+// // Predicate counting scalar
+def : InstRW<[C1UWrite_1c_1I], (instregex "^(CNT|DEC|INC)[BHWD]_XPiI")>;
+def : InstRW<[C1UWrite_1c_1I], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;
+def : InstRW<[C1UWrite_2c_1M],
+ (instregex "^(SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI",
+ "^SQ(DEC|INC)[BHWD]_XPiWdI",
+ "^UQ(DEC|INC)[BHWD]_WPiI")>;
+
+
+// Predicate counting scalar, active predicate
+def : InstRW<[C1UWrite_2c_1M],
+ (instregex "^CNTP_XPP_[BHSD]",
+ "^(DEC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]",
+ "^(UQDEC|UQINC)P_WP_[BHSD]",
+ "^(SQDEC|SQINC)P_XPWd_[BHSD]")>;
+
+// Predicate counting vector, active predicate
+def : InstRW<[C1UWrite_7c_1M_1M0_1V],
+ (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>;
+def : InstRW<[C1UWrite_7c_1M_1M0_1V], (instregex "^INCP_XP_[BHSD]")>;
+
+// Predicate logical
+def : InstRW<[C1UWr_Pred, C1URd_Pred, C1URd_Pred, C1URd_Pred],
+ (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;
+
+// Predicate logical, flag setting
+def : InstRW<[C1UWr_Pred, C1URd_Pred, C1URd_Pred, C1URd_Pred],
+ (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;
+
+// Predicate reverse
+def : InstRW<[C1UWrite_2c_1M], (instregex "^REV_PP_[BHSD]")>;
+
+// Predicate select
+def : InstRW<[C1UWr_Pred, C1URd_Pred, C1URd_Pred, C1URd_Pred], (instrs SEL_PPPP)>;
+
+// Predicate set
+def : InstRW<[C1UWrite_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
+
+// Predicate set/initialize, set flags
+def : InstRW<[C1UWrite_2c_1M], (instregex "^PTRUES_[BHSD]")>;
+
+// Predicate find first/next
+def : InstRW<[C1UWrite_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
+
+// Predicate test
+def : InstRW<[C1UWrite_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
+
+// Predicate transpose
+def : InstRW<[C1UWrite_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;
+
+// Predicate unpack and widen
+def : InstRW<[C1UWrite_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;
+
+// Predicate zip/unzip
+def : InstRW<[C1UWrite_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]")>;
+
+
+// SVE integer instructions
+// -----------------------------------------------------------------------------
+
+// Arithmetic, absolute diff
+def : InstRW<[C1UWrite_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",
+ "^[SU]ABD_ZPZZ_[BHSD]")>;
+
+// Arithmetic, absolute diff accum
+def : InstRW<[C1UWr_ZA, C1URd_ZA, C1URd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]")>;
+
+// Arithmetic, absolute diff accum long
+def : InstRW<[C1UWr_ZA, C1URd_ZA, C1URd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]")>;
+
+// Arithmetic, absolute diff long
+def : InstRW<[C1UWrite_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>;
+
+// Arithmetic, basic
+def : InstRW<[C1UWrite_2c_1V],
+ (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",
+ "^(ADD|SUB)_ZZZ_[BHSD]",
+ "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",
+ "^(ADD|SUB|SUBR)_ZI_[BHSD]",
+ "^ADR_[SU]XTW_ZZZ_D_[0123]",
+ "^ADR_LSL_ZZZ_[SD]_[0123]",
+ "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
+ "^SADDLBT_ZZZ_[HSD]",
+ "^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
+ "^SSUBL(BT|TB)_ZZZ_[HSD]")>;
+
+// Arithmetic, complex
+def : InstRW<[C1UWrite_2c_1V],
+ (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",
+ "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",
+ "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",
+ "^[SU]Q(ADD|SUB)_ZI_[BHSD]",
+ "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]",
+ "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;
+
+// Arithmetic, large integer
+def : InstRW<[C1UWrite_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>;
+
+// Arithmetic, pairwise add
+def : InstRW<[C1UWrite_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]")>;
+
+// Arithmetic, pairwise add and accum long
+def : InstRW<[C1UWr_ZPA, ReadDefault, C1URd_ZPA, C1URd_ZPA],
+ (instregex "^[SU]ADALP_ZPmZ_[HSD]")>;
+
+// Arithmetic, shift
+def : InstRW<[C1UWrite_2c_1V],
+ (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
+ "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
+ "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
+ "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
+ "^(ASR|LSL|LSR)_ZZI_[BHSD]",
+ "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
+ "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;
+
+// Arithmetic, shift and accumulate
+def : InstRW<[C1UWr_ZSA, C1URd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]")>;
+
+// Arithmetic, shift by immediate
+def : InstRW<[C1UWrite_2c_1V], (instregex "^SHRN[BT]_ZZI_[BHS]",
+ "^[SU]SHLL[BT]_ZZI_[HSD]")>;
+
+// Arithmetic, shift by immediate and insert
+def : InstRW<[C1UWrite_2c_1V], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>;
+
+// Arithmetic, shift complex
+def : InstRW<[C1UWrite_4c_1V],
+ (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",
+ "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",
+ "^[SU]QR?SHL_ZPZZ_[BHSD]",
+ "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]",
+ "^SQSHRU?N[BT]_ZZI_[BHS]",
+ "^UQR?SHRN[BT]_ZZI_[BHS]")>;
+
+// Arithmetic, shift right for divide
+def : InstRW<[C1UWrite_4c_1V], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;
+
+// Arithmetic, shift rounding
+def : InstRW<[C1UWrite_4c_1V], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",
+ "^[SU]RSHL_ZPZZ_[BHSD]",
+ "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;
+
+// Bit manipulation
+def : InstRW<[C1UWrite_6c_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;
+
+// Bitwise select
+def : InstRW<[C1UWrite_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;
+
+// Count/reverse bits
+def : InstRW<[C1UWrite_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;
+
+// Broadcast logical bitmask immediate to vector
+def : InstRW<[C1UWrite_2c_1V], (instrs DUPM_ZI)>;
+
+// Compare and set flags
+def : InstRW<[C1UWrite_2c_1V0],
+ (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]",
+ "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>;
+
+// Complex add
+def : InstRW<[C1UWrite_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]")>;
+
+// Complex dot product 8-bit element
+def : InstRW<[C1UWr_ZDOTB, C1URd_ZDOTB, C1URd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;
+
+// Complex dot product 16-bit element
+def : InstRW<[C1UWr_ZDOTH, C1URd_ZDOTH, C1URd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;
+
+// Complex multiply-add B, H, S, D element size
+def : InstRW<[C1UWr_ZCMABHS, C1URd_ZCMABHS, C1URd_ZCMABHS], (instregex "^CMLA_ZZZ_[BHSD]",
+ "^CMLA_ZZZI_[HS]")>;
+
+// Conditional extract operations, scalar form
+def : InstRW<[C1UWrite_8c_1M0_1V1_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;
+
+// Conditional extract operations, SIMD&FP scalar and vector forms
+def : InstRW<[C1UWrite_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",
+ "^COMPACT_ZPZ_[SD]",
+ "^SPLICE_ZPZZ?_[BHSD]")>;
+
+// Convert to floating point, 64b to float or convert to double
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",
+ "^[SU]CVTF_ZPmZ_StoD")>;
+
+// Convert to floating point, 32b to single or half
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;
+
+// Convert to floating point, 16b to half
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;
+
+// Copy, scalar
+def : InstRW<[C1UWrite_3c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]")>;
+
+// Copy, scalar SIMD&FP or imm
+def : InstRW<[C1UWrite_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]",
+ "^CPY_ZPzI_[BHSD]")>;
+
+// Divides, 32 bit
+def : InstRW<[C1UWrite_12c_7V0], (instregex "^[SU]DIVR?_ZPmZ_S",
+ "^[SU]DIV_ZPZZ_S")>;
+
+// Divides, 64 bit
+def : InstRW<[C1UWrite_20c_7V0], (instregex "^[SU]DIVR?_ZPmZ_D",
+ "^[SU]DIV_ZPZZ_D")>;
+
+// Dot product, 8 bit
+def : InstRW<[C1UWr_ZDOTB, C1URd_ZDOTB, C1URd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_BtoS")>;
+
+// Dot product, 8 bit, using signed and unsigned integers
+def : InstRW<[C1UWr_ZDOTB, C1URd_ZDOTB, C1URd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;
+
+// Dot product, 16 bit
+def : InstRW<[C1UWr_ZDOTH, C1URd_ZDOTH, C1URd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_HtoD")>;
+
+// Duplicate, immediate and indexed form
+def : InstRW<[C1UWrite_2c_1V], (instregex "^DUP_ZI_[BHSD]",
+ "^DUP_ZZI_[BHSDQ]")>;
+
+// Duplicate, scalar form
+def : InstRW<[C1UWrite_3c_1M0], (instregex "^DUP_ZR_[BHSD]")>;
+
+// Extend, sign or zero
+def : InstRW<[C1UWrite_2c_1V], (instregex "^[SU]XTB_ZPmZ_[HSD]",
+ "^[SU]XTH_ZPmZ_[SD]",
+ "^[SU]XTW_ZPmZ_[D]")>;
+
+// Extract
+def : InstRW<[C1UWrite_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;
+
+// Extract narrow saturating
+def : InstRW<[C1UWrite_4c_1V], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",
+ "^SQXTUN[BT]_ZZ_[BHS]")>;
+
+// Extract operation, SIMD and FP scalar form
+def : InstRW<[C1UWrite_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]")>;
+
+// Extract operation, scalar
+def : InstRW<[C1UWrite_5c_1V1_1V01], (instregex "^LAST[AB]_RPZ_[BHSD]")>;
+
+// Histogram operations
+def : InstRW<[C1UWrite_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]",
+ "^HISTSEG_ZZZ")>;
+
+// Horizontal operations,immediate operands only
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^INDEX_(II)_[BHSD]")>;
+
+// Horizontal operations, D form, scalar, immediate operands/ scalar operands
+// only / immediate, scalar operands
+def : InstRW<[C1UWrite_7c_1M0_1V0134], (instregex "^INDEX_(IR|RI|RR)_[BHSD]")>;
+
+// insert operation, SIMD and FP scalar form
+def : InstRW<[C1UWrite_2c_1V], (instregex "^INSR_ZV_[BHSD]")>;
+
+// insert operation, scalar
+def : InstRW<[C1UWrite_5c_1V_1M0], (instregex "^INSR_ZR_[BHSD]")>;
+
+// Logical
+def : InstRW<[C1UWrite_2c_1V],
+ (instregex "^(AND|EOR|ORR)_ZI",
+ "^(AND|BIC|EOR|ORR|EON|NAND|NOR)_ZZZ",
+ "^EOR(BT|TB)_ZZZ_[BHSD]",
+ "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",
+ "^NOT_ZPmZ_[BHSD]")>;
+
+// Max/min, basic and pairwise
+def : InstRW<[C1UWrite_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",
+ "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",
+ "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;
+
+// Matching operations
+def : InstRW<[C1UWrite_2c_1V0], (instregex "^N?MATCH_PPzZZ_[BH]")>;
+
+// Matrix multiply-accumulate
+def : InstRW<[C1UWr_ZMMA, C1URd_ZMMA, C1URd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
+
+// Move prefix
+def : InstRW<[C1UWrite_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",
+ "^MOVPRFX_ZZ")>;
+
+// Multiply
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHSD]",
+ "^MUL_ZPZZ_[BHSD]",
+ "^[SU]MULH_(ZPmZ|ZZZ)_[BHSD]",
+ "^[SU]MULH_ZPZZ_[BHSD]")>;
+
+// Multiply long
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",
+ "^[SU]MULL[BT]_ZZZ_[HSD]")>;
+
+
+// Multiply accumulate, B, H, S element size
+def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+ (instregex "^ML[AS]_ZZZI_[HS]", "^ML[AS]_ZPZZZ_[BHS]")>;
+def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+ (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;
+
+// Multiply accumulate, D element size
+def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+ (instregex "^ML[AS]_ZZZI_D", "^ML[AS]_ZPZZZ_D")>;
+def : InstRW<[C1UWr_ZMA, ReadDefault, C1URd_ZMA, C1URd_ZMA],
+ (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;
+
+
+
+// Multiply accumulate long
+def : InstRW<[C1UWr_ZMA, C1URd_ZMA, C1URd_ZMA], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]",
+ "^[SU]ML[AS]L[BT]_ZZZI_[SD]")>;
+
+// Multiply accumulate saturating doubling long regular
+def : InstRW<[C1UWr_ZMASQL, C1URd_ZMASQL, C1URd_ZMASQL],
+ (instregex "^SQDML[AS]L(B|T|BT)_ZZZ_[HSD]",
+ "^SQDML[AS]L[BT]_ZZZI_[SD]")>;
+
+// Multiply saturating doubling high
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^SQDMULH_ZZZ_[BHSD]",
+ "^SQDMULH_ZZZI_[HSD]")>;
+
+// Multiply saturating doubling long
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",
+ "^SQDMULL[BT]_ZZZI_[SD]")>;
+
+// Multiply saturating rounding doubling regular/complex accumulate
+def : InstRW<[C1UWr_ZMASQL, C1URd_ZMASQL, C1URd_ZMASQL], (instregex "^SQRDML[AS]H_ZZZ_[BHSD]",
+ "^SQRDCMLAH_ZZZ_[BHSD]",
+ "^SQRDML[AS]H_ZZZI_[HSD]",
+ "^SQRDCMLAH_ZZZI_[HSD]")>;
+
+
+// Multiply saturating rounding doubling regular/complex, B, H, S element size
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^SQRDMULH_ZZZ_[BHS]",
+ "^SQRDMULH_ZZZI_[HS]",
+ "^SQRDMULH_ZZZI?_D")>;
+
+
+// Multiply/multiply long, (8x8) polynomial
+def : InstRW<[C1UWrite_2c_1V0134], (instregex "^PMUL_ZZZ_B",
+ "^PMULL[BT]_ZZZ_[HDQ]")>;
+
+// Predicate counting vector
+def : InstRW<[C1UWrite_2c_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;
+
+// Reciprocal estimate
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;
+
+// Reduction, arithmetic, B form
+def : InstRW<[C1UWrite_8c_1V_3V0134], (instregex "^[SU]ADDV_VPZ_B")>;
+def : InstRW<[C1UWrite_6c_1V_2V0134], (instregex "^[SU](MAX|MIN)V_VPZ_B")>;
+
+// // Reduction, arithmetic, H form
+def : InstRW<[C1UWrite_6c_1V_2V0134], (instregex "^[SU]ADDV_VPZ_H")>;
+def : InstRW<[C1UWrite_6c_2V_1V0134], (instregex "^[SU](MAX|MIN)V_VPZ_H")>;
+
+// Reduction, arithmetic, S form
+def : InstRW<[C1UWrite_6c_2V_1V0134], (instregex "^[SU]ADDV_VPZ_S")>;
+def : InstRW<[C1UWrite_4c_1V_1V0134], (instregex "^[SU](MAX|MIN)V_VPZ_S")>;
+
+// Reduction, arithmetic, D form
+def : InstRW<[C1UWrite_4c_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;
+
+// Reduction, logical
+def : InstRW<[C1UWrite_4c_1V_1V0134], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;
+
+// Reverse, vector
+def : InstRW<[C1UWrite_2c_1V], (instregex "^REV_ZZ_[BHSD]",
+ "^REVB_ZPmZ_[HSD]",
+ "^REVH_ZPmZ_[SD]",
+ "^REVW_ZPmZ_D")>;
+
+// Select, vector form
+def : InstRW<[C1UWrite_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]")>;
+
+// Table lookup
+def : InstRW<[C1UWrite_2c_1V], (instregex "^TBL_ZZZZ?_[BHSD]")>;
+
+// Table lookup extension
+def : InstRW<[C1UWrite_2c_1V], (instregex "^TBX_ZZZ_[BHSD]")>;
+
+// Transpose, vector form
+def : InstRW<[C1UWrite_2c_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>;
+
+// Unpack and extend
+def : InstRW<[C1UWrite_2c_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>;
+
+// Zip/unzip
+def : InstRW<[C1UWrite_2c_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>;
+
+// SVE floating-point instructions
+// -----------------------------------------------------------------------------
+
+// Floating point absolute value/difference
+def : InstRW<[C1UWrite_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",
+ "^FABD_ZPZZ_[HSD]",
+ "^FABS_ZPmZ_[HSD]")>;
+
+// Floating point arithmetic
+def : InstRW<[C1UWrite_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",
+ "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",
+ "^FADDP_ZPmZZ_[HSD]",
+ "^FNEG_ZPmZ_[HSD]",
+ "^FSUBR_ZPm[IZ]_[HSD]",
+ "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;
+
+// Floating point associative add, F16
+def : InstRW<[C1UWrite_10c_10V0], (instrs FADDA_VPZ_H)>;
+
+// Floating point associative add, F32
+def : InstRW<[C1UWrite_6c_6V0], (instrs FADDA_VPZ_S)>;
+
+// Floating point associative add, F64
+def : InstRW<[C1UWrite_4c_2V], (instrs FADDA_VPZ_D)>;
+
+// Floating point compare
+def : InstRW<[C1UWrite_2c_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]",
+ "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]",
+ "^FCM(LE|LT)_PPzZ0_[HSD]",
+ "^FCMUO_PPzZZ_[HSD]")>;
+
+// Floating point complex add
+def : InstRW<[C1UWrite_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]")>;
+
+// Floating point complex multiply add
+def : InstRW<[C1UWr_ZFCMA, ReadDefault, C1URd_ZFCMA, C1URd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]")>;
+def : InstRW<[C1UWr_ZFCMA, C1URd_ZFCMA, C1URd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;
+
+// Floating point convert, long or narrow (F16 to F32 or F32 to F16)
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",
+ "^FCVTLT_ZPmZ_HtoS",
+ "^FCVTNT_ZPmZ_StoH")>;
+
+// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32
+// or F64 to F16)
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",
+ "^FCVTLT_ZPmZ_StoD",
+ "^FCVTNT_ZPmZ_DtoS")>;
+
+// Floating point convert, round to odd
+def : InstRW<[C1UWrite_3c_1V0134], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;
+
+// Floating point base2 log, F16
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;
+
+// Floating point base2 log, F32
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;
+
+// Floating point base2 log, F64
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;
+
+// Floating point convert to integer, F16
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;
+
+// Floating point convert to integer, F32
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;
+
+// Floating point convert to integer, F64
+def : InstRW<[C1UWrite_3c_1V0134],
+ (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;
+
+// Floating point copy
+def : InstRW<[C1UWrite_2c_1V], (instregex "^FCPY_ZPmI_[HSD]",
+ "^FDUP_ZI_[HSD]")>;
+
+// Floating point divide, F16
+def : InstRW<[C1UWrite_12c_1V0_8rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;
+
+// Floating point divide, F32
+def : InstRW<[C1UWrite_11c_1V0_4rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;
+
+// Floating point divide, F64
+def : InstRW<[C1UWrite_13c_1V0_2rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;
+
+// Floating point min/max pairwise
+def : InstRW<[C1UWrite_2c_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;
+
+// Floating point min/max
+def : InstRW<[C1UWrite_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",
+ "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;
+
+// Floating point multiply
+def : InstRW<[C1UWrite_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",
+ "^FMULX_ZPZZ_[HSD]",
+ "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",
+ "^FMUL_ZPZ[IZ]_[HSD]")>;
+
+// Floating point multiply accumulate
+def : InstRW<[C1UWr_ZFMA, ReadDefault, C1URd_ZFMA, C1URd_ZFMA],
+ (instregex "^FN?ML[AS]_ZPmZZ_[HSD]",
+ "^FN?(MAD|MSB)_ZPmZZ_[HSD]",
+ "^FN?ML[AS]_ZPZZZ_[HSD]")>;
+
+def : InstRW<[C1UWr_ZFMA, C1URd_ZFMA, C1URd_ZFMA],
+ (instregex "^FML[AS]_ZZZI_[HSD]")>;
+
+// Floating point multiply add/sub accumulate long
+def : InstRW<[C1UWr_ZFMAL, C1URd_ZFMAL, C1URd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH")>;
+
+// Floating point reciprocal estimate, F16
+def : InstRW<[C1UWrite_6c_1V0134], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;
+
+// Floating point reciprocal estimate, F32
+def : InstRW<[C1UWrite_4c_1V0134], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;
+
+// Floating point reciprocal estimate, F64
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;
+
+// Floating point reciprocal step
+def : InstRW<[C1UWrite_4c_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;
+
+// Floating point reduction, F16
+def : InstRW<[C1UWrite_8c_4V],
+ (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H")>;
+
+// Floating point reduction, F32
+def : InstRW<[C1UWrite_6c_3V],
+ (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S")>;
+
+// Floating point reduction, F64
+def : InstRW<[C1UWrite_4c_2V],
+ (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D")>;
+
+// Floating point round to integral, F16
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;
+
+// Floating point round to integral, F32
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;
+
+// Floating point round to integral, F64
+def : InstRW<[C1UWrite_3c_1V0134], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;
+
+// Floating point square root, F16
+def : InstRW<[C1UWrite_12c_1V1_8rc], (instregex "^FSQRT_ZPmZ_H")>;
+
+// Floating point square root, F32
+def : InstRW<[C1UWrite_11c_1V1_4rc], (instregex "^FSQRT_ZPmZ_S")>;
+
+// Floating point square root, F64
+def : InstRW<[C1UWrite_13c_1V1_2rc], (instregex "^FSQRT_ZPmZ_D")>;
+
+// Floating point trigonometric exponentiation
+def : InstRW<[C1UWrite_3c_1V1], (instregex "^FEXPA_ZZ_[HSD]")>;
+
+// Floating point trigonometric multiply add
+def : InstRW<[C1UWrite_4c_1V], (instregex "^FTMAD_ZZI_[HSD]")>;
+
+// Floating point trigonometric, miscellaneous
+def : InstRW<[C1UWrite_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]")>;
+
+
+// SVE BFloat16 (BF16) instructions
+// -----------------------------------------------------------------------------
+
+// Convert, F32 to BF16
+def : InstRW<[C1UWrite_3c_1V0134], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;
+
+// Dot product
+def : InstRW<[C1UWr_ZBFDOT, C1URd_ZBFDOT, C1URd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;
+
+// Matrix multiply accumulate
+def : InstRW<[C1UWr_ZBFMMA, C1URd_ZBFMMA, C1URd_ZBFMMA], (instrs BFMMLA_ZZZ_HtoS)>;
+
+// Multiply accumulate long
+def : InstRW<[C1UWr_ZBFMAL, C1URd_ZBFMAL, C1URd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZI?")>;
+
+// SVE Load instructions
+// -----------------------------------------------------------------------------
+
+// Load vector
+def : InstRW<[C1UWrite_6c_1L], (instrs LDR_ZXI)>;
+
+// Load predicate
+def : InstRW<[C1UWrite_6c_1L_1M], (instrs LDR_PXI)>;
+
+// Contiguous load, scalar + imm
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LD1[BHWD]_IMM$",
+ "^LD1S?B_[HSD]_IMM$",
+ "^LD1S?H_[SD]_IMM$",
+ "^LD1S?W_D_IMM$" )>;
+// Contiguous load, scalar + scalar
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LD1[BHWD]$",
+ "^LD1S?B_[HSD]$",
+ "^LD1S?H_[SD]$",
+ "^LD1S?W_D$" )>;
+
+// Contiguous load broadcast, scalar + imm
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LD1R[BHWD]_IMM$",
+ "^LD1RS?B_[HSD]_IMM$",
+ "^LD1RS?H_[SD]_IMM$",
+ "^LD1RW_D_IMM$",
+ "^LD1RSW_IMM$",
+ "^LD1RQ_[BHWD]_IMM$")>;
+
+// Contiguous load broadcast, scalar + scalar
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;
+
+// Non temporal load, scalar + imm
+// Non temporal load, scalar + scalar
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>;
+
+// Non temporal gather load, vector + scalar 32-bit element size
+def : InstRW<[C1UWrite_9c_1V01_1L], (instregex "^LDNT1[BHW]_ZZR_S$",
+ "^LDNT1S[BH]_ZZR_S$")>;
+
+// Non temporal gather load, vector + scalar 64-bit element size
+def : InstRW<[C1UWrite_9c_1V01_1L], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;
+def : InstRW<[C1UWrite_6c_1L], (instrs LDNT1D_ZZR_D)>;
+
+// Contiguous first faulting load, scalar + scalar
+def : InstRW<[C1UWrite_9c_1V01_1L], (instregex "^LDFF1[BHWD]$",
+ "^LDFF1S?B_[HSD]$",
+ "^LDFF1S?H_[SD]$",
+ "^LDFF1S?W_D$")>;
+
+// Contiguous non faulting load, scalar + imm
+def : InstRW<[C1UWrite_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",
+ "^LDNF1S?B_[HSD]_IMM$",
+ "^LDNF1S?H_[SD]_IMM$",
+ "^LDNF1S?W_D_IMM$")>;
+
+// Contiguous Load two structures to two vectors, scalar + imm
+def : InstRW<[C1UWrite_8c_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;
+
+// Contiguous Load two structures to two vectors, scalar + scalar
+def : InstRW<[C1UWrite_9c_2L_2V_1I], (instregex "^LD2[BHWD]$")>;
+
+// Contiguous Load three structures to three vectors, scalar + imm
+def : InstRW<[C1UWrite_8c_3L_3V], (instregex "^LD3[BHWD]_IMM$")>;
+
+// Contiguous Load three structures to three vectors, scalar + scalar
+def : InstRW<[C1UWrite_9c_3L_3V_1I], (instregex "^LD3[BHWD]$")>;
+
+// Contiguous Load four structures to four vectors, scalar + imm
+def : InstRW<[C1UWrite_10c_4L_8V], (instregex "^LD4[BHWD]_IMM$")>;
+
+// Contiguous Load four structures to four vectors, scalar + scalar
+def : InstRW<[C1UWrite_11c_4L_8V_1I], (instregex "^LD4[BHWD]$")>;
+
+// Gather load, vector + imm, 32-bit element size
+def : InstRW<[C1UWrite_9c_1V01_1L], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
+ "^GLD(FF)?1W_IMM$")>;
+
+// Gather load, vector + imm, 64-bit element size
+def : InstRW<[C1UWrite_9c_1V01_1L], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",
+ "^GLD(FF)?1D_IMM$")>;
+
+// Gather load, 32-bit scaled offset
+def : InstRW<[C1UWrite_9c_1V01_1L],
+ (instregex "^GLD(FF)?1S?H_S_[SU]XTW_SCALED$",
+ "^GLD(FF)?1W_[SU]XTW_SCALED")>;
+// Gather load, 64-bit scaled offset
+// NOTE: These instructions are not specified in the SOG.
+def : InstRW<[C1UWrite_9c_1V01_1L],
+ (instregex "^GLD(FF)?1S?[HW]_D_([SU]XTW_)?SCALED$",
+ "^GLD(FF)?1D_([SU]XTW_)?SCALED$")>;
+
+
+// Gather load, 32-bit unpacked unscaled offset
+def : InstRW<[C1UWrite_9c_1V01_1L], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
+ "^GLD(FF)?1W_[SU]XTW$")>;
+
+// Gather load, 64-bit unpacked unscaled offset
+// NOTE: These instructions are not specified in the SOG.
+def : InstRW<[C1UWrite_9c_1V01_1L],
+ (instregex "^GLD(FF)?1S?[BHW]_D(_[SU]XTW)?$",
+ "^GLD(FF)?1D(_[SU]XTW)?$")>;
+// SVE Store instructions
+// -----------------------------------------------------------------------------
+
+// Store from predicate reg
+def : InstRW<[C1UWrite_1c_1SA], (instrs STR_PXI)>;
+
+// Store from vector reg
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instrs STR_ZXI)>;
+
+// Contiguous store, scalar + imm
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "^ST1[BHWD]_IMM$",
+ "^ST1B_[HSD]_IMM$",
+ "^ST1H_[SD]_IMM$",
+ "^ST1W_D_IMM$")>;
+
+// Contiguous store, scalar + scalar
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "^ST1H(_[SD])?$",
+ "^ST1[BWD]$",
+ "^ST1B_[HSD]$",
+ "^ST1W_D$")>;
+
+// Contiguous store two structures from two vectors, scalar + imm
+def : InstRW<[C1UWrite_4c_2SA_2V01], (instregex "^ST2[BHWD]_IMM$")>;
+
+// Contiguous store two structures from two vectors, scalar + scalar
+def : InstRW<[C1UWrite_4c_2SA_2V01_1I], (instregex "^ST2[BHWD]$")>;
+
+// Contiguous store three structures from three vectors, scalar + imm
+def : InstRW<[C1UWrite_5c_3SA_3V01], (instregex "^ST3[BHWD]_IMM$")>;
+
+// Contiguous store three structures from three vectors, scalar + scalar
+def : InstRW<[C1UWrite_5c_3SA_3V01_1I], (instregex "^ST3[BHWD]$")>;
+
+// Contiguous store four structures from four vectors, scalar + imm
+def : InstRW<[C1UWrite_7c_4SA_4V01], (instregex "^ST4[BHWD]_IMM$")>;
+
+// Contiguous store four structures from four vectors, scalar + scalar
+def : InstRW<[C1UWrite_7c_4SA_4V01_1I], (instregex "^ST4[BHWD]$")>;
+
+// Non temporal store, scalar + imm
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "^STNT1[BHWD]_ZRI$")>;
+
+// Non temporal store, scalar + scalar
+def : InstRW<[C1UWrite_2c_1SA_1V01], (instregex "^STNT1[BHWD]_ZRR$")>;
+
+// Scatter non temporal store, vector + scalar 32-bit element size
+def : InstRW<[C1UWrite_5or7c_3SA_6V01], (instregex "^STNT1[BHW]_ZZR_S")>;
+
+// Scatter non temporal store, vector + scalar 64-bit element size
+def : InstRW<[C1UWrite_4or6c_3SA_3V01], (instregex "^STNT1[BHWD]_ZZR_D")>;
+
+// Scatter store vector + imm 32-bit element size
+def : InstRW<[C1UWrite_5or7c_5SA_5V01], (instregex "^SST1[BHW]_S_IMM$",
+ "^SST1W_IMM$")>;
+
+// Scatter store vector + imm 64-bit element size
+def : InstRW<[C1UWrite_4or6c_3SA_3V01], (instregex "^SST1[BHW]_D_IMM$",
+ "^SST1D_IMM$")>;
+
+// Scatter store, 32-bit scaled offset
+def : InstRW<[C1UWrite_2or4c_3SA_6V01],
+ (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;
+
+// Scatter store, 32-bit unpacked unscaled offset
+def : InstRW<[C1UWrite_2or4c_1SA_1V01], (instregex "^SST1[BHW]_D_[SU]XTW$",
+ "^SST1D_[SU]XTW$")>;
+
+// Scatter store, 32-bit unpacked scaled offset
+def : InstRW<[C1UWrite_2or4c_1SA_1V01], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",
+ "^SST1D_[SU]XTW_SCALED$")>;
+
+// Scatter store, 32-bit unscaled offset
+def : InstRW<[C1UWrite_2or4c_1SA_1V01], (instregex "^SST1[BH]_S_[SU]XTW$",
+ "^SST1W_[SU]XTW$")>;
+
+// Scatter store, 64-bit scaled offset
+def : InstRW<[C1UWrite_2or4c_1SA_1V01], (instregex "^SST1[HW]_D_SCALED$",
+ "^SST1D_SCALED$")>;
+
+// Scatter store, 64-bit unscaled offset
+def : InstRW<[C1UWrite_2or4c_1SA_1V01], (instregex "^SST1[BHW]_D$",
+ "^SST1D$")>;
+
+// SVE Miscellaneous instructions
+// -----------------------------------------------------------------------------
+
+// Read first fault register, unpredicated
+def : InstRW<[C1UWrite_2c_1M0], (instrs RDFFR_P)>;
+
+// Read first fault register, predicated
+def : InstRW<[C1UWrite_2c_1M0], (instrs RDFFR_PPz)>;
+
+// Read first fault register and set flags
+def : InstRW<[C1UWrite_3c_1M0], (instrs RDFFRS_PPz)>;
+
+// Set first fault register
+// Write to first fault register
+def : InstRW<[C1UWrite_2c_1M0], (instrs SETFFR, WRFFR)>;
+
+// Prefetch
+// NOTE: This is not specified in the SOG.
+def : InstRW<[C1UWrite_4c_1L], (instregex "^PRF[BHWD]")>;
+
+// SVE Cryptographic instructions
+// -----------------------------------------------------------------------------
+
+// Crypto AES ops
+def : InstRW<[C1UWrite_2c_1V0134], (instregex "^AES[DE]_ZZZ_B$",
+ "^AESI?MC_ZZ_B$")>;
+
+// Crypto SHA3 ops
+def : InstRW<[C1UWrite_2c_1V], (instregex "^(BCAX|EOR3)_ZZZZ$",
+ "^RAX1_ZZZ_D$",
+ "^XAR_ZZZI_[BHSD]$")>;
+
+// Crypto SM4 ops
+def : InstRW<[C1UWrite_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;
+
+}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
index f841e60..41ea355 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
@@ -24,6 +24,12 @@
CheckAny<[CheckHForm, CheckQForm]>,
CheckImmOperand<4, 1>]>>;
+// Identify LDR/STR Q-form scaled (and potentially extended) FP instructions
+def NeoverseQForm : MCSchedPredicate<
+ CheckAll<[
+ CheckAny<[CheckQForm]>,
+ CheckImmOperand<4, 1>]>>;
+
// Check if <Pd> == <Pg>
def NeoversePdIsPgFn : TIIPredicate<
"isNeoversePdSameAsPg",
@@ -100,3 +106,5 @@
CheckIsImmOperand<1>,
CheckImmOperand<1, 31>]>,
]>>;
+
+
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index 854d3ce..8de4e8d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -343,3 +343,80 @@
def IsRORImmIdiomPred : MCSchedPredicate< // EXTR Rd, Rs, Rs, #Imm
CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
CheckSameRegOperand<1, 2>]>>;
+
+// Identify whether destination operand is a W-form register.
+def CheckIsWRegOp0 : CheckAll<[
+ CheckIsRegOperand<0>,
+ CheckAny<[
+ CheckRegOperand<0, W0>, CheckRegOperand<0, W1>, CheckRegOperand<0, W2>,
+ CheckRegOperand<0, W3>, CheckRegOperand<0, W4>, CheckRegOperand<0, W5>,
+ CheckRegOperand<0, W6>, CheckRegOperand<0, W7>, CheckRegOperand<0, W8>,
+ CheckRegOperand<0, W9>, CheckRegOperand<0, W10>, CheckRegOperand<0, W11>,
+ CheckRegOperand<0, W12>, CheckRegOperand<0, W13>, CheckRegOperand<0, W14>,
+ CheckRegOperand<0, W15>, CheckRegOperand<0, W16>, CheckRegOperand<0, W17>,
+ CheckRegOperand<0, W18>, CheckRegOperand<0, W19>, CheckRegOperand<0, W20>,
+ CheckRegOperand<0, W21>, CheckRegOperand<0, W22>, CheckRegOperand<0, W23>,
+ CheckRegOperand<0, W24>, CheckRegOperand<0, W25>, CheckRegOperand<0, W26>,
+ CheckRegOperand<0, W27>, CheckRegOperand<0, W28>, CheckRegOperand<0, W29>,
+ CheckRegOperand<0, W30>, CheckRegOperand<0, WZR>, CheckRegOperand<0, WSP>
+ ]>
+]>;
+def IsWFormPred : MCSchedPredicate<CheckIsWRegOp0>;
+
+// Identify whether destination operand is an X-form register.
+def CheckIsXRegOp0 : CheckAll<[
+ CheckIsRegOperand<0>,
+ CheckAny<[
+ CheckRegOperand<0, X0>, CheckRegOperand<0, X1>, CheckRegOperand<0, X2>,
+ CheckRegOperand<0, X3>, CheckRegOperand<0, X4>, CheckRegOperand<0, X5>,
+ CheckRegOperand<0, X6>, CheckRegOperand<0, X7>, CheckRegOperand<0, X8>,
+ CheckRegOperand<0, X9>, CheckRegOperand<0, X10>, CheckRegOperand<0, X11>,
+ CheckRegOperand<0, X12>, CheckRegOperand<0, X13>, CheckRegOperand<0, X14>,
+ CheckRegOperand<0, X15>, CheckRegOperand<0, X16>, CheckRegOperand<0, X17>,
+ CheckRegOperand<0, X18>, CheckRegOperand<0, X19>, CheckRegOperand<0, X20>,
+ CheckRegOperand<0, X21>, CheckRegOperand<0, X22>, CheckRegOperand<0, X23>,
+ CheckRegOperand<0, X24>, CheckRegOperand<0, X25>, CheckRegOperand<0, X26>,
+ CheckRegOperand<0, X27>, CheckRegOperand<0, X28>, CheckRegOperand<0, FP>,
+ CheckRegOperand<0, LR>, CheckRegOperand<0, XZR>, CheckRegOperand<0, SP>
+ ]>
+]>;
+def IsXFormPred : MCSchedPredicate<CheckIsXRegOp0>;
+
+def IsXOrWDest : MCSchedPredicate<
+ CheckAll<[CheckAny<[CheckIsXRegOp0, CheckIsWRegOp0]>]>
+>;
+
+def CheckIsZRegOp0 : CheckAll<[
+ CheckIsRegOperand<0>,
+ CheckAny<[
+ CheckRegOperand<0, Z0>, CheckRegOperand<0, Z1>, CheckRegOperand<0, Z2>,
+ CheckRegOperand<0, Z3>, CheckRegOperand<0, Z4>, CheckRegOperand<0, Z5>,
+ CheckRegOperand<0, Z6>, CheckRegOperand<0, Z7>, CheckRegOperand<0, Z8>,
+ CheckRegOperand<0, Z9>, CheckRegOperand<0, Z10>, CheckRegOperand<0, Z11>,
+ CheckRegOperand<0, Z12>, CheckRegOperand<0, Z13>, CheckRegOperand<0, Z14>,
+ CheckRegOperand<0, Z15>, CheckRegOperand<0, Z16>, CheckRegOperand<0, Z17>,
+ CheckRegOperand<0, Z18>, CheckRegOperand<0, Z19>, CheckRegOperand<0, Z20>,
+ CheckRegOperand<0, Z21>, CheckRegOperand<0, Z22>, CheckRegOperand<0, Z23>,
+ CheckRegOperand<0, Z24>, CheckRegOperand<0, Z25>, CheckRegOperand<0, Z26>,
+ CheckRegOperand<0, Z27>, CheckRegOperand<0, Z28>, CheckRegOperand<0, Z29>,
+ CheckRegOperand<0, Z30>, CheckRegOperand<0, Z31>
+ ]>
+]>;
+
+
+// Check if destination and source are the same Z register (Zn == Zm)
+def SameZRegDstSrcPred : MCSchedPredicate<
+ CheckAll<[CheckSameRegOperand<0, 1>, CheckIsZRegOp0]>
+>;
+
+// Identify LDR/STR Q-form scaled (and potentially extended) FP instructions
+def FPIsQForm : MCSchedPredicate<
+ CheckAll<[
+ CheckAny<[CheckQForm]>,
+ CheckImmOperand<4, 1>]>>;
+
+// Check whether the subtarget enables SME.
+def SMESchedPred : FeatureSchedPredicate<FeatureSME>;
+
+// Check whether the subtarget enables SME and is in streaming mode.
+def SMEStreamingSchedPred : SchedPredicate<[{STI->hasSME() && STI->isStreaming()}]>;
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-basic-instructions.s
new file mode 100644
index 0000000..1d71612
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-basic-instructions.s
@@ -0,0 +1,2527 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.13 add w2, w3, #4095
+# CHECK-NEXT: 1 1 0.13 add w30, w29, #1, lsl #12
+# CHECK-NEXT: 1 1 0.13 add w13, w5, #4095, lsl #12
+# CHECK-NEXT: 1 1 0.13 add x5, x7, #1638
+# CHECK-NEXT: 1 1 0.13 add w20, wsp, #801
+# CHECK-NEXT: 1 1 0.13 add wsp, wsp, #1104
+# CHECK-NEXT: 1 1 0.13 add wsp, w30, #4084
+# CHECK-NEXT: 1 1 0.13 add x0, x24, #291
+# CHECK-NEXT: 1 1 0.13 add x3, x24, #4095, lsl #12
+# CHECK-NEXT: 1 1 0.13 add x8, sp, #1074
+# CHECK-NEXT: 1 1 0.13 add sp, x29, #3816
+# CHECK-NEXT: 1 1 0.13 sub w0, wsp, #4077
+# CHECK-NEXT: 1 1 0.13 sub w4, w20, #546, lsl #12
+# CHECK-NEXT: 1 1 0.13 sub sp, sp, #288
+# CHECK-NEXT: 1 1 0.13 sub wsp, w19, #16
+# CHECK-NEXT: 1 1 0.25 adds w13, w23, #291, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmn w2, #4095
+# CHECK-NEXT: 1 1 0.25 adds w20, wsp, #0
+# CHECK-NEXT: 1 1 0.25 cmn x3, #1, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmp wsp, #2342
+# CHECK-NEXT: 1 1 0.25 cmp sp, #20, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmp x30, #4095
+# CHECK-NEXT: 1 1 0.25 subs x4, sp, #3822
+# CHECK-NEXT: 1 1 0.25 cmn w3, #291, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmn wsp, #1365
+# CHECK-NEXT: 1 1 0.25 cmn sp, #1092, lsl #12
+# CHECK-NEXT: 1 1 0.13 mov x10, #-63432
+# CHECK-NEXT: 1 1 0.13 add wsp, wsp, w10
+# CHECK-NEXT: 1 1 0.13 add x25, x9, w25, uxtb
+# CHECK-NEXT: 1 1 0.13 add w3, w5, w7
+# CHECK-NEXT: 1 1 0.13 add wzr, w3, w5
+# CHECK-NEXT: 1 1 0.13 add w20, wzr, w4
+# CHECK-NEXT: 1 1 0.13 add w4, w6, wzr
+# CHECK-NEXT: 1 1 0.13 add w11, w13, w15
+# CHECK-NEXT: 1 1 0.13 add w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.13 add w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.13 add w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.13 add w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.13 add w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.13 add w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.13 add w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.13 add w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.13 add x3, x5, x7
+# CHECK-NEXT: 1 1 0.13 add xzr, x3, x5
+# CHECK-NEXT: 1 1 0.13 add x20, xzr, x4
+# CHECK-NEXT: 1 1 0.13 add x4, x6, xzr
+# CHECK-NEXT: 1 1 0.13 add x11, x13, x15
+# CHECK-NEXT: 1 2 0.13 add x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 1 0.13 add x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.13 add x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.13 add x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.13 add x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.13 add x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.13 add x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.13 add x8, x9, x10, asr #63
+# CHECK-NEXT: 1 2 0.25 adds w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 adds w17, wsp, w25
+# CHECK-NEXT: 1 1 0.25 adds x13, x23, w8, uxtb
+# CHECK-NEXT: 1 2 0.25 cmn w3, w5
+# CHECK-NEXT: 1 2 0.25 adds w20, wzr, w4
+# CHECK-NEXT: 1 2 0.25 adds w4, w6, wzr
+# CHECK-NEXT: 1 2 0.25 adds w11, w13, w15
+# CHECK-NEXT: 1 2 0.25 adds w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.25 adds w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.25 adds w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.25 adds w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.25 adds w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.25 adds w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.25 adds w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.25 adds w8, w9, w10, asr #31
+# CHECK-NEXT: 1 2 0.25 adds x3, x5, x7
+# CHECK-NEXT: 1 2 0.25 cmn x3, x5
+# CHECK-NEXT: 1 2 0.25 adds x20, xzr, x4
+# CHECK-NEXT: 1 2 0.25 adds x4, x6, xzr
+# CHECK-NEXT: 1 2 0.25 adds x11, x13, x15
+# CHECK-NEXT: 1 2 0.25 adds x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 2 0.25 adds x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.25 adds x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.25 adds x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.25 adds x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.25 adds x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.25 adds x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.25 adds x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.13 sub w3, w5, w7
+# CHECK-NEXT: 1 1 0.13 sub wzr, w3, w5
+# CHECK-NEXT: 1 1 0.13 sub w4, w6, wzr
+# CHECK-NEXT: 1 1 0.13 sub w11, w13, w15
+# CHECK-NEXT: 1 1 0.13 sub w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.13 sub w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.13 sub w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.13 sub w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.13 sub w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.13 sub w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.13 sub w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.13 sub w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.13 sub x3, x5, x7
+# CHECK-NEXT: 1 1 0.13 sub xzr, x3, x5
+# CHECK-NEXT: 1 1 0.13 sub x4, x6, xzr
+# CHECK-NEXT: 1 1 0.13 sub x11, x13, x15
+# CHECK-NEXT: 1 2 0.13 sub x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 1 0.13 sub x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.13 sub x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.13 sub x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.13 sub x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.13 sub x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.13 sub x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.13 sub x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.13 sub w13, wsp, w10
+# CHECK-NEXT: 1 1 0.13 sub x16, x2, w19, uxtb
+# CHECK-NEXT: 1 1 0.25 subs x13, x15, x14, sxtx #1
+# CHECK-NEXT: 1 2 0.25 subs w3, w5, w7
+# CHECK-NEXT: 1 2 0.25 cmp w3, w5
+# CHECK-NEXT: 1 2 0.25 subs w4, w6, wzr
+# CHECK-NEXT: 1 2 0.25 subs w11, w13, w15
+# CHECK-NEXT: 1 2 0.25 subs w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.25 subs w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.25 subs w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.25 subs w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.25 subs w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.25 subs w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.25 subs w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.25 subs w8, w9, w10, asr #31
+# CHECK-NEXT: 1 2 0.25 subs x3, x5, x7
+# CHECK-NEXT: 1 2 0.25 cmp x3, x5
+# CHECK-NEXT: 1 2 0.25 subs x4, x6, xzr
+# CHECK-NEXT: 1 2 0.25 subs x11, x13, x15
+# CHECK-NEXT: 1 2 0.25 subs x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 2 0.25 subs x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.25 subs x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.25 subs x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.25 subs x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.25 subs x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.25 subs x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.25 subs x8, x9, x10, asr #63
+# CHECK-NEXT: 1 2 0.25 cmn wzr, w4
+# CHECK-NEXT: 1 2 0.25 cmn w5, wzr
+# CHECK-NEXT: 1 2 0.25 cmn w6, w7
+# CHECK-NEXT: 1 2 0.25 cmn w8, w9, lsl #1
+# CHECK-NEXT: 1 2 0.25 cmn w10, w11, lsl #31
+# CHECK-NEXT: 1 2 0.25 cmn w12, w13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmn w14, w15, lsr #21
+# CHECK-NEXT: 1 2 0.25 cmn w16, w17, lsr #31
+# CHECK-NEXT: 1 2 0.25 cmn w18, w19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmn w20, w21, asr #22
+# CHECK-NEXT: 1 2 0.25 cmn w22, w23, asr #31
+# CHECK-NEXT: 1 2 0.25 cmn x0, x3
+# CHECK-NEXT: 1 2 0.25 cmn xzr, x4
+# CHECK-NEXT: 1 2 0.25 cmn x5, xzr
+# CHECK-NEXT: 1 2 0.25 cmn x6, x7
+# CHECK-NEXT: 1 2 0.25 cmn x8, x9, lsl #15
+# CHECK-NEXT: 1 2 0.25 cmn x10, x11, lsl #3
+# CHECK-NEXT: 1 2 0.25 cmn x12, x13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmn x14, x15, lsr #41
+# CHECK-NEXT: 1 2 0.25 cmn x16, x17, lsr #63
+# CHECK-NEXT: 1 2 0.25 cmn x18, x19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmn x20, x21, asr #55
+# CHECK-NEXT: 1 2 0.25 cmn x22, x23, asr #63
+# CHECK-NEXT: 1 2 0.25 cmp w0, w3
+# CHECK-NEXT: 1 2 0.25 cmp wzr, w4
+# CHECK-NEXT: 1 2 0.25 cmp w5, wzr
+# CHECK-NEXT: 1 2 0.25 cmp w6, w7
+# CHECK-NEXT: 1 2 0.25 cmp w8, w9, lsl #1
+# CHECK-NEXT: 1 2 0.25 cmp w10, w11, lsl #31
+# CHECK-NEXT: 1 2 0.25 cmp w12, w13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmp w14, w15, lsr #21
+# CHECK-NEXT: 1 2 0.25 cmp w18, w19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmp w20, w21, asr #22
+# CHECK-NEXT: 1 2 0.25 cmp w22, w23, asr #31
+# CHECK-NEXT: 1 1 0.25 cmp wsp, w26
+# CHECK-NEXT: 1 1 0.25 cmp x16, w27, uxtb
+# CHECK-NEXT: 1 2 0.25 cmp x0, x3
+# CHECK-NEXT: 1 2 0.25 cmp xzr, x4
+# CHECK-NEXT: 1 2 0.25 cmp x5, xzr
+# CHECK-NEXT: 1 2 0.25 cmp x6, x7
+# CHECK-NEXT: 1 2 0.25 cmp x8, x9, lsl #15
+# CHECK-NEXT: 1 2 0.25 cmp x10, x11, lsl #3
+# CHECK-NEXT: 1 2 0.25 cmp x12, x13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmp x14, x15, lsr #41
+# CHECK-NEXT: 1 2 0.25 cmp x16, x17, lsr #63
+# CHECK-NEXT: 1 2 0.25 cmp x18, x19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmp x20, x21, asr #55
+# CHECK-NEXT: 1 2 0.25 cmp x22, x23, asr #63
+# CHECK-NEXT: 1 2 0.25 cmp wzr, w0
+# CHECK-NEXT: 1 2 0.25 cmp xzr, x0
+# CHECK-NEXT: 1 1 0.13 mov sp, x30
+# CHECK-NEXT: 1 1 0.13 mov wsp, w20
+# CHECK-NEXT: 1 1 0.13 mov x11, sp
+# CHECK-NEXT: 1 1 0.13 mov w24, wsp
+# CHECK-NEXT: 1 1 0.13 adc w29, w27, w25
+# CHECK-NEXT: 1 1 0.13 adc wzr, w3, w4
+# CHECK-NEXT: 1 1 0.13 adc w9, wzr, w10
+# CHECK-NEXT: 1 1 0.13 adc w20, w0, wzr
+# CHECK-NEXT: 1 1 0.13 adc x29, x27, x25
+# CHECK-NEXT: 1 1 0.13 adc xzr, x3, x4
+# CHECK-NEXT: 1 1 0.13 adc x9, xzr, x10
+# CHECK-NEXT: 1 1 0.13 adc x20, x0, xzr
+# CHECK-NEXT: 1 1 0.25 adcs w29, w27, w25
+# CHECK-NEXT: 1 1 0.25 adcs wzr, w3, w4
+# CHECK-NEXT: 1 1 0.25 adcs w9, wzr, w10
+# CHECK-NEXT: 1 1 0.25 adcs w20, w0, wzr
+# CHECK-NEXT: 1 1 0.25 adcs x29, x27, x25
+# CHECK-NEXT: 1 1 0.25 adcs xzr, x3, x4
+# CHECK-NEXT: 1 1 0.25 adcs x9, xzr, x10
+# CHECK-NEXT: 1 1 0.25 adcs x20, x0, xzr
+# CHECK-NEXT: 1 1 0.13 sbc w29, w27, w25
+# CHECK-NEXT: 1 1 0.13 sbc wzr, w3, w4
+# CHECK-NEXT: 1 1 0.13 ngc w9, w10
+# CHECK-NEXT: 1 1 0.13 sbc w20, w0, wzr
+# CHECK-NEXT: 1 1 0.13 sbc x29, x27, x25
+# CHECK-NEXT: 1 1 0.13 sbc xzr, x3, x4
+# CHECK-NEXT: 1 1 0.13 ngc x9, x10
+# CHECK-NEXT: 1 1 0.13 sbc x20, x0, xzr
+# CHECK-NEXT: 1 1 0.25 sbcs w29, w27, w25
+# CHECK-NEXT: 1 1 0.25 sbcs wzr, w3, w4
+# CHECK-NEXT: 1 1 0.25 ngcs w9, w10
+# CHECK-NEXT: 1 1 0.25 sbcs w20, w0, wzr
+# CHECK-NEXT: 1 1 0.25 sbcs x29, x27, x25
+# CHECK-NEXT: 1 1 0.25 sbcs xzr, x3, x4
+# CHECK-NEXT: 1 1 0.25 ngcs x9, x10
+# CHECK-NEXT: 1 1 0.25 sbcs x20, x0, xzr
+# CHECK-NEXT: 1 1 0.13 ngc w3, w12
+# CHECK-NEXT: 1 1 0.13 ngc wzr, w9
+# CHECK-NEXT: 1 1 0.13 ngc w23, wzr
+# CHECK-NEXT: 1 1 0.13 ngc x29, x30
+# CHECK-NEXT: 1 1 0.13 ngc xzr, x0
+# CHECK-NEXT: 1 1 0.13 ngc x0, xzr
+# CHECK-NEXT: 1 1 0.25 ngcs w3, w12
+# CHECK-NEXT: 1 1 0.25 ngcs wzr, w9
+# CHECK-NEXT: 1 1 0.25 ngcs w23, wzr
+# CHECK-NEXT: 1 1 0.25 ngcs x29, x30
+# CHECK-NEXT: 1 1 0.25 ngcs xzr, x0
+# CHECK-NEXT: 1 1 0.25 ngcs x0, xzr
+# CHECK-NEXT: 1 1 0.13 sbfx x1, x2, #3, #2
+# CHECK-NEXT: 1 1 0.13 asr x3, x4, #63
+# CHECK-NEXT: 1 1 0.13 asr wzr, wzr, #31
+# CHECK-NEXT: 1 1 0.13 sbfx w12, w9, #0, #1
+# CHECK-NEXT: 1 1 0.13 ubfiz x4, x5, #52, #11
+# CHECK-NEXT: 1 1 0.13 ubfx xzr, x4, #0, #1
+# CHECK-NEXT: 1 1 0.13 ubfiz x4, xzr, #1, #6
+# CHECK-NEXT: 1 1 0.13 lsr x5, x6, #12
+# CHECK-NEXT: 1 2 0.13 bfi x4, x5, #52, #11
+# CHECK-NEXT: 1 2 0.13 bfxil xzr, x4, #0, #1
+# CHECK-NEXT: 1 2 0.13 bfc x4, #1, #6
+# CHECK-NEXT: 1 2 0.13 bfxil x5, x6, #12, #52
+# CHECK-NEXT: 1 1 0.13 sxtb w1, w2
+# CHECK-NEXT: 1 1 0.13 sxtb xzr, w3
+# CHECK-NEXT: 1 1 0.13 sxth w9, w10
+# CHECK-NEXT: 1 1 0.13 sxth x0, w1
+# CHECK-NEXT: 1 1 0.13 sxtw x3, w30
+# CHECK-NEXT: 1 1 0.13 uxtb w1, w2
+# CHECK-NEXT: 1 1 0.13 uxth w9, w10
+# CHECK-NEXT: 1 1 0.13 ubfx x3, x30, #0, #32
+# CHECK-NEXT: 1 1 0.13 asr w3, w2, #0
+# CHECK-NEXT: 1 1 0.13 asr w9, w10, #31
+# CHECK-NEXT: 1 1 0.13 asr x20, x21, #63
+# CHECK-NEXT: 1 1 0.13 asr w1, wzr, #3
+# CHECK-NEXT: 1 1 0.13 lsr w3, w2, #0
+# CHECK-NEXT: 1 1 0.13 lsr w9, w10, #31
+# CHECK-NEXT: 1 1 0.13 lsr x20, x21, #63
+# CHECK-NEXT: 1 1 0.13 lsr wzr, wzr, #3
+# CHECK-NEXT: 1 1 0.13 lsl w9, w10, #31
+# CHECK-NEXT: 1 1 0.13 lsl x20, x21, #63
+# CHECK-NEXT: 1 1 0.13 lsl w1, wzr, #3
+# CHECK-NEXT: 1 1 0.13 sbfiz x2, x3, #63, #1
+# CHECK-NEXT: 1 1 0.13 sbfiz x9, x10, #5, #59
+# CHECK-NEXT: 1 1 0.13 sbfiz w11, w12, #31, #1
+# CHECK-NEXT: 1 1 0.13 sbfiz w13, w14, #29, #3
+# CHECK-NEXT: 1 1 0.13 sbfiz xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.13 sbfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.13 asr x2, x3, #63
+# CHECK-NEXT: 1 1 0.13 asr x19, x20, #0
+# CHECK-NEXT: 1 1 0.13 asr x9, x10, #5
+# CHECK-NEXT: 1 1 0.13 asr w9, w10, #0
+# CHECK-NEXT: 1 1 0.13 asr w11, w12, #31
+# CHECK-NEXT: 1 1 0.13 asr w13, w14, #29
+# CHECK-NEXT: 1 1 0.13 sbfx xzr, xzr, #10, #11
+# CHECK-NEXT: 1 2 0.13 bfi x2, x3, #63, #1
+# CHECK-NEXT: 1 2 0.13 bfi x9, x10, #5, #59
+# CHECK-NEXT: 1 2 0.13 bfi w11, w12, #31, #1
+# CHECK-NEXT: 1 2 0.13 bfi w13, w14, #29, #3
+# CHECK-NEXT: 1 2 0.13 bfc xzr, #10, #11
+# CHECK-NEXT: 1 2 0.13 bfxil w9, w10, #0, #1
+# CHECK-NEXT: 1 2 0.13 bfxil x2, x3, #63, #1
+# CHECK-NEXT: 1 2 0.13 bfxil x19, x20, #0, #64
+# CHECK-NEXT: 1 2 0.13 bfxil x9, x10, #5, #59
+# CHECK-NEXT: 1 2 0.13 bfxil w9, w10, #0, #32
+# CHECK-NEXT: 1 2 0.13 bfxil w11, w12, #31, #1
+# CHECK-NEXT: 1 2 0.13 bfxil w13, w14, #29, #3
+# CHECK-NEXT: 1 2 0.13 bfxil xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.13 lsl x2, x3, #63
+# CHECK-NEXT: 1 1 0.13 lsl x9, x10, #5
+# CHECK-NEXT: 1 1 0.13 lsl w11, w12, #31
+# CHECK-NEXT: 1 1 0.13 lsl w13, w14, #29
+# CHECK-NEXT: 1 1 0.13 ubfiz xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.13 ubfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.13 lsr x2, x3, #63
+# CHECK-NEXT: 1 1 0.13 lsr x19, x20, #0
+# CHECK-NEXT: 1 1 0.13 lsr x9, x10, #5
+# CHECK-NEXT: 1 1 0.13 lsr w9, w10, #0
+# CHECK-NEXT: 1 1 0.13 lsr w11, w12, #31
+# CHECK-NEXT: 1 1 0.13 lsr w13, w14, #29
+# CHECK-NEXT: 1 1 0.13 ubfx xzr, xzr, #10, #11
+# CHECK-NEXT: 1 2 0.33 cbz w5, #4
+# CHECK-NEXT: 1 2 0.33 cbz x5, #0
+# CHECK-NEXT: 1 2 0.33 cbnz x2, #-4
+# CHECK-NEXT: 1 2 0.33 cbnz x26, #1048572
+# CHECK-NEXT: 1 2 0.33 cbz wzr, #0
+# CHECK-NEXT: 1 2 0.33 cbnz xzr, #0
+# CHECK-NEXT: 1 2 0.33 cbnz w21, test
+# CHECK-NEXT: 1 2 0.33 b.ne #4
+# CHECK-NEXT: 1 2 0.33 b.ge #1048572
+# CHECK-NEXT: 1 2 0.33 b.ge #-4
+# CHECK-NEXT: 1 1 0.25 ccmp w1, #31, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmp w3, #0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmp wzr, #15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmp x9, #31, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmp x3, #0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmp xzr, #5, #7, ne
+# CHECK-NEXT: 1 1 0.25 ccmn w1, #31, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmn w3, #0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmn wzr, #15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmn x9, #31, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmn x3, #0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmn xzr, #5, #7, ne
+# CHECK-NEXT: 1 1 0.25 ccmp w1, wzr, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmp w3, w0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmp wzr, w15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmp x9, xzr, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmp x3, x0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmp xzr, x5, #7, ne
+# CHECK-NEXT: 1 1 0.25 ccmn w1, wzr, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmn w3, w0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmn wzr, w15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmn x9, xzr, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmn x3, x0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmn xzr, x5, #7, ne
+# CHECK-NEXT: 1 1 0.13 csel w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csel wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csel w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csel w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csel x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csel xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csel x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csel x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 csinc w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csinc wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csinc w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csinc w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csinc x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csinc xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csinc x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csinc x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 csinv w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csinv wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csinv w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csinv w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csinv x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csinv xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csinv x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csinv x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 csneg w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csneg wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csneg w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csneg w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csneg x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csneg xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csneg x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csneg x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 cset w3, eq
+# CHECK-NEXT: 1 1 0.13 cset x9, pl
+# CHECK-NEXT: 1 1 0.13 csetm w20, ne
+# CHECK-NEXT: 1 1 0.13 csetm x30, ge
+# CHECK-NEXT: 1 1 0.13 csinc w2, wzr, wzr, al
+# CHECK-NEXT: 1 1 0.13 csinv x3, xzr, xzr, nv
+# CHECK-NEXT: 1 1 0.13 cinc w3, w5, gt
+# CHECK-NEXT: 1 1 0.13 cinc wzr, w4, le
+# CHECK-NEXT: 1 1 0.13 cset w9, lt
+# CHECK-NEXT: 1 1 0.13 cinc x3, x5, gt
+# CHECK-NEXT: 1 1 0.13 cinc xzr, x4, le
+# CHECK-NEXT: 1 1 0.13 cset x9, lt
+# CHECK-NEXT: 1 1 0.13 csinc w5, w6, w6, nv
+# CHECK-NEXT: 1 1 0.13 csinc x1, x2, x2, al
+# CHECK-NEXT: 1 1 0.13 cinv w3, w5, gt
+# CHECK-NEXT: 1 1 0.13 cinv wzr, w4, le
+# CHECK-NEXT: 1 1 0.13 csetm w9, lt
+# CHECK-NEXT: 1 1 0.13 cinv x3, x5, gt
+# CHECK-NEXT: 1 1 0.13 cinv xzr, x4, le
+# CHECK-NEXT: 1 1 0.13 csetm x9, lt
+# CHECK-NEXT: 1 1 0.13 csinv x1, x0, x0, al
+# CHECK-NEXT: 1 1 0.13 csinv w9, w8, w8, nv
+# CHECK-NEXT: 1 1 0.13 cneg w3, w5, gt
+# CHECK-NEXT: 1 1 0.13 cneg wzr, w4, le
+# CHECK-NEXT: 1 1 0.13 cneg w9, wzr, lt
+# CHECK-NEXT: 1 1 0.13 cneg x3, x5, gt
+# CHECK-NEXT: 1 1 0.13 cneg xzr, x4, le
+# CHECK-NEXT: 1 1 0.13 cneg x9, xzr, lt
+# CHECK-NEXT: 1 1 0.13 csneg x4, x8, x8, al
+# CHECK-NEXT: 1 1 0.13 rbit w0, w7
+# CHECK-NEXT: 1 1 0.13 rbit x18, x3
+# CHECK-NEXT: 1 1 0.13 rev16 w17, w1
+# CHECK-NEXT: 1 1 0.13 rev16 x5, x2
+# CHECK-NEXT: 1 1 0.13 rev w18, w0
+# CHECK-NEXT: 1 1 0.13 rev32 x20, x1
+# CHECK-NEXT: 1 1 0.13 rev x22, x2
+# CHECK-NEXT: 1 1 0.13 clz w24, w3
+# CHECK-NEXT: 1 1 0.13 clz x26, x4
+# CHECK-NEXT: 1 1 0.13 cls w3, w5
+# CHECK-NEXT: 1 1 0.13 cls x20, x5
+# CHECK-NEXT: 1 12 12.00 udiv w0, w7, w10
+# CHECK-NEXT: 1 20 20.00 udiv x9, x22, x4
+# CHECK-NEXT: 1 12 12.00 sdiv w12, w21, w0
+# CHECK-NEXT: 1 20 20.00 sdiv x13, x2, x1
+# CHECK-NEXT: 1 1 0.13 lsl w11, w12, w13
+# CHECK-NEXT: 1 1 0.13 lsl x14, x15, x16
+# CHECK-NEXT: 1 1 0.13 lsr w17, w18, w19
+# CHECK-NEXT: 1 1 0.13 lsr x20, x21, x22
+# CHECK-NEXT: 1 1 0.13 asr w23, w24, w25
+# CHECK-NEXT: 1 1 0.13 asr x26, x27, x28
+# CHECK-NEXT: 1 1 0.13 ror w0, w1, w2
+# CHECK-NEXT: 1 1 0.13 ror x3, x4, x5
+# CHECK-NEXT: 1 1 0.13 lsl w6, w7, w8
+# CHECK-NEXT: 1 1 0.13 lsl x9, x10, x11
+# CHECK-NEXT: 1 1 0.13 lsr w12, w13, w14
+# CHECK-NEXT: 1 1 0.13 lsr x15, x16, x17
+# CHECK-NEXT: 1 1 0.13 asr w18, w19, w20
+# CHECK-NEXT: 1 1 0.13 asr x21, x22, x23
+# CHECK-NEXT: 1 1 0.13 ror w24, w25, w26
+# CHECK-NEXT: 1 1 0.13 ror x27, x28, x29
+# CHECK-NEXT: 1 2 0.50 crc32cb w30, w23, w15
+# CHECK-NEXT: 1 2 0.50 crc32cb wzr, w12, w14
+# CHECK-NEXT: 1 2 0.50 crc32cb w28, w10, w11
+# CHECK-NEXT: 1 2 0.50 crc32b w27, w12, w15
+# CHECK-NEXT: 1 2 0.50 crc32h w3, w15, w21
+# CHECK-NEXT: 1 2 0.50 crc32w w9, w18, w24
+# CHECK-NEXT: 1 2 0.50 crc32x w19, w6, x25
+# CHECK-NEXT: 1 2 0.50 crc32ch w25, w26, w16
+# CHECK-NEXT: 1 2 0.50 crc32cw w27, w12, w23
+# CHECK-NEXT: 1 2 0.50 crc32cx w21, w28, x5
+# CHECK-NEXT: 1 2 0.25 smulh x30, x29, x28
+# CHECK-NEXT: 1 2 0.25 smulh xzr, x27, x26
+# CHECK-NEXT: 1 2 0.25 umulh x30, x29, x28
+# CHECK-NEXT: 1 2 0.25 umulh x23, x30, xzr
+# CHECK-NEXT: 1 3 0.25 madd w1, w3, w7, w4
+# CHECK-NEXT: 1 3 0.25 madd wzr, w0, w9, w11
+# CHECK-NEXT: 1 3 0.25 madd w13, wzr, w4, w4
+# CHECK-NEXT: 1 3 0.25 madd w19, w30, wzr, w29
+# CHECK-NEXT: 1 2 0.25 mul w4, w5, w6
+# CHECK-NEXT: 1 3 0.25 madd x1, x3, x7, x4
+# CHECK-NEXT: 1 3 0.25 madd xzr, x0, x9, x11
+# CHECK-NEXT: 1 3 0.25 madd x13, xzr, x4, x4
+# CHECK-NEXT: 1 3 0.25 madd x19, x30, xzr, x29
+# CHECK-NEXT: 1 2 0.25 mul x4, x5, x6
+# CHECK-NEXT: 1 3 0.25 msub w1, w3, w7, w4
+# CHECK-NEXT: 1 3 0.25 msub wzr, w0, w9, w11
+# CHECK-NEXT: 1 3 0.25 msub w13, wzr, w4, w4
+# CHECK-NEXT: 1 3 0.25 msub w19, w30, wzr, w29
+# CHECK-NEXT: 1 2 0.25 mneg w4, w5, w6
+# CHECK-NEXT: 1 3 0.25 msub x1, x3, x7, x4
+# CHECK-NEXT: 1 3 0.25 msub xzr, x0, x9, x11
+# CHECK-NEXT: 1 3 0.25 msub x13, xzr, x4, x4
+# CHECK-NEXT: 1 3 0.25 msub x19, x30, xzr, x29
+# CHECK-NEXT: 1 2 0.25 mneg x4, x5, x6
+# CHECK-NEXT: 1 3 0.25 smaddl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 smaddl xzr, w10, w11, x12
+# CHECK-NEXT: 1 3 0.25 smaddl x13, wzr, w14, x15
+# CHECK-NEXT: 1 3 0.25 smaddl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 smull x19, w20, w21
+# CHECK-NEXT: 1 3 0.25 smsubl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 smsubl xzr, w10, w11, x12
+# CHECK-NEXT: 1 3 0.25 smsubl x13, wzr, w14, x15
+# CHECK-NEXT: 1 3 0.25 smsubl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 smnegl x19, w20, w21
+# CHECK-NEXT: 1 3 0.25 umaddl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 umaddl xzr, w10, w11, x12
+# CHECK-NEXT: 1 3 0.25 umaddl x13, wzr, w14, x15
+# CHECK-NEXT: 1 3 0.25 umaddl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 umull x19, w20, w21
+# CHECK-NEXT: 1 3 0.25 umsubl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 umsubl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 umnegl x19, w20, w21
+# CHECK-NEXT: 1 2 0.25 smulh x23, x22, xzr
+# CHECK-NEXT: 1 2 0.25 umulh x23, x22, xzr
+# CHECK-NEXT: 1 2 0.25 mul x19, x20, xzr
+# CHECK-NEXT: 1 2 0.25 mneg w21, w22, w23
+# CHECK-NEXT: 1 2 0.25 smull x11, w13, w17
+# CHECK-NEXT: 1 2 0.25 umull x11, w13, w17
+# CHECK-NEXT: 1 2 0.25 smnegl x11, w13, w17
+# CHECK-NEXT: 1 2 0.25 umnegl x11, w13, w17
+# CHECK-NEXT: 1 3 0.13 extr w3, w5, w7, #0
+# CHECK-NEXT: 1 3 0.13 extr w11, w13, w17, #31
+# CHECK-NEXT: 1 3 0.13 extr x3, x5, x7, #15
+# CHECK-NEXT: 1 3 0.13 extr x11, x13, x17, #63
+# CHECK-NEXT: 1 1 0.13 ror x19, x23, #24
+# CHECK-NEXT: 1 1 0.13 ror x29, xzr, #63
+# CHECK-NEXT: 1 1 0.13 ror w9, w13, #31
+# CHECK-NEXT: 1 2 0.50 fcmp h5, h21
+# CHECK-NEXT: 1 2 0.50 fcmp h5, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmpe h22, h21
+# CHECK-NEXT: 1 2 0.50 fcmpe h13, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmp s3, s5
+# CHECK-NEXT: 1 2 0.50 fcmp s31, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmpe s29, s30
+# CHECK-NEXT: 1 2 0.50 fcmpe s15, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmp d4, d12
+# CHECK-NEXT: 1 2 0.50 fcmp d23, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmpe d26, d22
+# CHECK-NEXT: 1 2 0.50 fcmpe d29, #0.0
+# CHECK-NEXT: 1 2 0.50 fccmp s1, s31, #0, eq
+# CHECK-NEXT: 1 2 0.50 fccmp s3, s0, #15, hs
+# CHECK-NEXT: 1 2 0.50 fccmp s31, s15, #13, hs
+# CHECK-NEXT: 1 2 0.50 fccmp d9, d31, #0, le
+# CHECK-NEXT: 1 2 0.50 fccmp d3, d0, #15, gt
+# CHECK-NEXT: 1 2 0.50 fccmp d31, d5, #7, ne
+# CHECK-NEXT: 1 2 0.50 fccmp h31, h3, #11, hs
+# CHECK-NEXT: 1 2 0.50 fccmpe h6, h1, #12, ne
+# CHECK-NEXT: 1 2 0.50 fccmpe s1, s31, #0, eq
+# CHECK-NEXT: 1 2 0.50 fccmpe s3, s0, #15, hs
+# CHECK-NEXT: 1 2 0.50 fccmpe s31, s15, #13, hs
+# CHECK-NEXT: 1 2 0.50 fccmpe d9, d31, #0, le
+# CHECK-NEXT: 1 2 0.50 fccmpe d3, d0, #15, gt
+# CHECK-NEXT: 1 2 0.50 fccmpe d31, d5, #7, ne
+# CHECK-NEXT: 1 2 0.17 fcsel s3, s20, s9, pl
+# CHECK-NEXT: 1 2 0.17 fcsel d9, d10, d11, mi
+# CHECK-NEXT: 1 2 0.17 fcsel h26, h2, h11, hs
+# CHECK-NEXT: 1 2 0.17 fmov h18, h28
+# CHECK-NEXT: 1 2 0.17 fmov s0, s1
+# CHECK-NEXT: 1 2 0.17 fabs s2, s3
+# CHECK-NEXT: 1 2 0.17 fneg h2, h9
+# CHECK-NEXT: 1 2 0.17 fneg s4, s5
+# CHECK-NEXT: 1 8 1.00 fsqrt s6, s7
+# CHECK-NEXT: 1 3 0.25 fcvt d8, s9
+# CHECK-NEXT: 1 3 0.25 fcvt h10, s11
+# CHECK-NEXT: 1 2 0.25 frintn h12, h3
+# CHECK-NEXT: 1 2 0.25 frintn s12, s13
+# CHECK-NEXT: 1 2 0.25 frintp h17, h31
+# CHECK-NEXT: 1 2 0.25 frintp s14, s15
+# CHECK-NEXT: 1 2 0.25 frintm h0, h21
+# CHECK-NEXT: 1 2 0.25 frintm s16, s17
+# CHECK-NEXT: 1 2 0.25 frintz h10, h29
+# CHECK-NEXT: 1 2 0.25 frintz s18, s19
+# CHECK-NEXT: 1 2 0.25 frinta h22, h10
+# CHECK-NEXT: 1 2 0.25 frinta s20, s21
+# CHECK-NEXT: 1 2 0.25 frintx h4, h5
+# CHECK-NEXT: 1 2 0.25 frintx s22, s23
+# CHECK-NEXT: 1 2 0.25 frinti s24, s25
+# CHECK-NEXT: 1 2 0.25 frinti h31, h14
+# CHECK-NEXT: 1 2 0.17 fmov d0, d1
+# CHECK-NEXT: 1 2 0.17 fabs d2, d3
+# CHECK-NEXT: 1 2 0.17 fneg d4, d5
+# CHECK-NEXT: 1 5 1.00 fsqrt h13, h24
+# CHECK-NEXT: 1 12 1.00 fsqrt d6, d7
+# CHECK-NEXT: 1 3 0.25 fcvt s8, d9
+# CHECK-NEXT: 1 3 0.25 fcvt h10, d11
+# CHECK-NEXT: 1 2 0.25 frintn d12, d13
+# CHECK-NEXT: 1 2 0.25 frintp d14, d15
+# CHECK-NEXT: 1 2 0.25 frintm d16, d17
+# CHECK-NEXT: 1 2 0.25 frintz d18, d19
+# CHECK-NEXT: 1 2 0.25 frinta d20, d21
+# CHECK-NEXT: 1 2 0.25 frintx d22, d23
+# CHECK-NEXT: 1 2 0.25 frinti d24, d25
+# CHECK-NEXT: 1 3 0.25 fcvt s26, h27
+# CHECK-NEXT: 1 3 0.25 fcvt d28, h29
+# CHECK-NEXT: 1 3 0.17 fmul s20, s19, s17
+# CHECK-NEXT: 1 5 1.00 fdiv h1, h26, h23
+# CHECK-NEXT: 1 8 1.00 fdiv s1, s2, s3
+# CHECK-NEXT: 1 2 0.17 fadd h23, h27, h22
+# CHECK-NEXT: 1 2 0.17 fadd s4, s5, s6
+# CHECK-NEXT: 1 2 0.17 fsub h20, h11, h18
+# CHECK-NEXT: 1 2 0.17 fsub s7, s8, s9
+# CHECK-NEXT: 1 2 0.17 fmax s10, s11, s12
+# CHECK-NEXT: 1 2 0.17 fmax h8, h7, h11
+# CHECK-NEXT: 1 2 0.17 fmin s13, s14, s15
+# CHECK-NEXT: 1 2 0.17 fmaxnm h29, h13, h14
+# CHECK-NEXT: 1 2 0.17 fmaxnm s16, s17, s18
+# CHECK-NEXT: 1 2 0.17 fminnm s19, s20, s21
+# CHECK-NEXT: 1 3 0.17 fnmul h3, h15, h7
+# CHECK-NEXT: 1 3 0.17 fnmul s22, s23, s2
+# CHECK-NEXT: 1 3 0.17 fmul d20, d19, d17
+# CHECK-NEXT: 1 12 1.00 fdiv d1, d2, d3
+# CHECK-NEXT: 1 2 0.17 fadd d4, d5, d6
+# CHECK-NEXT: 1 2 0.17 fsub d7, d8, d9
+# CHECK-NEXT: 1 2 0.17 fmax d10, d11, d12
+# CHECK-NEXT: 1 2 0.17 fmin d13, d14, d15
+# CHECK-NEXT: 1 2 0.17 fmin h4, h13, h17
+# CHECK-NEXT: 1 2 0.17 fmaxnm d16, d17, d18
+# CHECK-NEXT: 1 2 0.17 fminnm d19, d20, d21
+# CHECK-NEXT: 1 2 0.17 fminnm h29, h23, h17
+# CHECK-NEXT: 1 3 0.17 fnmul d22, d23, d24
+# CHECK-NEXT: 1 4 0.17 fmadd h27, h0, h6, h28
+# CHECK-NEXT: 1 4 0.17 fmadd s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.17 fmadd d3, d13, d0, d23
+# CHECK-NEXT: 1 4 0.17 fmsub h25, h28, h12, h24
+# CHECK-NEXT: 1 4 0.17 fmsub s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.17 fmsub d3, d13, d0, d23
+# CHECK-NEXT: 1 4 0.17 fnmadd h3, h18, h31, h24
+# CHECK-NEXT: 1 4 0.17 fnmadd s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.17 fnmadd d3, d13, d0, d23
+# CHECK-NEXT: 1 4 0.17 fnmsub s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.17 fnmsub d3, d13, d0, d23
+# CHECK-NEXT: 1 4 0.17 fnmsub h3, h29, h24, h17
+# CHECK-NEXT: 1 3 0.50 fcvtzs w3, h5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs wzr, h20, #13
+# CHECK-NEXT: 1 3 0.50 fcvtzs w19, h0, #32
+# CHECK-NEXT: 1 3 0.50 fcvtzs x3, h5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs x12, h30, #45
+# CHECK-NEXT: 1 3 0.50 fcvtzs x19, h0, #64
+# CHECK-NEXT: 1 3 0.50 fcvtzs w3, s5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs wzr, s20, #13
+# CHECK-NEXT: 1 3 0.50 fcvtzs w19, s0, #32
+# CHECK-NEXT: 1 3 0.50 fcvtzs x3, s5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs x12, s30, #45
+# CHECK-NEXT: 1 3 0.50 fcvtzs x19, s0, #64
+# CHECK-NEXT: 1 3 0.50 fcvtzs w3, d5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs wzr, d20, #13
+# CHECK-NEXT: 1 3 0.50 fcvtzs w19, d0, #32
+# CHECK-NEXT: 1 3 0.50 fcvtzs x3, d5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs x12, d30, #45
+# CHECK-NEXT: 1 3 0.50 fcvtzs x19, d0, #64
+# CHECK-NEXT: 1 3 0.50 fcvtzu w3, h5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu wzr, h20, #13
+# CHECK-NEXT: 1 3 0.50 fcvtzu w19, h0, #32
+# CHECK-NEXT: 1 3 0.50 fcvtzu x3, h5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu x12, h30, #45
+# CHECK-NEXT: 1 3 0.50 fcvtzu x19, h0, #64
+# CHECK-NEXT: 1 3 0.50 fcvtzu w3, s5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu wzr, s20, #13
+# CHECK-NEXT: 1 3 0.50 fcvtzu w19, s0, #32
+# CHECK-NEXT: 1 3 0.50 fcvtzu x3, s5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu x12, s30, #45
+# CHECK-NEXT: 1 3 0.50 fcvtzu x19, s0, #64
+# CHECK-NEXT: 1 3 0.50 fcvtzu w3, d5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu wzr, d20, #13
+# CHECK-NEXT: 1 3 0.50 fcvtzu w19, d0, #32
+# CHECK-NEXT: 1 3 0.50 fcvtzu x3, d5, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu x12, d30, #45
+# CHECK-NEXT: 1 3 0.50 fcvtzu x19, d0, #64
+# CHECK-NEXT: 1 3 1.00 scvtf h23, w19, #1
+# CHECK-NEXT: 1 3 1.00 scvtf h31, wzr, #20
+# CHECK-NEXT: 1 3 1.00 scvtf h14, w0, #32
+# CHECK-NEXT: 1 3 1.00 scvtf h23, x19, #1
+# CHECK-NEXT: 1 3 1.00 scvtf h31, xzr, #20
+# CHECK-NEXT: 1 3 1.00 scvtf h14, x0, #64
+# CHECK-NEXT: 1 3 1.00 scvtf s23, w19, #1
+# CHECK-NEXT: 1 3 1.00 scvtf s31, wzr, #20
+# CHECK-NEXT: 1 3 1.00 scvtf s14, w0, #32
+# CHECK-NEXT: 1 3 1.00 scvtf s23, x19, #1
+# CHECK-NEXT: 1 3 1.00 scvtf s31, xzr, #20
+# CHECK-NEXT: 1 3 1.00 scvtf s14, x0, #64
+# CHECK-NEXT: 1 3 1.00 scvtf d23, w19, #1
+# CHECK-NEXT: 1 3 1.00 scvtf d31, wzr, #20
+# CHECK-NEXT: 1 3 1.00 scvtf d14, w0, #32
+# CHECK-NEXT: 1 3 1.00 scvtf d23, x19, #1
+# CHECK-NEXT: 1 3 1.00 scvtf d31, xzr, #20
+# CHECK-NEXT: 1 3 1.00 scvtf d14, x0, #64
+# CHECK-NEXT: 1 3 1.00 ucvtf h23, w19, #1
+# CHECK-NEXT: 1 3 1.00 ucvtf h31, wzr, #20
+# CHECK-NEXT: 1 3 1.00 ucvtf h14, w0, #32
+# CHECK-NEXT: 1 3 1.00 ucvtf h23, x19, #1
+# CHECK-NEXT: 1 3 1.00 ucvtf h31, xzr, #20
+# CHECK-NEXT: 1 3 1.00 ucvtf h14, x0, #64
+# CHECK-NEXT: 1 3 1.00 ucvtf s23, w19, #1
+# CHECK-NEXT: 1 3 1.00 ucvtf s31, wzr, #20
+# CHECK-NEXT: 1 3 1.00 ucvtf s14, w0, #32
+# CHECK-NEXT: 1 3 1.00 ucvtf s23, x19, #1
+# CHECK-NEXT: 1 3 1.00 ucvtf s31, xzr, #20
+# CHECK-NEXT: 1 3 1.00 ucvtf s14, x0, #64
+# CHECK-NEXT: 1 3 1.00 ucvtf d23, w19, #1
+# CHECK-NEXT: 1 3 1.00 ucvtf d31, wzr, #20
+# CHECK-NEXT: 1 3 1.00 ucvtf d14, w0, #32
+# CHECK-NEXT: 1 3 1.00 ucvtf d23, x19, #1
+# CHECK-NEXT: 1 3 1.00 ucvtf d31, xzr, #20
+# CHECK-NEXT: 1 3 1.00 ucvtf d14, x0, #64
+# CHECK-NEXT: 1 3 0.50 fcvtns w3, h31
+# CHECK-NEXT: 1 3 0.50 fcvtns xzr, h12
+# CHECK-NEXT: 1 3 0.50 fcvtnu wzr, h12
+# CHECK-NEXT: 1 3 0.50 fcvtnu x0, h0
+# CHECK-NEXT: 1 3 0.50 fcvtps wzr, h9
+# CHECK-NEXT: 1 3 0.50 fcvtps x12, h20
+# CHECK-NEXT: 1 3 0.50 fcvtpu w30, h23
+# CHECK-NEXT: 1 3 0.50 fcvtpu x29, h3
+# CHECK-NEXT: 1 3 0.50 fcvtms w2, h3
+# CHECK-NEXT: 1 3 0.50 fcvtms x4, h5
+# CHECK-NEXT: 1 3 0.50 fcvtmu w6, h7
+# CHECK-NEXT: 1 3 0.50 fcvtmu x8, h9
+# CHECK-NEXT: 1 3 0.50 fcvtzs w10, h11
+# CHECK-NEXT: 1 3 0.50 fcvtzs x12, h13
+# CHECK-NEXT: 1 3 0.50 fcvtzu w14, h15
+# CHECK-NEXT: 1 3 0.50 fcvtzu x15, h16
+# CHECK-NEXT: 1 3 1.00 scvtf h17, w18
+# CHECK-NEXT: 1 3 1.00 scvtf h19, x20
+# CHECK-NEXT: 1 3 1.00 ucvtf h21, w22
+# CHECK-NEXT: 1 3 1.00 scvtf h23, x24
+# CHECK-NEXT: 1 3 0.50 fcvtas w25, h26
+# CHECK-NEXT: 1 3 0.50 fcvtas x27, h28
+# CHECK-NEXT: 1 3 0.50 fcvtau w29, h30
+# CHECK-NEXT: 1 3 0.50 fcvtau xzr, h0
+# CHECK-NEXT: 1 3 0.50 fcvtns w3, s31
+# CHECK-NEXT: 1 3 0.50 fcvtns xzr, s12
+# CHECK-NEXT: 1 3 0.50 fcvtnu wzr, s12
+# CHECK-NEXT: 1 3 0.50 fcvtnu x0, s0
+# CHECK-NEXT: 1 3 0.50 fcvtps wzr, s9
+# CHECK-NEXT: 1 3 0.50 fcvtps x12, s20
+# CHECK-NEXT: 1 3 0.50 fcvtpu w30, s23
+# CHECK-NEXT: 1 3 0.50 fcvtpu x29, s3
+# CHECK-NEXT: 1 3 0.50 fcvtms w2, s3
+# CHECK-NEXT: 1 3 0.50 fcvtms x4, s5
+# CHECK-NEXT: 1 3 0.50 fcvtmu w6, s7
+# CHECK-NEXT: 1 3 0.50 fcvtmu x8, s9
+# CHECK-NEXT: 1 3 0.50 fcvtzs w10, s11
+# CHECK-NEXT: 1 3 0.50 fcvtzs x12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtzu w14, s15
+# CHECK-NEXT: 1 3 0.50 fcvtzu x15, s16
+# CHECK-NEXT: 1 3 1.00 scvtf s17, w18
+# CHECK-NEXT: 1 3 1.00 scvtf s19, x20
+# CHECK-NEXT: 1 3 1.00 ucvtf s21, w22
+# CHECK-NEXT: 1 3 1.00 scvtf s23, x24
+# CHECK-NEXT: 1 3 0.50 fcvtas w25, s26
+# CHECK-NEXT: 1 3 0.50 fcvtas x27, s28
+# CHECK-NEXT: 1 3 0.50 fcvtau w29, s30
+# CHECK-NEXT: 1 3 0.50 fcvtau xzr, s0
+# CHECK-NEXT: 1 3 0.50 fcvtns w3, d31
+# CHECK-NEXT: 1 3 0.50 fcvtns xzr, d12
+# CHECK-NEXT: 1 3 0.50 fcvtnu wzr, d12
+# CHECK-NEXT: 1 3 0.50 fcvtnu x0, d0
+# CHECK-NEXT: 1 3 0.50 fcvtps wzr, d9
+# CHECK-NEXT: 1 3 0.50 fcvtps x12, d20
+# CHECK-NEXT: 1 3 0.50 fcvtpu w30, d23
+# CHECK-NEXT: 1 3 0.50 fcvtpu x29, d3
+# CHECK-NEXT: 1 3 0.50 fcvtms w2, d3
+# CHECK-NEXT: 1 3 0.50 fcvtms x4, d5
+# CHECK-NEXT: 1 3 0.50 fcvtmu w6, d7
+# CHECK-NEXT: 1 3 0.50 fcvtmu x8, d9
+# CHECK-NEXT: 1 3 0.50 fcvtzs w10, d11
+# CHECK-NEXT: 1 3 0.50 fcvtzs x12, d13
+# CHECK-NEXT: 1 3 0.50 fcvtzu w14, d15
+# CHECK-NEXT: 1 3 0.50 fcvtzu x15, d16
+# CHECK-NEXT: 1 3 1.00 scvtf d17, w18
+# CHECK-NEXT: 1 3 1.00 scvtf d19, x20
+# CHECK-NEXT: 1 3 1.00 ucvtf d21, w22
+# CHECK-NEXT: 1 3 1.00 ucvtf d23, x24
+# CHECK-NEXT: 1 3 0.50 fcvtas w25, d26
+# CHECK-NEXT: 1 3 0.50 fcvtas x27, d28
+# CHECK-NEXT: 1 3 0.50 fcvtau w29, d30
+# CHECK-NEXT: 1 3 0.50 fcvtau xzr, d0
+# CHECK-NEXT: 1 3 1.00 fmov h6, w5
+# CHECK-NEXT: 1 3 1.00 fmov h16, x27
+# CHECK-NEXT: 1 2 0.50 fmov w15, h31
+# CHECK-NEXT: 1 2 0.50 fmov w3, s9
+# CHECK-NEXT: 1 3 1.00 fmov s9, w3
+# CHECK-NEXT: 1 2 0.50 fmov x21, h14
+# CHECK-NEXT: 1 2 0.50 fmov x20, d31
+# CHECK-NEXT: 1 3 1.00 fmov d1, x15
+# CHECK-NEXT: 1 2 0.50 fmov x3, v12.d[1]
+# CHECK-NEXT: 1 5 1.00 fmov v1.d[1], x19
+# CHECK-NEXT: 1 2 0.17 fmov h29, #0.50000000
+# CHECK-NEXT: 1 2 0.17 fmov s2, #0.12500000
+# CHECK-NEXT: 1 2 0.17 fmov s3, #1.00000000
+# CHECK-NEXT: 1 2 0.17 fmov d30, #16.00000000
+# CHECK-NEXT: 1 2 0.17 fmov s4, #1.06250000
+# CHECK-NEXT: 1 2 0.17 fmov d10, #1.93750000
+# CHECK-NEXT: 1 2 0.17 fmov s12, #-1.00000000
+# CHECK-NEXT: 1 2 0.17 fmov d16, #8.50000000
+# CHECK-NEXT: 1 5 0.25 * ldr w3, #0
+# CHECK-NEXT: 1 5 0.25 * ldr x29, #4
+# CHECK-NEXT: 1 5 0.25 * ldrsw xzr, #-4
+# CHECK-NEXT: 1 7 0.25 * ldr s0, #8
+# CHECK-NEXT: 1 7 0.25 * ldr d0, #1048572
+# CHECK-NEXT: 1 7 0.25 * ldr q0, #-1048576
+# CHECK-NEXT: 1 5 0.25 U prfm pldl1strm, #0
+# CHECK-NEXT: 1 5 0.25 U prfm #25, #0
+# CHECK-NEXT: 2 5 0.50 * * U stxrb w18, w8, [sp]
+# CHECK-NEXT: 2 5 0.50 * * U stxrh w24, w15, [x16]
+# CHECK-NEXT: 2 5 0.50 * * U stxr w5, w6, [x17]
+# CHECK-NEXT: 2 5 0.50 * * U stxr w1, x10, [x21]
+# CHECK-NEXT: 1 4 0.25 * * U ldxrb w30, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U ldxrh w17, [x4]
+# CHECK-NEXT: 1 4 0.25 * * U ldxr w22, [sp]
+# CHECK-NEXT: 1 4 0.25 * * U ldxr x11, [x29]
+# CHECK-NEXT: 2 5 0.50 * * U stxp w12, w11, w10, [sp]
+# CHECK-NEXT: 2 5 0.50 * * U stxp wzr, x27, x9, [x12]
+# CHECK-NEXT: 2 4 0.25 * * U ldxp w0, wzr, [sp]
+# CHECK-NEXT: 2 4 0.25 * * U ldxp x17, x0, [x18]
+# CHECK-NEXT: 2 5 0.50 * * U stlxrb w12, w22, [x0]
+# CHECK-NEXT: 2 5 0.50 * * U stlxrh w10, w1, [x1]
+# CHECK-NEXT: 2 5 0.50 * * U stlxr w9, w2, [x2]
+# CHECK-NEXT: 2 5 0.50 * * U stlxr w9, x3, [sp]
+# CHECK-NEXT: 1 4 0.25 * * U ldaxrb w8, [x4]
+# CHECK-NEXT: 1 4 0.25 * * U ldaxrh w7, [x5]
+# CHECK-NEXT: 1 4 0.25 * * U ldaxr w6, [sp]
+# CHECK-NEXT: 1 4 0.25 * * U ldaxr x5, [x6]
+# CHECK-NEXT: 2 5 0.50 * * U stlxp w4, w5, w6, [sp]
+# CHECK-NEXT: 2 5 0.50 * * U stlxp wzr, x6, x7, [x1]
+# CHECK-NEXT: 2 4 0.25 * * U ldaxp w5, w18, [sp]
+# CHECK-NEXT: 2 4 0.25 * * U ldaxp x6, x19, [x22]
+# CHECK-NEXT: 1 1 0.50 * U stlrb w24, [sp]
+# CHECK-NEXT: 1 1 0.50 * U stlrh w25, [x30]
+# CHECK-NEXT: 1 1 0.50 * U stlr w26, [x29]
+# CHECK-NEXT: 1 1 0.50 * U stlr x27, [x28]
+# CHECK-NEXT: 1 4 0.25 * U ldarb w16, [x21]
+# CHECK-NEXT: 1 4 0.25 * U ldarb w23, [sp]
+# CHECK-NEXT: 1 4 0.25 * U ldarh w22, [x30]
+# CHECK-NEXT: 1 4 0.25 * U ldar wzr, [x29]
+# CHECK-NEXT: 1 4 0.25 * U ldar x21, [x28]
+# CHECK-NEXT: 1 1 0.50 * sturb w9, [sp]
+# CHECK-NEXT: 1 1 0.50 * sturh wzr, [x12, #255]
+# CHECK-NEXT: 1 1 0.50 * stur w16, [x0, #-256]
+# CHECK-NEXT: 1 1 0.50 * stur x28, [x14, #1]
+# CHECK-NEXT: 1 4 0.25 * ldurb w1, [x20, #255]
+# CHECK-NEXT: 1 4 0.25 * ldurh w20, [x1, #255]
+# CHECK-NEXT: 1 4 0.25 * ldur w12, [sp, #255]
+# CHECK-NEXT: 1 4 0.25 * ldur xzr, [x12, #255]
+# CHECK-NEXT: 1 4 0.25 * ldursb x9, [x7, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldursh x17, [x19, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldursw x20, [x15, #-256]
+# CHECK-NEXT: 1 4 0.25 U prfum pldl2keep, [sp, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldursb w19, [x1, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldursh w15, [x21, #-256]
+# CHECK-NEXT: 1 2 0.50 * stur b0, [sp, #1]
+# CHECK-NEXT: 1 2 0.50 * stur h12, [x12, #-1]
+# CHECK-NEXT: 1 2 0.50 * stur s15, [x0, #255]
+# CHECK-NEXT: 1 2 0.50 * stur d31, [x5, #25]
+# CHECK-NEXT: 1 2 0.50 * stur q9, [x5]
+# CHECK-NEXT: 1 6 0.25 * ldur b3, [sp]
+# CHECK-NEXT: 1 6 0.25 * ldur h5, [x4, #-256]
+# CHECK-NEXT: 1 6 0.25 * ldur s7, [x12, #-1]
+# CHECK-NEXT: 1 6 0.25 * ldur d11, [x19, #4]
+# CHECK-NEXT: 1 6 0.25 * ldur q13, [x1, #2]
+# CHECK-NEXT: 2 1 0.50 * strb w9, [x2], #255
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3], #1
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3], #-256
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2], #255
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2], #1
+# CHECK-NEXT: 2 1 0.50 * strh w10, [x3], #-256
+# CHECK-NEXT: 2 1 0.50 * str w19, [sp], #255
+# CHECK-NEXT: 2 1 0.50 * str w20, [x30], #1
+# CHECK-NEXT: 2 1 0.50 * str w21, [x12], #-256
+# CHECK-NEXT: 2 1 0.50 * str xzr, [x9], #255
+# CHECK-NEXT: 2 1 0.50 * str x2, [x3], #1
+# CHECK-NEXT: 2 1 0.50 * str x19, [x12], #-256
+# CHECK-NEXT: 2 4 0.25 * ldrb w9, [x2], #255
+# CHECK-NEXT: 2 4 0.25 * ldrb w10, [x3], #1
+# CHECK-NEXT: 2 4 0.25 * ldrb w10, [x3], #-256
+# CHECK-NEXT: 2 4 0.25 * ldrh w9, [x2], #255
+# CHECK-NEXT: 2 4 0.25 * ldrh w9, [x2], #1
+# CHECK-NEXT: 2 4 0.25 * ldrh w10, [x3], #-256
+# CHECK-NEXT: 2 4 0.25 * ldr w19, [sp], #255
+# CHECK-NEXT: 2 4 0.25 * ldr w20, [x30], #1
+# CHECK-NEXT: 2 4 0.25 * ldr w21, [x12], #-256
+# CHECK-NEXT: 2 4 0.25 * ldr xzr, [x9], #255
+# CHECK-NEXT: 2 4 0.25 * ldr x2, [x3], #1
+# CHECK-NEXT: 2 4 0.25 * ldr x19, [x12], #-256
+# CHECK-NEXT: 2 4 0.25 * ldrsb xzr, [x9], #255
+# CHECK-NEXT: 2 4 0.25 * ldrsb x2, [x3], #1
+# CHECK-NEXT: 2 4 0.25 * ldrsb x19, [x12], #-256
+# CHECK-NEXT: 2 4 0.25 * ldrsh xzr, [x9], #255
+# CHECK-NEXT: 2 4 0.25 * ldrsh x2, [x3], #1
+# CHECK-NEXT: 2 4 0.25 * ldrsh x19, [x12], #-256
+# CHECK-NEXT: 2 4 0.25 * ldrsw xzr, [x9], #255
+# CHECK-NEXT: 2 4 0.25 * ldrsw x2, [x3], #1
+# CHECK-NEXT: 2 4 0.25 * ldrsw x19, [x12], #-256
+# CHECK-NEXT: 2 4 0.25 * ldrsb wzr, [x9], #255
+# CHECK-NEXT: 2 4 0.25 * ldrsb w2, [x3], #1
+# CHECK-NEXT: 2 4 0.25 * ldrsb w19, [x12], #-256
+# CHECK-NEXT: 2 4 0.25 * ldrsh wzr, [x9], #255
+# CHECK-NEXT: 2 4 0.25 * ldrsh w2, [x3], #1
+# CHECK-NEXT: 2 4 0.25 * ldrsh w19, [x12], #-256
+# CHECK-NEXT: 2 2 0.50 * str b0, [x0], #255
+# CHECK-NEXT: 2 2 0.50 * str b3, [x3], #1
+# CHECK-NEXT: 2 2 0.50 * str b5, [sp], #-256
+# CHECK-NEXT: 2 2 0.50 * str h10, [x10], #255
+# CHECK-NEXT: 2 2 0.50 * str h13, [x23], #1
+# CHECK-NEXT: 2 2 0.50 * str h15, [sp], #-256
+# CHECK-NEXT: 2 2 0.50 * str s20, [x20], #255
+# CHECK-NEXT: 2 2 0.50 * str s23, [x23], #1
+# CHECK-NEXT: 2 2 0.50 * str s25, [x0], #-256
+# CHECK-NEXT: 2 2 0.50 * str d20, [x20], #255
+# CHECK-NEXT: 2 2 0.50 * str d23, [x23], #1
+# CHECK-NEXT: 2 2 0.50 * str d25, [x0], #-256
+# CHECK-NEXT: 2 6 0.25 * ldr b0, [x0], #255
+# CHECK-NEXT: 2 6 0.25 * ldr b3, [x3], #1
+# CHECK-NEXT: 2 6 0.25 * ldr b5, [sp], #-256
+# CHECK-NEXT: 2 6 0.25 * ldr h10, [x10], #255
+# CHECK-NEXT: 2 6 0.25 * ldr h13, [x23], #1
+# CHECK-NEXT: 2 6 0.25 * ldr h15, [sp], #-256
+# CHECK-NEXT: 2 6 0.25 * ldr s20, [x20], #255
+# CHECK-NEXT: 2 6 0.25 * ldr s23, [x23], #1
+# CHECK-NEXT: 2 6 0.25 * ldr s25, [x0], #-256
+# CHECK-NEXT: 2 6 0.25 * ldr d20, [x20], #255
+# CHECK-NEXT: 2 6 0.25 * ldr d23, [x23], #1
+# CHECK-NEXT: 2 6 0.25 * ldr d25, [x0], #-256
+# CHECK-NEXT: 2 6 0.25 * ldr q20, [x1], #255
+# CHECK-NEXT: 2 6 0.25 * ldr q23, [x9], #1
+# CHECK-NEXT: 2 6 0.25 * ldr q25, [x20], #-256
+# CHECK-NEXT: 2 2 0.50 * str q10, [x1], #255
+# CHECK-NEXT: 2 2 0.50 * str q22, [sp], #1
+# CHECK-NEXT: 2 2 0.50 * str q21, [x20], #-256
+# CHECK-NEXT: 2 4 0.25 * ldr x3, [x4, #0]!
+# CHECK-NEXT: 2 1 0.50 * strb w9, [x2, #255]!
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3, #1]!
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3, #-256]!
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2, #255]!
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2, #1]!
+# CHECK-NEXT: 2 1 0.50 * strh w10, [x3, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str w19, [sp, #255]!
+# CHECK-NEXT: 2 1 0.50 * str w20, [x30, #1]!
+# CHECK-NEXT: 2 1 0.50 * str w21, [x12, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str xzr, [x9, #255]!
+# CHECK-NEXT: 2 1 0.50 * str x2, [x3, #1]!
+# CHECK-NEXT: 2 1 0.50 * str x19, [x12, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldrb w9, [x2, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldrb w10, [x3, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldrb w10, [x3, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldrh w9, [x2, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldrh w9, [x2, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldrh w10, [x3, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldr w19, [sp, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldr w20, [x30, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldr w21, [x12, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldr xzr, [x9, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldr x2, [x3, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldr x19, [x12, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldrsb xzr, [x9, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldrsb x2, [x3, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldrsb x19, [x12, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldrsh xzr, [x9, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldrsh x2, [x3, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldrsh x19, [x12, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldrsw xzr, [x9, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldrsw x2, [x3, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldrsw x19, [x12, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldrsb wzr, [x9, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldrsb w2, [x3, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldrsb w19, [x12, #-256]!
+# CHECK-NEXT: 2 4 0.25 * ldrsh wzr, [x9, #255]!
+# CHECK-NEXT: 2 4 0.25 * ldrsh w2, [x3, #1]!
+# CHECK-NEXT: 2 4 0.25 * ldrsh w19, [x12, #-256]!
+# CHECK-NEXT: 2 2 0.50 * str b0, [x0, #255]!
+# CHECK-NEXT: 2 2 0.50 * str b3, [x3, #1]!
+# CHECK-NEXT: 2 2 0.50 * str b5, [sp, #-256]!
+# CHECK-NEXT: 2 2 0.50 * str h10, [x10, #255]!
+# CHECK-NEXT: 2 2 0.50 * str h13, [x23, #1]!
+# CHECK-NEXT: 2 2 0.50 * str h15, [sp, #-256]!
+# CHECK-NEXT: 2 2 0.50 * str s20, [x20, #255]!
+# CHECK-NEXT: 2 2 0.50 * str s23, [x23, #1]!
+# CHECK-NEXT: 2 2 0.50 * str s25, [x0, #-256]!
+# CHECK-NEXT: 2 2 0.50 * str d20, [x20, #255]!
+# CHECK-NEXT: 2 2 0.50 * str d23, [x23, #1]!
+# CHECK-NEXT: 2 2 0.50 * str d25, [x0, #-256]!
+# CHECK-NEXT: 2 6 0.25 * ldr b0, [x0, #255]!
+# CHECK-NEXT: 2 6 0.25 * ldr b3, [x3, #1]!
+# CHECK-NEXT: 2 6 0.25 * ldr b5, [sp, #-256]!
+# CHECK-NEXT: 2 6 0.25 * ldr h10, [x10, #255]!
+# CHECK-NEXT: 2 6 0.25 * ldr h13, [x23, #1]!
+# CHECK-NEXT: 2 6 0.25 * ldr h15, [sp, #-256]!
+# CHECK-NEXT: 2 6 0.25 * ldr s20, [x20, #255]!
+# CHECK-NEXT: 2 6 0.25 * ldr s23, [x23, #1]!
+# CHECK-NEXT: 2 6 0.25 * ldr s25, [x0, #-256]!
+# CHECK-NEXT: 2 6 0.25 * ldr d20, [x20, #255]!
+# CHECK-NEXT: 2 6 0.25 * ldr d23, [x23, #1]!
+# CHECK-NEXT: 2 6 0.25 * ldr d25, [x0, #-256]!
+# CHECK-NEXT: 2 6 0.25 * ldr q20, [x1, #255]!
+# CHECK-NEXT: 2 6 0.25 * ldr q23, [x9, #1]!
+# CHECK-NEXT: 2 6 0.25 * ldr q25, [x20, #-256]!
+# CHECK-NEXT: 2 2 0.50 * str q10, [x1, #255]!
+# CHECK-NEXT: 2 2 0.50 * str q22, [sp, #1]!
+# CHECK-NEXT: 2 2 0.50 * str q21, [x20, #-256]!
+# CHECK-NEXT: 1 1 0.50 * sttrb w9, [sp]
+# CHECK-NEXT: 1 1 0.50 * sttrh wzr, [x12, #255]
+# CHECK-NEXT: 1 1 0.50 * sttr w16, [x0, #-256]
+# CHECK-NEXT: 1 1 0.50 * sttr x28, [x14, #1]
+# CHECK-NEXT: 1 4 0.25 * ldtrb w1, [x20, #255]
+# CHECK-NEXT: 1 4 0.25 * ldtrh w20, [x1, #255]
+# CHECK-NEXT: 1 4 0.25 * ldtr w12, [sp, #255]
+# CHECK-NEXT: 1 4 0.25 * ldtr xzr, [x12, #255]
+# CHECK-NEXT: 1 4 0.25 * ldtrsb x9, [x7, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldtrsh x17, [x19, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldtrsw x20, [x15, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldtrsb w19, [x1, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldtrsh w15, [x21, #-256]
+# CHECK-NEXT: 1 4 0.25 * ldr x4, [x29]
+# CHECK-NEXT: 1 4 0.25 * ldr x30, [x12, #32760]
+# CHECK-NEXT: 1 4 0.25 * ldr x20, [sp, #8]
+# CHECK-NEXT: 1 4 0.25 * ldr xzr, [sp]
+# CHECK-NEXT: 1 4 0.25 * ldr w2, [sp]
+# CHECK-NEXT: 1 4 0.25 * ldr w17, [sp, #16380]
+# CHECK-NEXT: 1 4 0.25 * ldr w13, [x2, #4]
+# CHECK-NEXT: 1 4 0.25 * ldrsw x2, [x5, #4]
+# CHECK-NEXT: 1 4 0.25 * ldrsw x23, [sp, #16380]
+# CHECK-NEXT: 1 4 0.25 * ldrsw x21, [x25, x7]
+# CHECK-NEXT: 1 4 0.25 * ldrh w2, [x4]
+# CHECK-NEXT: 1 4 0.25 * ldrsh w23, [x6, #8190]
+# CHECK-NEXT: 1 4 0.25 * ldrsh wzr, [sp, #2]
+# CHECK-NEXT: 1 4 0.25 * ldrsh x29, [x2, #2]
+# CHECK-NEXT: 1 4 0.25 * ldrsh x25, [x8, w13, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrb w26, [x3, #121]
+# CHECK-NEXT: 1 4 0.25 * ldrb w12, [x2]
+# CHECK-NEXT: 1 4 0.25 * ldrsb w27, [sp, #4095]
+# CHECK-NEXT: 1 4 0.25 * ldrsb xzr, [x15]
+# CHECK-NEXT: 1 4 0.25 * ldrsb x12, [x28, x27]
+# CHECK-NEXT: 1 1 0.50 * str x30, [sp]
+# CHECK-NEXT: 1 1 0.50 * str w20, [x4, #16380]
+# CHECK-NEXT: 1 2 0.50 * str b5, [x11]
+# CHECK-NEXT: 1 2 0.50 * str h23, [x15]
+# CHECK-NEXT: 1 2 0.50 * str s25, [x19]
+# CHECK-NEXT: 1 2 0.50 * str d15, [x2]
+# CHECK-NEXT: 1 1 0.50 * strh w17, [sp, #8190]
+# CHECK-NEXT: 1 1 0.50 * strb w23, [x3, #4095]
+# CHECK-NEXT: 1 1 0.50 * strb wzr, [x2]
+# CHECK-NEXT: 1 6 0.25 * ldr b31, [sp, #4095]
+# CHECK-NEXT: 1 6 0.25 * ldr h20, [x2, #8190]
+# CHECK-NEXT: 1 6 0.25 * ldr s10, [x19, #16380]
+# CHECK-NEXT: 1 6 0.25 * ldr d3, [x10, #32760]
+# CHECK-NEXT: 1 2 0.50 * str q12, [sp, #65520]
+# CHECK-NEXT: 1 6 0.25 * ldr q14, [x6, #4624]
+# CHECK-NEXT: 1 4 0.25 * ldrb w3, [sp, x5]
+# CHECK-NEXT: 1 4 0.25 * ldrb w9, [x27, x6]
+# CHECK-NEXT: 1 4 0.25 * ldrsb w10, [x30, x7]
+# CHECK-NEXT: 1 4 0.25 * ldrb w11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 1 0.50 * strb w12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 1 0.50 * strb w5, [x26, w7, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrb w14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrsb w15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrb w17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrsb x18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrsh w3, [sp, x5]
+# CHECK-NEXT: 1 4 0.25 * ldrsh w9, [x27, x6]
+# CHECK-NEXT: 1 4 0.25 * ldrh w10, [x30, x7, lsl #1]
+# CHECK-NEXT: 1 1 0.50 * strh w11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 4 0.25 * ldrh w12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 4 0.25 * ldrsh x13, [x27, x5, sxtx #1]
+# CHECK-NEXT: 1 4 0.25 * ldrh w14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrh w15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrsh w16, [x24, w8, uxtw #1]
+# CHECK-NEXT: 1 4 0.25 * ldrh w17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrh w18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 1 0.50 * strh w19, [x21, wzr, sxtw #1]
+# CHECK-NEXT: 1 6 0.25 * ldr b25, [x21, w8, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ldr b8, [x30, x10]
+# CHECK-NEXT: 1 2 0.50 * str b14, [x13, x25]
+# CHECK-NEXT: 1 2 0.50 * str b30, [x16, w26, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ldr h3, [sp, x5]
+# CHECK-NEXT: 1 6 0.25 * ldr h9, [x27, x6]
+# CHECK-NEXT: 1 6 0.25 * ldr h10, [x30, x7, lsl #1]
+# CHECK-NEXT: 1 2 0.50 * str h11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 2 0.50 * str h12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 2 0.50 * str h13, [x27, x5, sxtx #1]
+# CHECK-NEXT: 1 6 0.25 * ldr h14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ldr h15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ldr h16, [x24, w8, uxtw #1]
+# CHECK-NEXT: 1 6 0.25 * ldr h17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 2 0.50 * str h18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 6 0.25 * ldr h19, [x21, wzr, sxtw #1]
+# CHECK-NEXT: 1 6 0.25 * ldr s12, [x30, w5, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ldr d24, [x26, w7, uxtw]
+# CHECK-NEXT: 1 2 0.50 * str s20, [x24, w10, uxtw]
+# CHECK-NEXT: 1 2 0.50 * str d5, [x26, x6]
+# CHECK-NEXT: 1 4 0.25 * ldr w3, [sp, x5]
+# CHECK-NEXT: 1 6 0.25 * ldr s9, [x27, x6]
+# CHECK-NEXT: 1 4 0.25 * ldr w10, [x30, x7, lsl #2]
+# CHECK-NEXT: 1 4 0.25 * ldr w11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 2 0.50 * str s12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 1 0.50 * str w13, [x27, x5, sxtx #2]
+# CHECK-NEXT: 1 1 0.50 * str w14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldr w15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldr w16, [x24, w8, uxtw #2]
+# CHECK-NEXT: 1 4 0.25 * ldrsw x17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 4 0.25 * ldr w18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 4 0.25 * ldrsw x19, [x21, wzr, sxtw #2]
+# CHECK-NEXT: 1 4 0.25 * ldr x3, [sp, x5]
+# CHECK-NEXT: 1 1 0.50 * str x9, [x27, x6]
+# CHECK-NEXT: 1 6 0.25 * ldr d10, [x30, x7, lsl #3]
+# CHECK-NEXT: 1 1 0.50 * str x11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 4 0.25 * ldr x12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 4 0.25 * ldr x13, [x27, x5, sxtx #3]
+# CHECK-NEXT: 1 4 0.25 U prfm pldl1keep, [x26, w6, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldr x15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 1 0.50 * str x27, [x26, w24, uxtw]
+# CHECK-NEXT: 1 4 0.25 * ldr x16, [x24, w8, uxtw #3]
+# CHECK-NEXT: 1 4 0.25 * ldr x17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 4 0.25 * ldr x18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 2 0.50 * str d19, [x21, wzr, sxtw #3]
+# CHECK-NEXT: 1 6 0.25 * ldr q3, [sp, x5]
+# CHECK-NEXT: 1 6 0.25 * ldr q9, [x27, x6]
+# CHECK-NEXT: 1 7 0.25 * ldr q10, [x30, x7, lsl #4]
+# CHECK-NEXT: 1 2 0.50 * str q11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 2 0.50 * str q12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 2 0.50 * str q13, [x27, x5, sxtx #4]
+# CHECK-NEXT: 1 6 0.25 * ldr q14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ldr q15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 7 0.25 * ldr q16, [x24, w8, uxtw #4]
+# CHECK-NEXT: 1 6 0.25 * ldr q17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 2 0.50 * str q18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 7 0.25 * ldr q19, [x21, wzr, sxtw #4]
+# CHECK-NEXT: 2 4 0.25 * ldp w3, w5, [sp]
+# CHECK-NEXT: 1 1 0.50 * stp wzr, w9, [sp, #252]
+# CHECK-NEXT: 2 4 0.25 * ldp w2, wzr, [sp, #-256]
+# CHECK-NEXT: 2 4 0.25 * ldp w9, w10, [sp, #4]
+# CHECK-NEXT: 2 5 0.50 * ldpsw x9, x10, [sp, #4]
+# CHECK-NEXT: 2 5 0.50 * ldpsw x9, x10, [x2, #-256]
+# CHECK-NEXT: 2 5 0.50 * ldpsw x20, x30, [sp, #252]
+# CHECK-NEXT: 1 4 0.50 * ldp x21, x29, [x2, #504]
+# CHECK-NEXT: 1 4 0.50 * ldp x22, x23, [x3, #-512]
+# CHECK-NEXT: 1 4 0.50 * ldp x24, x25, [x4, #8]
+# CHECK-NEXT: 2 6 0.25 * ldp s29, s28, [sp, #252]
+# CHECK-NEXT: 1 2 0.50 * stp s27, s26, [sp, #-256]
+# CHECK-NEXT: 2 6 0.25 * ldp s1, s2, [x3, #44]
+# CHECK-NEXT: 1 2 0.50 * stp d3, d5, [x9, #504]
+# CHECK-NEXT: 1 2 0.50 * stp d7, d11, [x10, #-512]
+# CHECK-NEXT: 1 1 0.50 * stnp x20, x16, [x8]
+# CHECK-NEXT: 1 1 0.50 * stp x3, x6, [x16]
+# CHECK-NEXT: 2 6 0.25 * ldp d2, d3, [x30, #-8]
+# CHECK-NEXT: 1 2 1.00 * stp q3, q5, [sp]
+# CHECK-NEXT: 1 2 1.00 * stp q17, q19, [sp, #1008]
+# CHECK-NEXT: 2 6 0.25 * ldp q23, q29, [x1, #-1024]
+# CHECK-NEXT: 3 4 0.25 * ldp w3, w5, [sp], #0
+# CHECK-NEXT: 2 1 0.50 * stp wzr, w9, [sp], #252
+# CHECK-NEXT: 3 4 0.25 * ldp w2, wzr, [sp], #-256
+# CHECK-NEXT: 3 4 0.25 * ldp w9, w10, [sp], #4
+# CHECK-NEXT: 3 5 0.50 * ldpsw x9, x10, [sp], #4
+# CHECK-NEXT: 3 5 0.50 * ldpsw x9, x10, [x2], #-256
+# CHECK-NEXT: 3 5 0.50 * ldpsw x20, x30, [sp], #252
+# CHECK-NEXT: 1 4 0.50 * ldp x21, x29, [x2], #504
+# CHECK-NEXT: 1 4 0.50 * ldp x22, x23, [x3], #-512
+# CHECK-NEXT: 1 4 0.50 * ldp x24, x25, [x4], #8
+# CHECK-NEXT: 3 6 0.25 * ldp s29, s28, [sp], #252
+# CHECK-NEXT: 2 2 0.50 * stp s27, s26, [sp], #-256
+# CHECK-NEXT: 3 6 0.25 * ldp s1, s2, [x3], #44
+# CHECK-NEXT: 2 2 0.50 * stp d3, d5, [x9], #504
+# CHECK-NEXT: 2 2 0.50 * stp d7, d11, [x10], #-512
+# CHECK-NEXT: 3 6 0.25 * ldp d2, d3, [x30], #-8
+# CHECK-NEXT: 1 2 1.00 * stp q3, q5, [sp], #0
+# CHECK-NEXT: 1 2 1.00 * stp q17, q19, [sp], #1008
+# CHECK-NEXT: 3 6 0.50 * ldp q23, q29, [x1], #-1024
+# CHECK-NEXT: 3 4 0.25 * ldp w3, w5, [sp, #0]!
+# CHECK-NEXT: 2 1 0.50 * stp wzr, w9, [sp, #252]!
+# CHECK-NEXT: 3 4 0.25 * ldp w2, wzr, [sp, #-256]!
+# CHECK-NEXT: 3 4 0.25 * ldp w9, w10, [sp, #4]!
+# CHECK-NEXT: 3 5 0.50 * ldpsw x9, x10, [sp, #4]!
+# CHECK-NEXT: 3 5 0.50 * ldpsw x9, x10, [x2, #-256]!
+# CHECK-NEXT: 3 5 0.50 * ldpsw x20, x30, [sp, #252]!
+# CHECK-NEXT: 1 4 0.50 * ldp x21, x29, [x2, #504]!
+# CHECK-NEXT: 1 4 0.50 * ldp x22, x23, [x3, #-512]!
+# CHECK-NEXT: 1 4 0.50 * ldp x24, x25, [x4, #8]!
+# CHECK-NEXT: 3 6 0.25 * ldp s29, s28, [sp, #252]!
+# CHECK-NEXT: 2 2 0.50 * stp s27, s26, [sp, #-256]!
+# CHECK-NEXT: 3 6 0.25 * ldp s1, s2, [x3, #44]!
+# CHECK-NEXT: 2 2 0.50 * stp d3, d5, [x9, #504]!
+# CHECK-NEXT: 2 2 0.50 * stp d7, d11, [x10, #-512]!
+# CHECK-NEXT: 3 6 0.25 * ldp d2, d3, [x30, #-8]!
+# CHECK-NEXT: 1 2 1.00 * stp q3, q5, [sp, #0]!
+# CHECK-NEXT: 1 2 1.00 * stp q17, q19, [sp, #1008]!
+# CHECK-NEXT: 3 6 0.50 * ldp q23, q29, [x1, #-1024]!
+# CHECK-NEXT: 2 4 0.25 * ldnp w3, w5, [sp]
+# CHECK-NEXT: 1 1 0.50 * stnp wzr, w9, [sp, #252]
+# CHECK-NEXT: 2 4 0.25 * ldnp w2, wzr, [sp, #-256]
+# CHECK-NEXT: 2 4 0.25 * ldnp w9, w10, [sp, #4]
+# CHECK-NEXT: 1 4 0.50 * ldnp x21, x29, [x2, #504]
+# CHECK-NEXT: 1 4 0.50 * ldnp x22, x23, [x3, #-512]
+# CHECK-NEXT: 1 4 0.50 * ldnp x24, x25, [x4, #8]
+# CHECK-NEXT: 2 6 0.25 * ldnp s29, s28, [sp, #252]
+# CHECK-NEXT: 1 2 0.50 * stnp s27, s26, [sp, #-256]
+# CHECK-NEXT: 2 6 0.25 * ldnp s1, s2, [x3, #44]
+# CHECK-NEXT: 1 2 0.50 * stnp d3, d5, [x9, #504]
+# CHECK-NEXT: 1 2 0.50 * stnp d7, d11, [x10, #-512]
+# CHECK-NEXT: 2 6 0.25 * ldnp d2, d3, [x30, #-8]
+# CHECK-NEXT: 1 2 1.00 * stnp q3, q5, [sp]
+# CHECK-NEXT: 1 2 1.00 * stnp q17, q19, [sp, #1008]
+# CHECK-NEXT: 2 6 0.25 * ldnp q23, q29, [x1, #-1024]
+# CHECK-NEXT: 1 1 0.13 and wsp, w16, #0xe00
+# CHECK-NEXT: 1 1 0.13 and x2, x22, #0x1e00
+# CHECK-NEXT: 1 1 0.25 ands w14, w8, #0x70
+# CHECK-NEXT: 1 1 0.25 ands x4, x10, #0x60
+# CHECK-NEXT: 1 1 0.13 eor wsp, w4, #0xe00
+# CHECK-NEXT: 1 1 0.13 eor x27, x25, #0x1e00
+# CHECK-NEXT: 1 1 0.13 mov w3, #983055
+# CHECK-NEXT: 1 1 0.13 mov x10, #-6148914691236517206
+# CHECK-NEXT: 1 1 0.13 and w12, w23, w21
+# CHECK-NEXT: 1 1 0.13 and w16, w15, w1, lsl #1
+# CHECK-NEXT: 1 1 0.13 and w9, w4, w10, lsl #31
+# CHECK-NEXT: 1 1 0.13 and w3, w30, w11
+# CHECK-NEXT: 1 1 0.13 and x3, x5, x7, lsl #63
+# CHECK-NEXT: 1 1 0.13 and x5, x14, x19, asr #4
+# CHECK-NEXT: 1 1 0.13 and w3, w17, w19, ror #31
+# CHECK-NEXT: 1 1 0.13 and w0, w2, wzr, lsr #17
+# CHECK-NEXT: 1 1 0.13 and w3, w30, w11, asr #2
+# CHECK-NEXT: 1 1 0.13 and xzr, x4, x26
+# CHECK-NEXT: 1 1 0.13 and w3, wzr, w20, ror #2
+# CHECK-NEXT: 1 1 0.13 and x7, x20, xzr, asr #63
+# CHECK-NEXT: 1 1 0.13 bic x13, x20, x14, lsl #47
+# CHECK-NEXT: 1 1 0.13 bic w2, w7, w9
+# CHECK-NEXT: 1 1 0.13 eon w29, w4, w19
+# CHECK-NEXT: 1 1 0.13 eon x19, x12, x2
+# CHECK-NEXT: 1 1 0.13 eor w8, w27, w2
+# CHECK-NEXT: 1 1 0.13 eor x22, x16, x6
+# CHECK-NEXT: 1 1 0.13 orr w2, w7, w0, asr #31
+# CHECK-NEXT: 1 1 0.13 orr x8, x9, x10, lsl #12
+# CHECK-NEXT: 1 1 0.13 orn x3, x5, x7, asr #2
+# CHECK-NEXT: 1 1 0.13 orn w2, w5, w29
+# CHECK-NEXT: 1 1 0.25 ands w7, wzr, w9, lsl #1
+# CHECK-NEXT: 1 1 0.25 ands x3, x5, x20, ror #63
+# CHECK-NEXT: 1 1 0.25 bics w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 bics x3, xzr, x3, lsl #1
+# CHECK-NEXT: 1 1 0.25 tst w3, w7, lsl #31
+# CHECK-NEXT: 1 1 0.25 tst x2, x20, asr #2
+# CHECK-NEXT: 1 1 0.13 mov x3, x6
+# CHECK-NEXT: 1 1 0.13 mov x3, xzr
+# CHECK-NEXT: 1 1 0.13 mov wzr, w2
+# CHECK-NEXT: 1 1 0.13 mov w3, w5
+# CHECK-NEXT: 1 1 0.13 movz w2, #0, lsl #16
+# CHECK-NEXT: 1 1 0.13 mov w2, #-1235
+# CHECK-NEXT: 1 1 0.13 mov x2, #5299989643264
+# CHECK-NEXT: 1 1 0.13 mov x2, #0
+# CHECK-NEXT: 1 1 0.13 movk w3, #0
+# CHECK-NEXT: 1 1 0.13 movz x4, #0, lsl #16
+# CHECK-NEXT: 1 1 0.13 movk w5, #0, lsl #16
+# CHECK-NEXT: 1 1 0.13 movz x6, #0, lsl #32
+# CHECK-NEXT: 1 1 0.13 movk x7, #0, lsl #32
+# CHECK-NEXT: 1 1 0.13 movz x8, #0, lsl #48
+# CHECK-NEXT: 1 1 0.13 movk x9, #0, lsl #48
+# CHECK-NEXT: 1 1 0.10 U msr DAIFSet, #0
+# CHECK-NEXT: 1 1 0.13 adr x2, #1600
+# CHECK-NEXT: 1 1 0.13 adrp x21, #6553600
+# CHECK-NEXT: 1 1 0.13 adr x0, #262144
+# CHECK-NEXT: 1 2 0.33 tbz x12, #62, #0
+# CHECK-NEXT: 1 2 0.33 tbz x12, #62, #4
+# CHECK-NEXT: 1 2 0.33 tbz x12, #62, #-32768
+# CHECK-NEXT: 1 2 0.33 tbz w17, #16, test
+# CHECK-NEXT: 1 2 0.33 tbnz x12, #60, #32764
+# CHECK-NEXT: 1 2 0.33 tbnz w3, #28, test
+# CHECK-NEXT: 1 2 0.33 b #4
+# CHECK-NEXT: 1 2 0.33 b #-4
+# CHECK-NEXT: 1 2 0.33 b #134217724
+# CHECK-NEXT: 1 2 0.33 bl test
+# CHECK-NEXT: 1 2 0.33 br x20
+# CHECK-NEXT: 1 2 0.33 blr xzr
+# CHECK-NEXT: 1 2 0.33 U ret x10
+# CHECK-NEXT: 1 2 0.33 U ret
+# CHECK-NEXT: 1 2 0.33 U eret
+# CHECK-NEXT: 1 2 0.33 U drps
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: 8.67 8.67 8.67 - 34.00 34.00 42.00 42.00 42.00 42.00 74.75 74.75 149.75 149.75 228.50 99.00 106.83 94.33 106.83 94.33 106.83 94.33 120.42 126.42 9.17 15.92 15.92 9.17
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w2, w3, #4095
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w30, w29, #1, lsl #12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w13, w5, #4095, lsl #12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x5, x7, #1638
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w20, wsp, #801
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add wsp, wsp, #1104
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add wsp, w30, #4084
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x0, x24, #291
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x3, x24, #4095, lsl #12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x8, sp, #1074
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add sp, x29, #3816
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w0, wsp, #4077
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w4, w20, #546, lsl #12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub sp, sp, #288
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub wsp, w19, #16
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w13, w23, #291, lsl #12
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w2, #4095
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w20, wsp, #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x3, #1, lsl #12
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp wsp, #2342
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp sp, #20, lsl #12
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x30, #4095
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x4, sp, #3822
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w3, #291, lsl #12
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn wsp, #1365
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn sp, #1092, lsl #12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov x10, #-63432
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add wsp, wsp, w10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x25, x9, w25, uxtb
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w3, w5, w7
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add wzr, w3, w5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w20, wzr, w4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w4, w6, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w11, w13, w15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w9, w3, wzr, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w17, w29, w20, lsl #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w21, w22, w23, lsr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w24, w25, w26, lsr #18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w27, w28, w29, lsr #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w2, w3, w4, asr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w5, w6, w7, asr #21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add w8, w9, w10, asr #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x3, x5, x7
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add xzr, x3, x5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x20, xzr, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x4, x6, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x11, x13, x15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x9, x3, xzr, lsl #10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x17, x29, x20, lsl #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x21, x22, x23, lsr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x24, x25, x26, lsr #18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x27, x28, x29, lsr #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x2, x3, x4, asr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x5, x6, x7, asr #21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - add x8, x9, x10, asr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w3, w5, w7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w17, wsp, w25
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x13, x23, w8, uxtb
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w3, w5
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w20, wzr, w4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w4, w6, wzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w11, w13, w15
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w9, w3, wzr, lsl #1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w17, w29, w20, lsl #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w21, w22, w23, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w24, w25, w26, lsr #18
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w27, w28, w29, lsr #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w2, w3, w4, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w5, w6, w7, asr #21
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds w8, w9, w10, asr #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x3, x5, x7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x3, x5
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x20, xzr, x4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x4, x6, xzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x11, x13, x15
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x9, x3, xzr, lsl #10
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x17, x29, x20, lsl #3
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x21, x22, x23, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x24, x25, x26, lsr #18
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x27, x28, x29, lsr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x2, x3, x4, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x5, x6, x7, asr #21
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adds x8, x9, x10, asr #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w3, w5, w7
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub wzr, w3, w5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w4, w6, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w11, w13, w15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w9, w3, wzr, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w17, w29, w20, lsl #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w21, w22, w23, lsr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w24, w25, w26, lsr #18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w27, w28, w29, lsr #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w2, w3, w4, asr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w5, w6, w7, asr #21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w8, w9, w10, asr #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x3, x5, x7
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub xzr, x3, x5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x4, x6, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x11, x13, x15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x9, x3, xzr, lsl #10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x17, x29, x20, lsl #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x21, x22, x23, lsr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x24, x25, x26, lsr #18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x27, x28, x29, lsr #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x2, x3, x4, asr #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x5, x6, x7, asr #21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x8, x9, x10, asr #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub w13, wsp, w10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sub x16, x2, w19, uxtb
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x13, x15, x14, sxtx #1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w3, w5, w7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w3, w5
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w4, w6, wzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w11, w13, w15
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w9, w3, wzr, lsl #1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w17, w29, w20, lsl #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w21, w22, w23, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w24, w25, w26, lsr #18
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w27, w28, w29, lsr #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w2, w3, w4, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w5, w6, w7, asr #21
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs w8, w9, w10, asr #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x3, x5, x7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x3, x5
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x4, x6, xzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x11, x13, x15
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x9, x3, xzr, lsl #10
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x17, x29, x20, lsl #3
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x21, x22, x23, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x24, x25, x26, lsr #18
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x27, x28, x29, lsr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x2, x3, x4, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x5, x6, x7, asr #21
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subs x8, x9, x10, asr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn wzr, w4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w5, wzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w6, w7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w8, w9, lsl #1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w10, w11, lsl #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w12, w13, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w14, w15, lsr #21
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w16, w17, lsr #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w18, w19, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w20, w21, asr #22
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn w22, w23, asr #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x0, x3
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn xzr, x4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x5, xzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x6, x7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x8, x9, lsl #15
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x10, x11, lsl #3
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x12, x13, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x14, x15, lsr #41
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x16, x17, lsr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x18, x19, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x20, x21, asr #55
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmn x22, x23, asr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w0, w3
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp wzr, w4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w5, wzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w6, w7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w8, w9, lsl #1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w10, w11, lsl #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w12, w13, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w14, w15, lsr #21
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w18, w19, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w20, w21, asr #22
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp w22, w23, asr #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp wsp, w26
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x16, w27, uxtb
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x0, x3
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp xzr, x4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x5, xzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x6, x7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x8, x9, lsl #15
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x10, x11, lsl #3
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x12, x13, lsr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x14, x15, lsr #41
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x16, x17, lsr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x18, x19, asr #0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x20, x21, asr #55
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp x22, x23, asr #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp wzr, w0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cmp xzr, x0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov sp, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov wsp, w20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov x11, sp
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov w24, wsp
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc w29, w27, w25
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc wzr, w3, w4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc w9, wzr, w10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc w20, w0, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc x29, x27, x25
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc xzr, x3, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc x9, xzr, x10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adc x20, x0, xzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs w29, w27, w25
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs wzr, w3, w4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs w9, wzr, w10
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs w20, w0, wzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs x29, x27, x25
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs xzr, x3, x4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs x9, xzr, x10
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adcs x20, x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbc w29, w27, w25
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbc wzr, w3, w4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc w9, w10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbc w20, w0, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbc x29, x27, x25
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbc xzr, x3, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc x9, x10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbc x20, x0, xzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbcs w29, w27, w25
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbcs wzr, w3, w4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs w9, w10
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbcs w20, w0, wzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbcs x29, x27, x25
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbcs xzr, x3, x4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs x9, x10
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbcs x20, x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc w3, w12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc wzr, w9
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc w23, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc x29, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc xzr, x0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngc x0, xzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs w3, w12
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs wzr, w9
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs w23, wzr
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs x29, x30
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs xzr, x0
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ngcs x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfx x1, x2, #3, #2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr x3, x4, #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr wzr, wzr, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfx w12, w9, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ubfiz x4, x5, #52, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ubfx xzr, x4, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ubfiz x4, xzr, #1, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr x5, x6, #12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfi x4, x5, #52, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil xzr, x4, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfc x4, #1, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil x5, x6, #12, #52
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sxtb w1, w2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sxtb xzr, w3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sxth w9, w10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sxth x0, w1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sxtw x3, w30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - uxtb w1, w2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - uxth w9, w10
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ubfx x3, x30, #0, #32
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w3, w2, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w9, w10, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr x20, x21, #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w1, wzr, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr w3, w2, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr w9, w10, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr x20, x21, #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr wzr, wzr, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl w9, w10, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl x20, x21, #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl w1, wzr, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfiz x2, x3, #63, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfiz x9, x10, #5, #59
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfiz w11, w12, #31, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfiz w13, w14, #29, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfiz xzr, xzr, #10, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfx w9, w10, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr x2, x3, #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr x19, x20, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr x9, x10, #5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w9, w10, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w11, w12, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w13, w14, #29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - sbfx xzr, xzr, #10, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfi x2, x3, #63, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfi x9, x10, #5, #59
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfi w11, w12, #31, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfi w13, w14, #29, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfc xzr, #10, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil w9, w10, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil x2, x3, #63, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil x19, x20, #0, #64
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil x9, x10, #5, #59
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil w9, w10, #0, #32
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil w11, w12, #31, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil w13, w14, #29, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bfxil xzr, xzr, #10, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl x2, x3, #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl x9, x10, #5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl w11, w12, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl w13, w14, #29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ubfiz xzr, xzr, #10, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ubfx w9, w10, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr x2, x3, #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr x19, x20, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr x9, x10, #5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr w9, w10, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr w11, w12, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr w13, w14, #29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ubfx xzr, xzr, #10, #11
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - cbz w5, #4
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - cbz x5, #0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - cbnz x2, #-4
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - cbnz x26, #1048572
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - cbz wzr, #0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - cbnz xzr, #0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - cbnz w21, test
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - b.ne #4
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - b.ge #1048572
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - b.ge #-4
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp w1, #31, #0, eq
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp w3, #0, #15, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp wzr, #15, #13, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp x9, #31, #0, le
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp x3, #0, #15, gt
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp xzr, #5, #7, ne
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn w1, #31, #0, eq
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn w3, #0, #15, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn wzr, #15, #13, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn x9, #31, #0, le
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn x3, #0, #15, gt
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn xzr, #5, #7, ne
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp w1, wzr, #0, eq
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp w3, w0, #15, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp wzr, w15, #13, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp x9, xzr, #0, le
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp x3, x0, #15, gt
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmp xzr, x5, #7, ne
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn w1, wzr, #0, eq
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn w3, w0, #15, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn wzr, w15, #13, hs
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn x9, xzr, #0, le
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn x3, x0, #15, gt
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ccmn xzr, x5, #7, ne
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel w1, w0, w19, ne
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel wzr, w5, w9, eq
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel w9, wzr, w30, gt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel w1, w28, wzr, mi
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel x19, x23, x29, lt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel xzr, x3, x4, ge
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel x5, xzr, x6, hs
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csel x7, x8, xzr, lo
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc w1, w0, w19, ne
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc wzr, w5, w9, eq
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc w9, wzr, w30, gt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc w1, w28, wzr, mi
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc x19, x23, x29, lt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc xzr, x3, x4, ge
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc x5, xzr, x6, hs
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc x7, x8, xzr, lo
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinv w1, w0, w19, ne
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+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg wzr, w5, w9, eq
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg w9, wzr, w30, gt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg w1, w28, wzr, mi
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg x19, x23, x29, lt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg xzr, x3, x4, ge
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg x5, xzr, x6, hs
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg x7, x8, xzr, lo
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+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csetm w20, ne
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csetm x30, ge
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc w2, wzr, wzr, al
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinv x3, xzr, xzr, nv
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinc w3, w5, gt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinc wzr, w4, le
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cset w9, lt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinc x3, x5, gt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinc xzr, x4, le
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cset x9, lt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc w5, w6, w6, nv
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinc x1, x2, x2, al
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinv w3, w5, gt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinv wzr, w4, le
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csetm w9, lt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinv x3, x5, gt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cinv xzr, x4, le
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+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csinv x1, x0, x0, al
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+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cneg xzr, x4, le
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cneg x9, xzr, lt
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - csneg x4, x8, x8, al
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rbit w0, w7
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rbit x18, x3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rev16 w17, w1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rev16 x5, x2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rev w18, w0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rev32 x20, x1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rev x22, x2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - clz w24, w3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - clz x26, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cls w3, w5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - cls x20, x5
+# CHECK-NEXT: - - - - - - - - - - - - - - 12.00 - - - - - - - - - - - - - udiv w0, w7, w10
+# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - - - - - - - - - - - - - udiv x9, x22, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 12.00 - - - - - - - - - - - - - sdiv w12, w21, w0
+# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - - - - - - - - - - - - - sdiv x13, x2, x1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl w11, w12, w13
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl x14, x15, x16
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr w17, w18, w19
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr x20, x21, x22
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w23, w24, w25
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr x26, x27, x28
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ror w0, w1, w2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ror x3, x4, x5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl w6, w7, w8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsl x9, x10, x11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr w12, w13, w14
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - lsr x15, x16, x17
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr w18, w19, w20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - asr x21, x22, x23
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ror w24, w25, w26
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ror x27, x28, x29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32cb w30, w23, w15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32cb wzr, w12, w14
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32cb w28, w10, w11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32b w27, w12, w15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32h w3, w15, w21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32w w9, w18, w24
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32x w19, w6, x25
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32ch w25, w26, w16
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32cw w27, w12, w23
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - crc32cx w21, w28, x5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smulh x30, x29, x28
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smulh xzr, x27, x26
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umulh x30, x29, x28
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umulh x23, x30, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd w1, w3, w7, w4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd wzr, w0, w9, w11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd w13, wzr, w4, w4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd w19, w30, wzr, w29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - mul w4, w5, w6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd x1, x3, x7, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd xzr, x0, x9, x11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd x13, xzr, x4, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - madd x19, x30, xzr, x29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - mul x4, x5, x6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub w1, w3, w7, w4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub wzr, w0, w9, w11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub w13, wzr, w4, w4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub w19, w30, wzr, w29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - mneg w4, w5, w6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub x1, x3, x7, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub xzr, x0, x9, x11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub x13, xzr, x4, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - msub x19, x30, xzr, x29
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - mneg x4, x5, x6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smaddl x3, w5, w2, x9
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smaddl xzr, w10, w11, x12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smaddl x13, wzr, w14, x15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smaddl x16, w17, wzr, x18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smull x19, w20, w21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smsubl x3, w5, w2, x9
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smsubl xzr, w10, w11, x12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smsubl x13, wzr, w14, x15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smsubl x16, w17, wzr, x18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smnegl x19, w20, w21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umaddl x3, w5, w2, x9
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umaddl xzr, w10, w11, x12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umaddl x13, wzr, w14, x15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umaddl x16, w17, wzr, x18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umull x19, w20, w21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umsubl x3, w5, w2, x9
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umsubl x16, w17, wzr, x18
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umnegl x19, w20, w21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smulh x23, x22, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umulh x23, x22, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - mul x19, x20, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - mneg w21, w22, w23
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - smull x11, w13, w17
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.25 - 0.25 - 0.25 - 0.25 - - - - - - - umull x11, w13, w17
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrh w9, [x2, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrh w10, [x3, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr w19, [sp, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr w20, [x30, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr w21, [x12, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr xzr, [x9, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr x2, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr x19, [x12, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsb xzr, [x9, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsb x2, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsb x19, [x12, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsh xzr, [x9, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsh x2, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsh x19, [x12, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsw xzr, [x9, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsw x2, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsw x19, [x12, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsb wzr, [x9, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsb w2, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsb w19, [x12, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsh wzr, [x9, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsh w2, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldrsh w19, [x12, #-256]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str b0, [x0, #255]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str b3, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str b5, [sp, #-256]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str h10, [x10, #255]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str h13, [x23, #1]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str h15, [sp, #-256]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str s20, [x20, #255]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str s23, [x23, #1]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str s25, [x0, #-256]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str d20, [x20, #255]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str d23, [x23, #1]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str d25, [x0, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr b0, [x0, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr b3, [x3, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr b5, [sp, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr h10, [x10, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr h13, [x23, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr h15, [sp, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr s20, [x20, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr s23, [x23, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr s25, [x0, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr d20, [x20, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr d23, [x23, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr d25, [x0, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr q20, [x1, #255]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr q23, [x9, #1]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldr q25, [x20, #-256]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str q10, [x1, #255]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str q22, [sp, #1]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - str q21, [x20, #-256]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - sttrb w9, [sp]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - sttrh wzr, [x12, #255]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - sttr w16, [x0, #-256]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - sttr x28, [x14, #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtrb w1, [x20, #255]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtrh w20, [x1, #255]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtr w12, [sp, #255]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtr xzr, [x12, #255]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtrsb x9, [x7, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtrsh x17, [x19, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtrsw x20, [x15, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtrsb w19, [x1, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldtrsh w15, [x21, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x4, [x29]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x30, [x12, #32760]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x20, [sp, #8]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr xzr, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w2, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w17, [sp, #16380]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w13, [x2, #4]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsw x2, [x5, #4]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsw x23, [sp, #16380]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsw x21, [x25, x7]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrh w2, [x4]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh w23, [x6, #8190]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh wzr, [sp, #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh x29, [x2, #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh x25, [x8, w13, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrb w26, [x3, #121]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrb w12, [x2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsb w27, [sp, #4095]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsb xzr, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsb x12, [x28, x27]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - str x30, [sp]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - str w20, [x4, #16380]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str b5, [x11]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str h23, [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str s25, [x19]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str d15, [x2]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - strh w17, [sp, #8190]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - strb w23, [x3, #4095]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - strb wzr, [x2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr b31, [sp, #4095]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h20, [x2, #8190]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr s10, [x19, #16380]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr d3, [x10, #32760]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str q12, [sp, #65520]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr q14, [x6, #4624]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrb w3, [sp, x5]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrb w9, [x27, x6]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsb w10, [x30, x7]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrb w11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - strb w12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - strb w5, [x26, w7, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrb w14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsb w15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrb w17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsb x18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh w3, [sp, x5]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh w9, [x27, x6]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrh w10, [x30, x7, lsl #1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - strh w11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrh w12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh x13, [x27, x5, sxtx #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrh w14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrh w15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsh w16, [x24, w8, uxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrh w17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrh w18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - strh w19, [x21, wzr, sxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr b25, [x21, w8, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr b8, [x30, x10]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str b14, [x13, x25]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str b30, [x16, w26, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h3, [sp, x5]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h9, [x27, x6]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h10, [x30, x7, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str h11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str h12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str h13, [x27, x5, sxtx #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h16, [x24, w8, uxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str h18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr h19, [x21, wzr, sxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr s12, [x30, w5, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr d24, [x26, w7, uxtw]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str s20, [x24, w10, uxtw]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str d5, [x26, x6]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w3, [sp, x5]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr s9, [x27, x6]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w10, [x30, x7, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str s12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - str w13, [x27, x5, sxtx #2]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - str w14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w16, [x24, w8, uxtw #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsw x17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr w18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldrsw x19, [x21, wzr, sxtw #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x3, [sp, x5]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - str x9, [x27, x6]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr d10, [x30, x7, lsl #3]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - str x11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x13, [x27, x5, sxtx #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - prfm pldl1keep, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - str x27, [x26, w24, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x16, [x24, w8, uxtw #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr x18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str d19, [x21, wzr, sxtw #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr q3, [sp, x5]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr q9, [x27, x6]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr q10, [x30, x7, lsl #4]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str q11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str q12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 - - - - str q13, [x27, x5, sxtx #4]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr q14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr q15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr q16, [x24, w8, uxtw #4]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldr q17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str q18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldr q19, [x21, wzr, sxtw #4]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldp w3, w5, [sp]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stp wzr, w9, [sp, #252]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldp w2, wzr, [sp, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldp w9, w10, [sp, #4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldpsw x9, x10, [sp, #4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldpsw x9, x10, [x2, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldpsw x20, x30, [sp, #252]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ldp x21, x29, [x2, #504]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ldp x22, x23, [x3, #-512]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ldp x24, x25, [x4, #8]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldp s29, s28, [sp, #252]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stp s27, s26, [sp, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldp s1, s2, [x3, #44]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stp d3, d5, [x9, #504]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stp d7, d11, [x10, #-512]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stnp x20, x16, [x8]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stp x3, x6, [x16]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldp d2, d3, [x30, #-8]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stp q3, q5, [sp]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stp q17, q19, [sp, #1008]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldp q23, q29, [x1, #-1024]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp w3, w5, [sp], #0
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stp wzr, w9, [sp], #252
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp w2, wzr, [sp], #-256
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp w9, w10, [sp], #4
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldpsw x9, x10, [sp], #4
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldpsw x9, x10, [x2], #-256
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldpsw x20, x30, [sp], #252
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp x21, x29, [x2], #504
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp x22, x23, [x3], #-512
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp x24, x25, [x4], #8
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp s29, s28, [sp], #252
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - stp s27, s26, [sp], #-256
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp s1, s2, [x3], #44
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - stp d3, d5, [x9], #504
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - stp d7, d11, [x10], #-512
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp d2, d3, [x30], #-8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stp q3, q5, [sp], #0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stp q17, q19, [sp], #1008
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp q23, q29, [x1], #-1024
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp w3, w5, [sp, #0]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stp wzr, w9, [sp, #252]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp w2, wzr, [sp, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp w9, w10, [sp, #4]!
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldpsw x9, x10, [sp, #4]!
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldpsw x9, x10, [x2, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldpsw x20, x30, [sp, #252]!
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp x21, x29, [x2, #504]!
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp x22, x23, [x3, #-512]!
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ldp x24, x25, [x4, #8]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp s29, s28, [sp, #252]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - stp s27, s26, [sp, #-256]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp s1, s2, [x3, #44]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - stp d3, d5, [x9, #504]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.50 0.50 - - - - stp d7, d11, [x10, #-512]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp d2, d3, [x30, #-8]!
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stp q3, q5, [sp, #0]!
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stp q17, q19, [sp, #1008]!
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 - - - - - - ldp q23, q29, [x1, #-1024]!
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnp w3, w5, [sp]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stnp wzr, w9, [sp, #252]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnp w2, wzr, [sp, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnp w9, w10, [sp, #4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ldnp x21, x29, [x2, #504]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ldnp x22, x23, [x3, #-512]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ldnp x24, x25, [x4, #8]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnp s29, s28, [sp, #252]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnp s27, s26, [sp, #-256]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnp s1, s2, [x3, #44]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnp d3, d5, [x9, #504]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnp d7, d11, [x10, #-512]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnp d2, d3, [x30, #-8]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stnp q3, q5, [sp]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - stnp q17, q19, [sp, #1008]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnp q23, q29, [x1, #-1024]
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and wsp, w16, #0xe00
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and x2, x22, #0x1e00
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ands w14, w8, #0x70
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ands x4, x10, #0x60
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - eor wsp, w4, #0xe00
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - eor x27, x25, #0x1e00
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov w3, #983055
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov x10, #-6148914691236517206
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w12, w23, w21
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w16, w15, w1, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w9, w4, w10, lsl #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w3, w30, w11
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and x3, x5, x7, lsl #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and x5, x14, x19, asr #4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w3, w17, w19, ror #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w0, w2, wzr, lsr #17
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w3, w30, w11, asr #2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and xzr, x4, x26
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and w3, wzr, w20, ror #2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - and x7, x20, xzr, asr #63
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bic x13, x20, x14, lsl #47
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bic w2, w7, w9
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - eon w29, w4, w19
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - eon x19, x12, x2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - eor w8, w27, w2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - eor x22, x16, x6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - orr w2, w7, w0, asr #31
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - orr x8, x9, x10, lsl #12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - orn x3, x5, x7, asr #2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - orn w2, w5, w29
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ands w7, wzr, w9, lsl #1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ands x3, x5, x20, ror #63
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bics w3, w5, w7
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - bics x3, xzr, x3, lsl #1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - tst w3, w7, lsl #31
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - tst x2, x20, asr #2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov x3, x6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov x3, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov wzr, w2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov w3, w5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movz w2, #0, lsl #16
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov w2, #-1235
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov x2, #5299989643264
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - mov x2, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movk w3, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movz x4, #0, lsl #16
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movk w5, #0, lsl #16
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movz x6, #0, lsl #32
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movk x7, #0, lsl #32
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movz x8, #0, lsl #48
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - movk x9, #0, lsl #48
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - - - - - - msr DAIFSet, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adr x2, #1600
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adrp x21, #6553600
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - adr x0, #262144
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - tbz x12, #62, #0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - tbz x12, #62, #4
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - tbz x12, #62, #-32768
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - tbz w17, #16, test
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - tbnz x12, #60, #32764
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - tbnz w3, #28, test
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - b #4
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - b #-4
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - b #134217724
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - bl test
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - br x20
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - blr xzr
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - ret x10
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - ret
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - eret
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - - - - - - drps
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-bf16-instructions.s
new file mode 100644
index 0000000..b2d3c87
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-bf16-instructions.s
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/bf16-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.25 bfcvt h0, s0
+# CHECK-NEXT: 1 3 0.25 bfcvtn v0.4h, v0.4s
+# CHECK-NEXT: 1 3 0.25 bfcvtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.17 bfdot v0.2s, v24.4h, v14.2h[2]
+# CHECK-NEXT: 1 4 0.17 bfdot v0.2s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 bfdot v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 5 0.17 bfmlalb v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 5 0.17 bfmlalb v0.4s, v0.8h, v0.h[3]
+# CHECK-NEXT: 1 5 0.17 bfmlalt v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 5 0.17 bfmlalt v0.4s, v0.8h, v0.h[3]
+# CHECK-NEXT: 1 5 0.17 bfmmla v0.4s, v0.8h, v0.8h
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 2.08 2.08 1.33 2.08 2.08 1.33
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - bfcvt h0, s0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - bfcvtn v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - bfcvtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfdot v0.2s, v24.4h, v14.2h[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfdot v0.2s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfdot v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfmlalb v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfmlalb v0.4s, v0.8h, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfmlalt v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfmlalt v0.4s, v0.8h, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bfmmla v0.4s, v0.8h, v0.8h
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-complxnum-instructions.s
new file mode 100644
index 0000000..5b59bc8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-complxnum-instructions.s
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/complxnum-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.17 fcadd v0.2s, v0.2s, v0.2s, #90
+# CHECK-NEXT: 1 3 0.17 fcadd v0.4s, v0.4s, v0.4s, #270
+# CHECK-NEXT: 1 5 0.17 fcmla v0.2s, v0.2s, v0.2s, #90
+# CHECK-NEXT: 1 5 0.17 fcmla v0.4s, v0.4s, v0.s[1], #0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fcadd v0.2s, v0.2s, v0.2s, #90
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fcadd v0.4s, v0.4s, v0.4s, #270
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fcmla v0.2s, v0.2s, v0.2s, #90
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fcmla v0.4s, v0.4s, v0.s[1], #0
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-flag-manipulation-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-flag-manipulation-instructions.s
new file mode 100644
index 0000000..1322a02
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-flag-manipulation-instructions.s
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/flag-manipulation-instructions.s | FileCheck %s
+
+setf8 w1
+setf16 w1
+rmif x0, #0, #0
+cfinv
+axflag
+xaflag
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.13 U setf8 w1
+# CHECK-NEXT: 1 1 0.13 U setf16 w1
+# CHECK-NEXT: 1 1 0.13 U rmif x0, #0, #0
+# CHECK-NEXT: 1 1 0.10 U cfinv
+# CHECK-NEXT: 1 1 0.13 U axflag
+# CHECK-NEXT: 1 1 0.13 U xaflag
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - setf8 w1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - setf16 w1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - rmif x0, #0, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - - - - - - cfinv
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - axflag
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - xaflag
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-forwarding.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-forwarding.s
new file mode 100644
index 0000000..6cb378f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-forwarding.s
@@ -0,0 +1,2520 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -mattr=+sve --instruction-info=0 --resource-pressure=0 --timeline --timeline-max-iterations=2 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN madd
+mul x0, x0, x0
+madd x0, x1, x2, x0
+madd x0, x1, x2, x0
+madd x0, x0, x0, x0
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN smaddl
+mul x0, x0, x0
+smaddl x0, w1, w2, x0
+smaddl x0, w1, w2, x0
+smaddl x0, w0, w0, x0
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fmadd
+fadd d0, d0, d0
+fmadd d0, d1, d2, d0
+fmul d0, d0, d0
+fmadd d0, d1, d2, d0
+fmadd d0, d1, d2, d0
+fmadd d0, d0, d1, d2
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN saba
+mul v0.4s, v0.4s, v0.4s
+saba v0.4s, v1.4s, v2.4s
+saba v0.4s, v1.4s, v2.4s
+saba v0.4s, v0.4s, v1.4s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sdot
+mul v0.4s, v0.4s, v0.4s
+sdot v0.4s, v1.16b, v2.16b
+sdot v0.4s, v1.16b, v2.16b
+sdot v0.4s, v0.16b, v1.16b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN smmla
+mul v0.4s, v0.4s, v0.4s
+smmla v0.4s, v1.16b, v2.16b
+smmla v0.4s, v1.16b, v2.16b
+smmla v0.4s, v0.16b, v1.16b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN mla
+mul v0.4s, v0.4s, v0.4s
+mla v0.4s, v1.4s, v2.4s
+mla v0.4s, v1.4s, v2.4s
+mla v0.4s, v0.4s, v1.4s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sqrdmlah
+mul v0.4s, v0.4s, v0.4s
+sqrdmlah v0.8h, v1.8h, v2.8h
+sqrdmlah v0.8h, v1.8h, v2.8h
+sqrdmlah v0.8h, v1.8h, v2.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN smlal2
+mul v0.4s, v0.4s, v0.4s
+smlal2 v0.4s, v1.8h, v2.8h
+smlal2 v0.4s, v1.8h, v2.8h
+smlal2 v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sadalp
+mul v0.4s, v0.4s, v0.4s
+sadalp v0.2d, v1.4s
+sadalp v0.2d, v1.4s
+sadalp v0.2d, v0.4s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fcmla
+fmul v0.4s, v0.4s, v0.4s
+fcmla v0.2d, v1.2d, v2.2d, #90
+fcmla v0.2d, v1.2d, v2.2d, #90
+fcmla v0.2d, v0.2d, v1.2d, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fmla
+fmul v0.2d, v0.2d, v0.2d
+fmla v0.2d, v1.2d, v2.2d
+fadd v0.2d, v0.2d, v0.2d
+fmla v0.2d, v1.2d, v2.2d
+fmla v0.2d, v1.2d, v2.2d
+fmla v0.2d, v0.2d, v1.2d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fmlal
+fmul v0.2d, v0.2d, v0.2d
+fmlal v0.4s, v1.4h, v2.4h
+fadd v0.2d, v0.2d, v0.2d
+fmlal v0.4s, v1.4h, v2.4h
+fmlal v0.4s, v1.4h, v2.4h
+fmlal v0.4s, v0.4h, v1.4h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfdot
+fmul v0.2d, v0.2d, v0.2d
+bfdot v0.4s, v1.8h, v2.8h
+bfdot v0.4s, v1.8h, v2.8h
+bfdot v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfmmla
+fmul v0.2d, v0.2d, v0.2d
+bfmmla v0.4s, v1.8h, v2.8h
+bfmmla v0.4s, v1.8h, v2.8h
+bfmmla v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfmlalb
+fmul v0.2d, v0.2d, v0.2d
+bfmlalb v0.4s, v1.8h, v2.8h
+bfmlalb v0.4s, v1.8h, v2.8h
+bfmlalb v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z saba
+mul z0.d, z0.d, z0.d
+saba z0.d, z1.d, z2.d
+saba z0.d, z1.d, z2.d
+saba z0.d, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sabalt
+mul z0.h, z0.h, z0.h
+sabalt z0.h, z1.b, z2.b
+sabalt z0.h, z1.b, z2.b
+sabalt z0.h, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sadalp
+mul z0.d, z0.d, z0.d
+sadalp z0.d, p0/m, z1.s
+sadalp z0.d, p0/m, z1.s
+sadalp z0.d, p0/m, z0.s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z ssra
+mul z0.d, z0.d, z0.d
+ssra z0.d, z1.d, #1
+ssra z0.d, z1.d, #1
+ssra z0.d, z0.d, #1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cdot.s
+mul z0.d, z0.d, z0.d
+cdot z0.s, z1.b, z2.b, #90
+cdot z0.s, z1.b, z2.b, #90
+cdot z0.s, z0.b, z1.b, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cdot.d
+mul z0.d, z0.d, z0.d
+cdot z0.d, z1.h, z2.h, #90
+cdot z0.d, z1.h, z2.h, #90
+cdot z0.d, z0.h, z1.h, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cmla.b
+mul z0.d, z0.d, z0.d
+cmla z0.b, z1.b, z2.b, #90
+cmla z0.b, z1.b, z2.b, #90
+cmla z0.b, z0.b, z1.b, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cmla.d
+mul z0.d, z0.d, z0.d
+cmla z0.d, z1.d, z2.d, #90
+cmla z0.d, z1.d, z2.d, #90
+cmla z0.d, z0.d, z1.d, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sdot.s
+mul z0.d, p0/m, z0.d, z0.d
+sdot z0.s, z1.b, z2.b
+sdot z0.s, z1.b, z2.b
+sdot z0.s, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sudot
+mul z0.d, p0/m, z0.d, z0.d
+sdot z0.s, z1.b, z2.b[1]
+sdot z0.s, z1.b, z2.b[1]
+sdot z0.s, z0.b, z1.b[1]
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sdot.d
+mul z0.d, z0.d, z0.d
+sdot z0.d, z1.h, z2.h
+sdot z0.d, z1.h, z2.h
+sdot z0.d, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z smmla
+mul z0.s, z0.s, z0.s
+smmla z0.s, z1.b, z2.b
+smmla z0.s, z1.b, z2.b
+smmla z0.s, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z mla.b
+mul z0.d, z0.d, z0.d
+mla z0.b, p0/m, z1.b, z2.b
+mla z0.b, p0/m, z1.b, z2.b
+mla z0.b, p0/m, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z mla.d
+mul z0.d, z0.d, z0.d
+mla z0.d, p0/m, z1.d, z2.d
+mla z0.d, p0/m, z1.d, z2.d
+mla z0.d, p0/m, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z smlalb
+mul z0.d, z0.d, z0.d
+smlalb z0.d, z1.s, z2.s
+smlalb z0.d, z1.s, z2.s
+smlalb z0.d, z0.s, z1.s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sqdmlalb
+mul z0.d, z0.d, z0.d
+sqdmlalb z0.d, z1.s, z2.s
+sqdmlalb z0.d, z1.s, z2.s
+sqdmlalb z0.d, z0.s, z1.s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sqrdmlah.b
+mul z0.d, z0.d, z0.d
+sqrdmlah z0.b, z1.b, z2.b
+sqrdmlah z0.b, z1.b, z2.b
+sqrdmlah z0.b, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sqrdmlah.d
+mul z0.d, z0.d, z0.d
+sqrdmlah z0.d, z1.d, z2.d
+sqrdmlah z0.d, z1.d, z2.d
+sqrdmlah z0.d, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fcmla ZPmZZ
+fmul z0.d, z0.d, z0.d
+fcmla z0.d, p0/m, z1.d, z2.d, 90
+fcmla z0.d, p0/m, z1.d, z2.d, 90
+fcmla z0.d, p0/m, z0.d, z1.d, 90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fcmla ZZZI
+fmul z0.d, z0.d, z0.d
+fcmla z0.s, z1.s, z2.s[1], 90
+fcmla z0.s, z1.s, z2.s[1], 90
+fcmla z0.s, z0.s, z1.s[1], 90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fmla ZPmZZ
+fmul z0.d, z0.d, z0.d
+fmla z0.d, p0/m, z1.d, z2.d
+fmla z0.d, p0/m, z1.d, z2.d
+fmla z0.d, p0/m, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fmla ZZZI
+fmul z0.d, z0.d, z0.d
+fmla z0.d, z1.d, z2.d[1]
+fmla z0.d, z1.d, z2.d[1]
+fmla z0.d, z0.d, z1.d[1]
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fmlalb ZZZ
+fmul z0.d, z0.d, z0.d
+fmlalb z0.s, z1.h, z2.h
+fmlalb z0.s, z1.h, z2.h
+fmlalb z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z bfdot
+fmul z0.d, z0.d, z0.d
+bfdot z0.s, z1.h, z2.h
+bfdot z0.s, z1.h, z2.h
+bfdot z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z bfmmla
+fmul z0.d, z0.d, z0.d
+bfmmla z0.s, z1.h, z2.h
+bfmmla z0.s, z1.h, z2.h
+bfmmla z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfmlalb
+fmul z0.d, z0.d, z0.d
+bfmlalb z0.s, z1.h, z2.h
+bfmlalb z0.s, z1.h, z2.h
+bfmlalb z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN brkn
+brkn p0.b, p15/z, p1.b, p0.b
+brkn p0.b, p15/z, p1.b, p0.b
+brkn p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN brkns
+brkns p0.b, p15/z, p1.b, p0.b
+brkns p0.b, p15/z, p1.b, p0.b
+brkns p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sel
+sel z0.s, p15, z1.s, z2.s
+sel z0.s, p15, z1.s, z2.s
+sel z0.s, p15, z1.s, z2.s
+sel z0.s, p15, z0.s, z1.s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN and
+and p0.b, p15/z, p1.b, p0.b
+and p0.b, p15/z, p1.b, p0.b
+and p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN ands
+ands p0.b, p15/z, p1.b, p0.b
+ands p0.b, p15/z, p1.b, p0.b
+ands p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bic
+bic p0.b, p15/z, p1.b, p0.b
+bic p0.b, p15/z, p1.b, p0.b
+bic p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bics
+bics p0.b, p15/z, p1.b, p0.b
+bics p0.b, p15/z, p1.b, p0.b
+bics p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN eor
+eor p0.b, p15/z, p1.b, p0.b
+eor p0.b, p15/z, p1.b, p0.b
+eor p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN eors
+eors p0.b, p15/z, p1.b, p0.b
+eors p0.b, p15/z, p1.b, p0.b
+eors p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN nand
+nand p0.b, p15/z, p1.b, p0.b
+nand p0.b, p15/z, p1.b, p0.b
+nand p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN nands
+nands p0.b, p15/z, p1.b, p0.b
+nands p0.b, p15/z, p1.b, p0.b
+nands p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN nor
+nor p0.b, p15/z, p1.b, p0.b
+nor p0.b, p15/z, p1.b, p0.b
+nor p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN nors
+nors p0.b, p15/z, p1.b, p0.b
+nors p0.b, p15/z, p1.b, p0.b
+nors p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN orn
+orn p0.b, p15/z, p1.b, p0.b
+orn p0.b, p15/z, p1.b, p0.b
+orn p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN orns
+orns p0.b, p15/z, p1.b, p0.b
+orns p0.b, p15/z, p1.b, p0.b
+orns p0.b, p15/z, p1.b, p0.b
+# LLVM-MCA-END
+
+# CHECK: [0] Code Region - madd
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 903
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeER. . . . mul x0, x0, x0
+# CHECK-NEXT: [0,1] D==eeeER . . . madd x0, x1, x2, x0
+# CHECK-NEXT: [0,2] D===eeeER . . . madd x0, x1, x2, x0
+# CHECK-NEXT: [0,3] D======eeeER . . madd x0, x0, x0, x0
+# CHECK-NEXT: [1,0] D=========eeER . . mul x0, x0, x0
+# CHECK-NEXT: [1,1] D===========eeeER . madd x0, x1, x2, x0
+# CHECK-NEXT: [1,2] D============eeeER . madd x0, x1, x2, x0
+# CHECK-NEXT: [1,3] D===============eeeER madd x0, x0, x0, x0
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 5.5 0.5 0.0 mul x0, x0, x0
+# CHECK-NEXT: 1. 2 7.5 0.0 0.0 madd x0, x1, x2, x0
+# CHECK-NEXT: 2. 2 8.5 0.0 0.0 madd x0, x1, x2, x0
+# CHECK-NEXT: 3. 2 11.5 0.0 0.0 madd x0, x0, x0, x0
+# CHECK-NEXT: 2 8.3 0.1 0.0 <total>
+
+# CHECK: [1] Code Region - smaddl
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 903
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeER. . . . mul x0, x0, x0
+# CHECK-NEXT: [0,1] D==eeeER . . . smaddl x0, w1, w2, x0
+# CHECK-NEXT: [0,2] D===eeeER . . . smaddl x0, w1, w2, x0
+# CHECK-NEXT: [0,3] D======eeeER . . smaddl x0, w0, w0, x0
+# CHECK-NEXT: [1,0] D=========eeER . . mul x0, x0, x0
+# CHECK-NEXT: [1,1] D===========eeeER . smaddl x0, w1, w2, x0
+# CHECK-NEXT: [1,2] D============eeeER . smaddl x0, w1, w2, x0
+# CHECK-NEXT: [1,3] D===============eeeER smaddl x0, w0, w0, x0
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 5.5 0.5 0.0 mul x0, x0, x0
+# CHECK-NEXT: 1. 2 7.5 0.0 0.0 smaddl x0, w1, w2, x0
+# CHECK-NEXT: 2. 2 8.5 0.0 0.0 smaddl x0, w1, w2, x0
+# CHECK-NEXT: 3. 2 11.5 0.0 0.0 smaddl x0, w0, w0, x0
+# CHECK-NEXT: 2 8.3 0.1 0.0 <total>
+
+# CHECK: [2] Code Region - fmadd
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 600
+# CHECK-NEXT: Total Cycles: 1703
+# CHECK-NEXT: Total uOps: 600
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.35
+# CHECK-NEXT: IPC: 0.35
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeER. . . . . . .. fadd d0, d0, d0
+# CHECK-NEXT: [0,1] D==eeeeER . . . . . .. fmadd d0, d1, d2, d0
+# CHECK-NEXT: [0,2] D======eeeER . . . . .. fmul d0, d0, d0
+# CHECK-NEXT: [0,3] D=======eeeeER . . . . .. fmadd d0, d1, d2, d0
+# CHECK-NEXT: [0,4] D=========eeeeER . . . .. fmadd d0, d1, d2, d0
+# CHECK-NEXT: [0,5] D=============eeeeER. . . .. fmadd d0, d0, d1, d2
+# CHECK-NEXT: [1,0] D=================eeER . . .. fadd d0, d0, d0
+# CHECK-NEXT: [1,1] D===================eeeeER . .. fmadd d0, d1, d2, d0
+# CHECK-NEXT: [1,2] D=======================eeeER . .. fmul d0, d0, d0
+# CHECK-NEXT: [1,3] D========================eeeeER .. fmadd d0, d1, d2, d0
+# CHECK-NEXT: [1,4] .D=========================eeeeER .. fmadd d0, d1, d2, d0
+# CHECK-NEXT: [1,5] .D=============================eeeeER fmadd d0, d0, d1, d2
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 9.5 0.5 0.0 fadd d0, d0, d0
+# CHECK-NEXT: 1. 2 11.5 0.0 0.0 fmadd d0, d1, d2, d0
+# CHECK-NEXT: 2. 2 15.5 0.0 0.0 fmul d0, d0, d0
+# CHECK-NEXT: 3. 2 16.5 0.0 0.0 fmadd d0, d1, d2, d0
+# CHECK-NEXT: 4. 2 18.0 0.0 0.0 fmadd d0, d1, d2, d0
+# CHECK-NEXT: 5. 2 22.0 0.0 0.0 fmadd d0, d0, d1, d2
+# CHECK-NEXT: 2 15.5 0.1 0.0 <total>
+
+# CHECK: [3] Code Region - saba
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D====eeeeER . . . saba v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [0,2] D=====eeeeER . . . saba v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [0,3] D======eeeeER . . . saba v0.4s, v0.4s, v1.4s
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D==============eeeeER . saba v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [1,2] D===============eeeeER. saba v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [1,3] D================eeeeER saba v0.4s, v0.4s, v1.4s
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 saba v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 saba v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 saba v0.4s, v0.4s, v1.4s
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [4] Code Region - sdot
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1103
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D====eeeER. . . . sdot v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [0,2] D=====eeeER . . . sdot v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [0,3] D========eeeER . . . sdot v0.4s, v0.16b, v1.16b
+# CHECK-NEXT: [1,0] D===========eeeeER . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D===============eeeER . sdot v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [1,2] D================eeeER . sdot v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [1,3] D===================eeeER sdot v0.4s, v0.16b, v1.16b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 10.5 0.0 0.0 sdot v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: 2. 2 11.5 0.0 0.0 sdot v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: 3. 2 14.5 0.0 0.0 sdot v0.4s, v0.16b, v1.16b
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [5] Code Region - smmla
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1103
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D====eeeER. . . . smmla v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [0,2] D=====eeeER . . . smmla v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [0,3] D========eeeER . . . smmla v0.4s, v0.16b, v1.16b
+# CHECK-NEXT: [1,0] D===========eeeeER . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D===============eeeER . smmla v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [1,2] D================eeeER . smmla v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: [1,3] D===================eeeER smmla v0.4s, v0.16b, v1.16b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.5 0.5 0.0 mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 10.5 0.0 0.0 smmla v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: 2. 2 11.5 0.0 0.0 smmla v0.4s, v1.16b, v2.16b
+# CHECK-NEXT: 3. 2 14.5 0.0 0.0 smmla v0.4s, v0.16b, v1.16b
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [6] Code Region - mla
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D====eeeeER . . . mla v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [0,2] D=====eeeeER . . . mla v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [0,3] D======eeeeER . . . mla v0.4s, v0.4s, v1.4s
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D==============eeeeER . mla v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [1,2] D===============eeeeER. mla v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: [1,3] D================eeeeER mla v0.4s, v0.4s, v1.4s
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 mla v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 mla v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 mla v0.4s, v0.4s, v1.4s
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [7] Code Region - sqrdmlah
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeeER . . . .. mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D====eeeeER . . .. sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: [0,2] D======eeeeER . . .. sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: [0,3] D========eeeeER. . .. sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: [1,0] D============eeeeER . .. mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D================eeeeER .. sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: [1,2] D==================eeeeER.. sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: [1,3] D====================eeeeER sqrdmlah v0.8h, v1.8h, v2.8h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 11.0 0.0 0.0 sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: 2. 2 13.0 0.0 0.0 sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: 3. 2 15.0 0.0 0.0 sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: 2 11.5 0.1 0.0 <total>
+
+# CHECK: [8] Code Region - smlal2
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D====eeeeER . . . smlal2 v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,2] D=====eeeeER . . . smlal2 v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,3] D======eeeeER . . . smlal2 v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D==============eeeeER . smlal2 v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,2] D===============eeeeER. smlal2 v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,3] D================eeeeER smlal2 v0.4s, v0.8h, v1.8h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 smlal2 v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 smlal2 v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 smlal2 v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [9] Code Region - sadalp
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D====eeeeER . . . sadalp v0.2d, v1.4s
+# CHECK-NEXT: [0,2] D=====eeeeER . . . sadalp v0.2d, v1.4s
+# CHECK-NEXT: [0,3] D======eeeeER . . . sadalp v0.2d, v0.4s
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D==============eeeeER . sadalp v0.2d, v1.4s
+# CHECK-NEXT: [1,2] D===============eeeeER. sadalp v0.2d, v1.4s
+# CHECK-NEXT: [1,3] D================eeeeER sadalp v0.2d, v0.4s
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 sadalp v0.2d, v1.4s
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 sadalp v0.2d, v1.4s
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 sadalp v0.2d, v0.4s
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [10] Code Region - fcmla
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. fmul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [0,1] D===eeeeeER . . .. fcmla v0.2d, v1.2d, v2.2d, #90
+# CHECK-NEXT: [0,2] D=====eeeeeER . . .. fcmla v0.2d, v1.2d, v2.2d, #90
+# CHECK-NEXT: [0,3] D=======eeeeeER. . .. fcmla v0.2d, v0.2d, v1.2d, #90
+# CHECK-NEXT: [1,0] D============eeeER . .. fmul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,1] D===============eeeeeER .. fcmla v0.2d, v1.2d, v2.2d, #90
+# CHECK-NEXT: [1,2] D=================eeeeeER.. fcmla v0.2d, v1.2d, v2.2d, #90
+# CHECK-NEXT: [1,3] D===================eeeeeER fcmla v0.2d, v0.2d, v1.2d, #90
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 fmul v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 fcmla v0.2d, v1.2d, v2.2d, #90
+# CHECK-NEXT: 2. 2 12.0 0.0 0.0 fcmla v0.2d, v1.2d, v2.2d, #90
+# CHECK-NEXT: 3. 2 14.0 0.0 0.0 fcmla v0.2d, v0.2d, v1.2d, #90
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [11] Code Region - fmla
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 600
+# CHECK-NEXT: Total Cycles: 1703
+# CHECK-NEXT: Total uOps: 600
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.35
+# CHECK-NEXT: IPC: 0.35
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeER . . . . . .. fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [0,1] D===eeeeER. . . . . .. fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: [0,2] D=======eeER . . . . .. fadd v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [0,3] D=========eeeeER . . . .. fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: [0,4] D===========eeeeER . . . .. fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: [0,5] D=============eeeeER. . . .. fmla v0.2d, v0.2d, v1.2d
+# CHECK-NEXT: [1,0] D=================eeeER . . .. fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,1] D====================eeeeER . .. fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: [1,2] D========================eeER . .. fadd v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,3] D==========================eeeeER .. fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: [1,4] .D===========================eeeeER.. fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: [1,5] .D=============================eeeeER fmla v0.2d, v0.2d, v1.2d
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 9.5 0.5 0.0 fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1. 2 12.5 0.0 0.0 fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: 2. 2 16.5 0.0 0.0 fadd v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 3. 2 18.5 0.0 0.0 fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: 4. 2 20.0 0.0 0.0 fmla v0.2d, v1.2d, v2.2d
+# CHECK-NEXT: 5. 2 22.0 0.0 0.0 fmla v0.2d, v0.2d, v1.2d
+# CHECK-NEXT: 2 16.5 0.1 0.0 <total>
+
+# CHECK: [12] Code Region - fmlal
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 600
+# CHECK-NEXT: Total Cycles: 1703
+# CHECK-NEXT: Total uOps: 600
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.35
+# CHECK-NEXT: IPC: 0.35
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeER . . . . . .. fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [0,1] D===eeeeER. . . . . .. fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: [0,2] D=======eeER . . . . .. fadd v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [0,3] D=========eeeeER . . . .. fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: [0,4] D===========eeeeER . . . .. fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: [0,5] D=============eeeeER. . . .. fmlal v0.4s, v0.4h, v1.4h
+# CHECK-NEXT: [1,0] D=================eeeER . . .. fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,1] D====================eeeeER . .. fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: [1,2] D========================eeER . .. fadd v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,3] D==========================eeeeER .. fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: [1,4] .D===========================eeeeER.. fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: [1,5] .D=============================eeeeER fmlal v0.4s, v0.4h, v1.4h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 9.5 0.5 0.0 fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1. 2 12.5 0.0 0.0 fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: 2. 2 16.5 0.0 0.0 fadd v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 3. 2 18.5 0.0 0.0 fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: 4. 2 20.0 0.0 0.0 fmlal v0.4s, v1.4h, v2.4h
+# CHECK-NEXT: 5. 2 22.0 0.0 0.0 fmlal v0.4s, v0.4h, v1.4h
+# CHECK-NEXT: 2 16.5 0.1 0.0 <total>
+
+# CHECK: [13] Code Region - bfdot
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1103
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeER . . . . fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [0,1] D===eeeeER. . . . bfdot v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,2] D=====eeeeER . . . bfdot v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,3] D=======eeeeER . . . bfdot v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: [1,0] D===========eeeER . . fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,1] D==============eeeeER . bfdot v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,2] D================eeeeER . bfdot v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,3] D==================eeeeER bfdot v0.4s, v0.8h, v1.8h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.5 0.5 0.0 fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 bfdot v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 2. 2 11.5 0.0 0.0 bfdot v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 3. 2 13.5 0.0 0.0 bfdot v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: 2 10.3 0.1 0.0 <total>
+
+# CHECK: [14] Code Region - bfmmla
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1603
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.25
+# CHECK-NEXT: IPC: 0.25
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 01234
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeER . . . . . . fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [0,1] D===eeeeeER . . . . . bfmmla v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,2] D=======eeeeeER. . . . . bfmmla v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,3] D===========eeeeeER . . . . bfmmla v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: [1,0] D================eeeER . . . fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,1] D===================eeeeeER . . bfmmla v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,2] D=======================eeeeeER . bfmmla v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,3] D===========================eeeeeER bfmmla v0.4s, v0.8h, v1.8h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 9.0 0.5 0.0 fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1. 2 12.0 0.0 0.0 bfmmla v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 2. 2 16.0 0.0 0.0 bfmmla v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 3. 2 20.0 0.0 0.0 bfmmla v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: 2 14.3 0.1 0.0 <total>
+
+# CHECK: [15] Code Region - bfmlalb
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [0,1] D===eeeeeER . . .. bfmlalb v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,2] D=====eeeeeER . . .. bfmlalb v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [0,3] D=======eeeeeER. . .. bfmlalb v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: [1,0] D============eeeER . .. fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,1] D===============eeeeeER .. bfmlalb v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,2] D=================eeeeeER.. bfmlalb v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: [1,3] D===================eeeeeER bfmlalb v0.4s, v0.8h, v1.8h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 fmul v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 bfmlalb v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 2. 2 12.0 0.0 0.0 bfmlalb v0.4s, v1.8h, v2.8h
+# CHECK-NEXT: 3. 2 14.0 0.0 0.0 bfmlalb v0.4s, v0.8h, v1.8h
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [16] Code Region - Z saba
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . saba z0.d, z1.d, z2.d
+# CHECK-NEXT: [0,2] D=====eeeeER . . . saba z0.d, z1.d, z2.d
+# CHECK-NEXT: [0,3] D======eeeeER . . . saba z0.d, z0.d, z1.d
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . saba z0.d, z1.d, z2.d
+# CHECK-NEXT: [1,2] D===============eeeeER. saba z0.d, z1.d, z2.d
+# CHECK-NEXT: [1,3] D================eeeeER saba z0.d, z0.d, z1.d
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 saba z0.d, z1.d, z2.d
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 saba z0.d, z1.d, z2.d
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 saba z0.d, z0.d, z1.d
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [17] Code Region - Z sabalt
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.h, z0.h, z0.h
+# CHECK-NEXT: [0,1] D====eeeeER . . . sabalt z0.h, z1.b, z2.b
+# CHECK-NEXT: [0,2] D=====eeeeER . . . sabalt z0.h, z1.b, z2.b
+# CHECK-NEXT: [0,3] D======eeeeER . . . sabalt z0.h, z0.b, z1.b
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.h, z0.h, z0.h
+# CHECK-NEXT: [1,1] D==============eeeeER . sabalt z0.h, z1.b, z2.b
+# CHECK-NEXT: [1,2] D===============eeeeER. sabalt z0.h, z1.b, z2.b
+# CHECK-NEXT: [1,3] D================eeeeER sabalt z0.h, z0.b, z1.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.h, z0.h, z0.h
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 sabalt z0.h, z1.b, z2.b
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 sabalt z0.h, z1.b, z2.b
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 sabalt z0.h, z0.b, z1.b
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [18] Code Region - Z sadalp
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . sadalp z0.d, p0/m, z1.s
+# CHECK-NEXT: [0,2] D=====eeeeER . . . sadalp z0.d, p0/m, z1.s
+# CHECK-NEXT: [0,3] D======eeeeER . . . sadalp z0.d, p0/m, z0.s
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . sadalp z0.d, p0/m, z1.s
+# CHECK-NEXT: [1,2] D===============eeeeER. sadalp z0.d, p0/m, z1.s
+# CHECK-NEXT: [1,3] D================eeeeER sadalp z0.d, p0/m, z0.s
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 sadalp z0.d, p0/m, z1.s
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 sadalp z0.d, p0/m, z1.s
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 sadalp z0.d, p0/m, z0.s
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [19] Code Region - Z ssra
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1303
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.31
+# CHECK-NEXT: IPC: 0.31
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012345678
+
+# CHECK: [0,0] DeeeeER . . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . . ssra z0.d, z1.d, #1
+# CHECK-NEXT: [0,2] D=====eeeeER . . . . ssra z0.d, z1.d, #1
+# CHECK-NEXT: [0,3] D=========eeeeER . . . ssra z0.d, z0.d, #1
+# CHECK-NEXT: [1,0] D=============eeeeER. . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D=================eeeeER . . ssra z0.d, z1.d, #1
+# CHECK-NEXT: [1,2] D==================eeeeER. . ssra z0.d, z1.d, #1
+# CHECK-NEXT: [1,3] D======================eeeeER ssra z0.d, z0.d, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.5 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 11.5 0.0 0.0 ssra z0.d, z1.d, #1
+# CHECK-NEXT: 2. 2 12.5 0.0 0.0 ssra z0.d, z1.d, #1
+# CHECK-NEXT: 3. 2 16.5 0.0 0.0 ssra z0.d, z0.d, #1
+# CHECK-NEXT: 2 12.0 0.1 0.0 <total>
+
+# CHECK: [20] Code Region - Z cdot.s
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 903
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeeeER . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeER. . . cdot z0.s, z1.b, z2.b, #90
+# CHECK-NEXT: [0,2] D=====eeeER . . cdot z0.s, z1.b, z2.b, #90
+# CHECK-NEXT: [0,3] D======eeeER . . cdot z0.s, z0.b, z1.b, #90
+# CHECK-NEXT: [1,0] D=========eeeeER . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D=============eeeER . cdot z0.s, z1.b, z2.b, #90
+# CHECK-NEXT: [1,2] D==============eeeER. cdot z0.s, z1.b, z2.b, #90
+# CHECK-NEXT: [1,3] D===============eeeER cdot z0.s, z0.b, z1.b, #90
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 5.5 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 cdot z0.s, z1.b, z2.b, #90
+# CHECK-NEXT: 2. 2 10.5 0.0 0.0 cdot z0.s, z1.b, z2.b, #90
+# CHECK-NEXT: 3. 2 11.5 0.0 0.0 cdot z0.s, z0.b, z1.b, #90
+# CHECK-NEXT: 2 9.3 0.1 0.0 <total>
+
+# CHECK: [21] Code Region - Z cdot.d
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 903
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeeeER . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeER. . . cdot z0.d, z1.h, z2.h, #90
+# CHECK-NEXT: [0,2] D=====eeeER . . cdot z0.d, z1.h, z2.h, #90
+# CHECK-NEXT: [0,3] D======eeeER . . cdot z0.d, z0.h, z1.h, #90
+# CHECK-NEXT: [1,0] D=========eeeeER . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D=============eeeER . cdot z0.d, z1.h, z2.h, #90
+# CHECK-NEXT: [1,2] D==============eeeER. cdot z0.d, z1.h, z2.h, #90
+# CHECK-NEXT: [1,3] D===============eeeER cdot z0.d, z0.h, z1.h, #90
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 5.5 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 cdot z0.d, z1.h, z2.h, #90
+# CHECK-NEXT: 2. 2 10.5 0.0 0.0 cdot z0.d, z1.h, z2.h, #90
+# CHECK-NEXT: 3. 2 11.5 0.0 0.0 cdot z0.d, z0.h, z1.h, #90
+# CHECK-NEXT: 2 9.3 0.1 0.0 <total>
+
+# CHECK: [22] Code Region - Z cmla.b
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . cmla z0.b, z1.b, z2.b, #90
+# CHECK-NEXT: [0,2] D=====eeeeER . . . cmla z0.b, z1.b, z2.b, #90
+# CHECK-NEXT: [0,3] D======eeeeER . . . cmla z0.b, z0.b, z1.b, #90
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . cmla z0.b, z1.b, z2.b, #90
+# CHECK-NEXT: [1,2] D===============eeeeER. cmla z0.b, z1.b, z2.b, #90
+# CHECK-NEXT: [1,3] D================eeeeER cmla z0.b, z0.b, z1.b, #90
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 cmla z0.b, z1.b, z2.b, #90
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 cmla z0.b, z1.b, z2.b, #90
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 cmla z0.b, z0.b, z1.b, #90
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [23] Code Region - Z cmla.d
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . cmla z0.d, z1.d, z2.d, #90
+# CHECK-NEXT: [0,2] D=====eeeeER . . . cmla z0.d, z1.d, z2.d, #90
+# CHECK-NEXT: [0,3] D======eeeeER . . . cmla z0.d, z0.d, z1.d, #90
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . cmla z0.d, z1.d, z2.d, #90
+# CHECK-NEXT: [1,2] D===============eeeeER. cmla z0.d, z1.d, z2.d, #90
+# CHECK-NEXT: [1,3] D================eeeeER cmla z0.d, z0.d, z1.d, #90
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 cmla z0.d, z1.d, z2.d, #90
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 cmla z0.d, z1.d, z2.d, #90
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 cmla z0.d, z0.d, z1.d, #90
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [24] Code Region - Z sdot.s
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 903
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeeeER . . . mul z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeER. . . sdot z0.s, z1.b, z2.b
+# CHECK-NEXT: [0,2] D=====eeeER . . sdot z0.s, z1.b, z2.b
+# CHECK-NEXT: [0,3] D======eeeER . . sdot z0.s, z0.b, z1.b
+# CHECK-NEXT: [1,0] D=========eeeeER . mul z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: [1,1] D=============eeeER . sdot z0.s, z1.b, z2.b
+# CHECK-NEXT: [1,2] D==============eeeER. sdot z0.s, z1.b, z2.b
+# CHECK-NEXT: [1,3] D===============eeeER sdot z0.s, z0.b, z1.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 5.5 0.5 0.0 mul z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 sdot z0.s, z1.b, z2.b
+# CHECK-NEXT: 2. 2 10.5 0.0 0.0 sdot z0.s, z1.b, z2.b
+# CHECK-NEXT: 3. 2 11.5 0.0 0.0 sdot z0.s, z0.b, z1.b
+# CHECK-NEXT: 2 9.3 0.1 0.0 <total>
+
+# CHECK: [25] Code Region - Z sudot
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 903
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeeeER . . . mul z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeER. . . sdot z0.s, z1.b, z2.b[1]
+# CHECK-NEXT: [0,2] D=====eeeER . . sdot z0.s, z1.b, z2.b[1]
+# CHECK-NEXT: [0,3] D======eeeER . . sdot z0.s, z0.b, z1.b[1]
+# CHECK-NEXT: [1,0] D=========eeeeER . mul z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: [1,1] D=============eeeER . sdot z0.s, z1.b, z2.b[1]
+# CHECK-NEXT: [1,2] D==============eeeER. sdot z0.s, z1.b, z2.b[1]
+# CHECK-NEXT: [1,3] D===============eeeER sdot z0.s, z0.b, z1.b[1]
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 5.5 0.5 0.0 mul z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 sdot z0.s, z1.b, z2.b[1]
+# CHECK-NEXT: 2. 2 10.5 0.0 0.0 sdot z0.s, z1.b, z2.b[1]
+# CHECK-NEXT: 3. 2 11.5 0.0 0.0 sdot z0.s, z0.b, z1.b[1]
+# CHECK-NEXT: 2 9.3 0.1 0.0 <total>
+
+# CHECK: [26] Code Region - Z sdot.d
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1103
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeER. . . . sdot z0.d, z1.h, z2.h
+# CHECK-NEXT: [0,2] D=====eeeER . . . sdot z0.d, z1.h, z2.h
+# CHECK-NEXT: [0,3] D========eeeER . . . sdot z0.d, z0.h, z1.h
+# CHECK-NEXT: [1,0] D===========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D===============eeeER . sdot z0.d, z1.h, z2.h
+# CHECK-NEXT: [1,2] D================eeeER . sdot z0.d, z1.h, z2.h
+# CHECK-NEXT: [1,3] D===================eeeER sdot z0.d, z0.h, z1.h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.5 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.5 0.0 0.0 sdot z0.d, z1.h, z2.h
+# CHECK-NEXT: 2. 2 11.5 0.0 0.0 sdot z0.d, z1.h, z2.h
+# CHECK-NEXT: 3. 2 14.5 0.0 0.0 sdot z0.d, z0.h, z1.h
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [27] Code Region - Z smmla
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 903
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 0.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0
+
+# CHECK: [0,0] DeeeeER . . . mul z0.s, z0.s, z0.s
+# CHECK-NEXT: [0,1] D====eeeER. . . smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: [0,2] D=====eeeER . . smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: [0,3] D======eeeER . . smmla z0.s, z0.b, z1.b
+# CHECK-NEXT: [1,0] D=========eeeeER . mul z0.s, z0.s, z0.s
+# CHECK-NEXT: [1,1] D=============eeeER . smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: [1,2] D==============eeeER. smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: [1,3] D===============eeeER smmla z0.s, z0.b, z1.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 5.5 0.5 0.0 mul z0.s, z0.s, z0.s
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: 2. 2 10.5 0.0 0.0 smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: 3. 2 11.5 0.0 0.0 smmla z0.s, z0.b, z1.b
+# CHECK-NEXT: 2 9.3 0.1 0.0 <total>
+
+# CHECK: [28] Code Region - Z mla.b
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . mla z0.b, p0/m, z1.b, z2.b
+# CHECK-NEXT: [0,2] D=====eeeeER . . . mla z0.b, p0/m, z1.b, z2.b
+# CHECK-NEXT: [0,3] D======eeeeER . . . mla z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . mla z0.b, p0/m, z1.b, z2.b
+# CHECK-NEXT: [1,2] D===============eeeeER. mla z0.b, p0/m, z1.b, z2.b
+# CHECK-NEXT: [1,3] D================eeeeER mla z0.b, p0/m, z0.b, z1.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 mla z0.b, p0/m, z1.b, z2.b
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 mla z0.b, p0/m, z1.b, z2.b
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 mla z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [29] Code Region - Z mla.d
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . mla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [0,2] D=====eeeeER . . . mla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [0,3] D======eeeeER . . . mla z0.d, p0/m, z0.d, z1.d
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . mla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [1,2] D===============eeeeER. mla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [1,3] D================eeeeER mla z0.d, p0/m, z0.d, z1.d
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 mla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 mla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 mla z0.d, p0/m, z0.d, z1.d
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [30] Code Region - Z smlalb
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeER . . . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . . smlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [0,2] D=====eeeeER . . . smlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [0,3] D======eeeeER . . . smlalb z0.d, z0.s, z1.s
+# CHECK-NEXT: [1,0] D==========eeeeER . . mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . smlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [1,2] D===============eeeeER. smlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [1,3] D================eeeeER smlalb z0.d, z0.s, z1.s
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 smlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: 2. 2 11.0 0.0 0.0 smlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: 3. 2 12.0 0.0 0.0 smlalb z0.d, z0.s, z1.s
+# CHECK-NEXT: 2 9.8 0.1 0.0 <total>
+
+# CHECK: [31] Code Region - Z sqdmlalb
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeeER . . . .. mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . .. sqdmlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [0,2] D======eeeeER . . .. sqdmlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [0,3] D========eeeeER. . .. sqdmlalb z0.d, z0.s, z1.s
+# CHECK-NEXT: [1,0] D============eeeeER . .. mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D================eeeeER .. sqdmlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [1,2] D==================eeeeER.. sqdmlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: [1,3] D====================eeeeER sqdmlalb z0.d, z0.s, z1.s
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 11.0 0.0 0.0 sqdmlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: 2. 2 13.0 0.0 0.0 sqdmlalb z0.d, z1.s, z2.s
+# CHECK-NEXT: 3. 2 15.0 0.0 0.0 sqdmlalb z0.d, z0.s, z1.s
+# CHECK-NEXT: 2 11.5 0.1 0.0 <total>
+
+# CHECK: [32] Code Region - Z sqrdmlah.b
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeeER . . . .. mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . .. sqrdmlah z0.b, z1.b, z2.b
+# CHECK-NEXT: [0,2] D======eeeeER . . .. sqrdmlah z0.b, z1.b, z2.b
+# CHECK-NEXT: [0,3] D========eeeeER. . .. sqrdmlah z0.b, z0.b, z1.b
+# CHECK-NEXT: [1,0] D============eeeeER . .. mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D================eeeeER .. sqrdmlah z0.b, z1.b, z2.b
+# CHECK-NEXT: [1,2] D==================eeeeER.. sqrdmlah z0.b, z1.b, z2.b
+# CHECK-NEXT: [1,3] D====================eeeeER sqrdmlah z0.b, z0.b, z1.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 11.0 0.0 0.0 sqrdmlah z0.b, z1.b, z2.b
+# CHECK-NEXT: 2. 2 13.0 0.0 0.0 sqrdmlah z0.b, z1.b, z2.b
+# CHECK-NEXT: 3. 2 15.0 0.0 0.0 sqrdmlah z0.b, z0.b, z1.b
+# CHECK-NEXT: 2 11.5 0.1 0.0 <total>
+
+# CHECK: [33] Code Region - Z sqrdmlah.d
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeeER . . . .. mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D====eeeeER . . .. sqrdmlah z0.d, z1.d, z2.d
+# CHECK-NEXT: [0,2] D======eeeeER . . .. sqrdmlah z0.d, z1.d, z2.d
+# CHECK-NEXT: [0,3] D========eeeeER. . .. sqrdmlah z0.d, z0.d, z1.d
+# CHECK-NEXT: [1,0] D============eeeeER . .. mul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D================eeeeER .. sqrdmlah z0.d, z1.d, z2.d
+# CHECK-NEXT: [1,2] D==================eeeeER.. sqrdmlah z0.d, z1.d, z2.d
+# CHECK-NEXT: [1,3] D====================eeeeER sqrdmlah z0.d, z0.d, z1.d
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 11.0 0.0 0.0 sqrdmlah z0.d, z1.d, z2.d
+# CHECK-NEXT: 2. 2 13.0 0.0 0.0 sqrdmlah z0.d, z1.d, z2.d
+# CHECK-NEXT: 3. 2 15.0 0.0 0.0 sqrdmlah z0.d, z0.d, z1.d
+# CHECK-NEXT: 2 11.5 0.1 0.0 <total>
+
+# CHECK: [34] Code Region - Z fcmla ZPmZZ
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeeER . . .. fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: [0,2] D=====eeeeeER . . .. fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: [0,3] D=======eeeeeER. . .. fcmla z0.d, p0/m, z0.d, z1.d, #90
+# CHECK-NEXT: [1,0] D============eeeER . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D===============eeeeeER .. fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: [1,2] D=================eeeeeER.. fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: [1,3] D===================eeeeeER fcmla z0.d, p0/m, z0.d, z1.d, #90
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: 2. 2 12.0 0.0 0.0 fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: 3. 2 14.0 0.0 0.0 fcmla z0.d, p0/m, z0.d, z1.d, #90
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [35] Code Region - Z fcmla ZZZI
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeeER . . .. fcmla z0.s, z1.s, z2.s[1], #90
+# CHECK-NEXT: [0,2] D=====eeeeeER . . .. fcmla z0.s, z1.s, z2.s[1], #90
+# CHECK-NEXT: [0,3] D=======eeeeeER. . .. fcmla z0.s, z0.s, z1.s[1], #90
+# CHECK-NEXT: [1,0] D============eeeER . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D===============eeeeeER .. fcmla z0.s, z1.s, z2.s[1], #90
+# CHECK-NEXT: [1,2] D=================eeeeeER.. fcmla z0.s, z1.s, z2.s[1], #90
+# CHECK-NEXT: [1,3] D===================eeeeeER fcmla z0.s, z0.s, z1.s[1], #90
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 fcmla z0.s, z1.s, z2.s[1], #90
+# CHECK-NEXT: 2. 2 12.0 0.0 0.0 fcmla z0.s, z1.s, z2.s[1], #90
+# CHECK-NEXT: 3. 2 14.0 0.0 0.0 fcmla z0.s, z0.s, z1.s[1], #90
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [36] Code Region - Z fmla ZPmZZ
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1103
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeER . . . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeER. . . . fmla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [0,2] D=====eeeeER . . . fmla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [0,3] D=======eeeeER . . . fmla z0.d, p0/m, z0.d, z1.d
+# CHECK-NEXT: [1,0] D===========eeeER . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . fmla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [1,2] D================eeeeER . fmla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: [1,3] D==================eeeeER fmla z0.d, p0/m, z0.d, z1.d
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.5 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 fmla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: 2. 2 11.5 0.0 0.0 fmla z0.d, p0/m, z1.d, z2.d
+# CHECK-NEXT: 3. 2 13.5 0.0 0.0 fmla z0.d, p0/m, z0.d, z1.d
+# CHECK-NEXT: 2 10.3 0.1 0.0 <total>
+
+# CHECK: [37] Code Region - Z fmla ZZZI
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1103
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeER . . . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeER. . . . fmla z0.d, z1.d, z2.d[1]
+# CHECK-NEXT: [0,2] D=====eeeeER . . . fmla z0.d, z1.d, z2.d[1]
+# CHECK-NEXT: [0,3] D=======eeeeER . . . fmla z0.d, z0.d, z1.d[1]
+# CHECK-NEXT: [1,0] D===========eeeER . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . fmla z0.d, z1.d, z2.d[1]
+# CHECK-NEXT: [1,2] D================eeeeER . fmla z0.d, z1.d, z2.d[1]
+# CHECK-NEXT: [1,3] D==================eeeeER fmla z0.d, z0.d, z1.d[1]
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.5 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 fmla z0.d, z1.d, z2.d[1]
+# CHECK-NEXT: 2. 2 11.5 0.0 0.0 fmla z0.d, z1.d, z2.d[1]
+# CHECK-NEXT: 3. 2 13.5 0.0 0.0 fmla z0.d, z0.d, z1.d[1]
+# CHECK-NEXT: 2 10.3 0.1 0.0 <total>
+
+# CHECK: [38] Code Region - Z fmlalb ZZZ
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeeER . . .. fmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,2] D=====eeeeeER . . .. fmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,3] D=======eeeeeER. . .. fmlalb z0.s, z0.h, z1.h
+# CHECK-NEXT: [1,0] D============eeeER . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D===============eeeeeER .. fmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,2] D=================eeeeeER.. fmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,3] D===================eeeeeER fmlalb z0.s, z0.h, z1.h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 fmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: 2. 2 12.0 0.0 0.0 fmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: 3. 2 14.0 0.0 0.0 fmlalb z0.s, z0.h, z1.h
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [39] Code Region - Z bfdot
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1103
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01234
+
+# CHECK: [0,0] DeeeER . . . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeER. . . . bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,2] D=====eeeeER . . . bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,3] D=======eeeeER . . . bfdot z0.s, z0.h, z1.h
+# CHECK-NEXT: [1,0] D===========eeeER . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D==============eeeeER . bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,2] D================eeeeER . bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,3] D==================eeeeER bfdot z0.s, z0.h, z1.h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 6.5 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 9.5 0.0 0.0 bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: 2. 2 11.5 0.0 0.0 bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: 3. 2 13.5 0.0 0.0 bfdot z0.s, z0.h, z1.h
+# CHECK-NEXT: 2 10.3 0.1 0.0 <total>
+
+# CHECK: [40] Code Region - Z bfmmla
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1403
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.29
+# CHECK-NEXT: IPC: 0.29
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeER . . . . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeeER . . . . bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,2] D======eeeeeER . . . . bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,3] D=========eeeeeER . . . bfmmla z0.s, z0.h, z1.h
+# CHECK-NEXT: [1,0] D==============eeeER. . . fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D=================eeeeeER. . bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,2] D====================eeeeeER . bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,3] D=======================eeeeeER bfmmla z0.s, z0.h, z1.h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 8.0 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 11.0 0.0 0.0 bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: 2. 2 14.0 0.0 0.0 bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: 3. 2 17.0 0.0 0.0 bfmmla z0.s, z0.h, z1.h
+# CHECK-NEXT: 2 12.5 0.1 0.0 <total>
+
+# CHECK: [41] Code Region - bfmlalb
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [0,1] D===eeeeeER . . .. bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,2] D=====eeeeeER . . .. bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [0,3] D=======eeeeeER. . .. bfmlalb z0.s, z0.h, z1.h
+# CHECK-NEXT: [1,0] D============eeeER . .. fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,1] D===============eeeeeER .. bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,2] D=================eeeeeER.. bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: [1,3] D===================eeeeeER bfmlalb z0.s, z0.h, z1.h
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 fmul z0.d, z0.d, z0.d
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: 2. 2 12.0 0.0 0.0 bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: 3. 2 14.0 0.0 0.0 bfmlalb z0.s, z0.h, z1.h
+# CHECK-NEXT: 2 10.8 0.1 0.0 <total>
+
+# CHECK: [42] Code Region - brkn
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER brkn p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [43] Code Region - brkns
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER brkns p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [44] Code Region - sel
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 72
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 5.56
+# CHECK-NEXT: IPC: 5.56
+# CHECK-NEXT: Block RThroughput: 0.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456
+
+# CHECK: [0,0] DeeER.. sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: [0,1] DeeER.. sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: [0,2] DeeER.. sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: [0,3] D==eeER sel z0.s, p15, z0.s, z1.s
+# CHECK-NEXT: [1,0] DeeE--R sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: [1,1] DeeE--R sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: [1,2] DeeE--R sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: [1,3] D==eeER sel z0.s, p15, z0.s, z1.s
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 1.0 1.0 1.0 sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: 1. 2 1.0 1.0 1.0 sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: 2. 2 1.0 1.0 1.0 sel z0.s, p15, z1.s, z2.s
+# CHECK-NEXT: 3. 2 3.0 0.0 0.0 sel z0.s, p15, z0.s, z1.s
+# CHECK-NEXT: 2 1.5 0.8 0.8 <total>
+
+# CHECK: [45] Code Region - and
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER and p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 and p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [46] Code Region - ands
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER ands p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 ands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [47] Code Region - bic
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER bic p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 bic p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [48] Code Region - bics
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER bics p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 bics p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [49] Code Region - eor
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER eor p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 eor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [50] Code Region - eors
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER eors p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 eors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [51] Code Region - nand
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER nand p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 nand p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [52] Code Region - nands
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER nands p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 nands p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [53] Code Region - nor
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER nor p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 nor p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [54] Code Region - nors
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER nors p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 nors p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [55] Code Region - orn
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER orn p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 orn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
+
+# CHECK: [56] Code Region - orns
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 304
+# CHECK-NEXT: Total uOps: 300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,1] D=eeER . orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [0,2] D==eeER . orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,0] D===eeER . orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,1] D====eeER. orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: [1,2] D=====eeER orns p0.b, p15/z, p1.b, p0.b
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 2.5 0.5 0.0 orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1. 2 3.5 0.0 0.0 orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2. 2 4.5 0.0 0.0 orns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3.5 0.2 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fp16fml-instructions.s
new file mode 100644
index 0000000..2a97cef
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fp16fml-instructions.s
@@ -0,0 +1,81 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/fp16fml-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.17 fmlal v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: 1 4 0.17 fmlal v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: 1 4 0.17 fmlal v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: 1 4 0.17 fmlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 fmlal2 v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: 1 4 0.17 fmlal2 v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: 1 4 0.17 fmlal2 v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: 1 4 0.17 fmlal2 v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 fmlsl v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: 1 4 0.17 fmlsl v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: 1 4 0.17 fmlsl v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: 1 4 0.17 fmlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 fmlsl2 v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: 1 4 0.17 fmlsl2 v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: 1 4 0.17 fmlsl2 v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: 1 4 0.17 fmlsl2 v0.4s, v0.4h, v0.4h
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 2.67 2.67 2.67 2.67 2.67 2.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal2 v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal2 v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal2 v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlal2 v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl2 v0.2s, v0.2h, v0.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl2 v0.4s, v0.4h, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl2 v0.2s, v0.2h, v0.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlsl2 v0.4s, v0.4h, v0.4h
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fptoint-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fptoint-instructions.s
new file mode 100644
index 0000000..67882b4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-fptoint-instructions.s
@@ -0,0 +1,73 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/fptoint-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.25 frint32x v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frint32x v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frint32x v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frint32z v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frint32z v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frint32z v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frint64x v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frint64x v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frint64x v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frint64z v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frint64z v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frint64z v0.4s, v0.4s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 3.00 3.00 - 3.00 3.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint32x v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint32x v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint32x v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint32z v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint32z v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint32z v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint64x v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint64x v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint64x v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint64z v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint64z v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frint64z v0.4s, v0.4s
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-i8mm-instructions.s
new file mode 100644
index 0000000..0ed2d90
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-i8mm-instructions.s
@@ -0,0 +1,67 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/i8mm-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.17 smmla v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.17 sudot v0.2s, v0.8b, v0.4b[2]
+# CHECK-NEXT: 1 3 0.17 sudot v0.4s, v0.16b, v0.4b[2]
+# CHECK-NEXT: 1 3 0.17 ummla v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.17 usdot v0.2s, v0.8b, v0.4b[2]
+# CHECK-NEXT: 1 3 0.17 usdot v0.2s, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.17 usdot v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.17 usdot v0.4s, v0.16b, v0.4b[2]
+# CHECK-NEXT: 1 3 0.17 usmmla v0.4s, v0.16b, v0.16b
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 1.50 1.50 1.50 1.50 1.50 1.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smmla v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sudot v0.2s, v0.8b, v0.4b[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sudot v0.4s, v0.16b, v0.4b[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ummla v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usdot v0.2s, v0.8b, v0.4b[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usdot v0.2s, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usdot v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usdot v0.4s, v0.16b, v0.4b[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usmmla v0.4s, v0.16b, v0.16b
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-mte-instructions.s
new file mode 100644
index 0000000..9e84213
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-mte-instructions.s
@@ -0,0 +1,259 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/mte-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.50 U irg x0, x1
+# CHECK-NEXT: 1 2 0.50 U irg sp, x1
+# CHECK-NEXT: 1 2 0.50 U irg x0, sp
+# CHECK-NEXT: 1 2 0.50 U irg x0, x1, x2
+# CHECK-NEXT: 1 2 0.50 U irg sp, x1, x2
+# CHECK-NEXT: 1 2 0.13 addg x0, x1, #0, #1
+# CHECK-NEXT: 1 2 0.13 addg sp, x2, #32, #3
+# CHECK-NEXT: 1 2 0.13 addg x0, sp, #64, #5
+# CHECK-NEXT: 1 2 0.13 addg x3, x4, #1008, #6
+# CHECK-NEXT: 1 2 0.13 addg x5, x6, #112, #15
+# CHECK-NEXT: 1 2 0.13 U subg x0, x1, #0, #1
+# CHECK-NEXT: 1 2 0.13 U subg sp, x2, #32, #3
+# CHECK-NEXT: 1 2 0.13 U subg x0, sp, #64, #5
+# CHECK-NEXT: 1 2 0.13 U subg x3, x4, #1008, #6
+# CHECK-NEXT: 1 2 0.13 U subg x5, x6, #112, #15
+# CHECK-NEXT: 1 1 0.13 gmi x0, x1, x2
+# CHECK-NEXT: 1 1 0.13 gmi x3, sp, x4
+# CHECK-NEXT: 1 1 0.13 gmi xzr, x0, x30
+# CHECK-NEXT: 1 1 0.13 gmi x30, x0, xzr
+# CHECK-NEXT: 1 1 0.13 subp x0, x1, x2
+# CHECK-NEXT: 1 1 0.25 U subps x0, x1, x2
+# CHECK-NEXT: 1 1 0.13 subp x0, sp, sp
+# CHECK-NEXT: 1 1 0.25 U subps x0, sp, sp
+# CHECK-NEXT: 1 1 0.25 U subps xzr, x0, x1
+# CHECK-NEXT: 1 1 0.25 U subps xzr, sp, sp
+# CHECK-NEXT: 1 1 0.50 * stg x0, [x1, #-4096]
+# CHECK-NEXT: 1 1 0.50 * stg x1, [x2, #4080]
+# CHECK-NEXT: 1 1 0.50 * stg x2, [sp, #16]
+# CHECK-NEXT: 1 1 0.50 * stg x3, [x1]
+# CHECK-NEXT: 1 1 0.50 * stg sp, [x1]
+# CHECK-NEXT: 1 1 0.50 * stzg x0, [x1, #-4096]
+# CHECK-NEXT: 1 1 0.50 * stzg x1, [x2, #4080]
+# CHECK-NEXT: 1 1 0.50 * stzg x2, [sp, #16]
+# CHECK-NEXT: 1 1 0.50 * stzg x3, [x1]
+# CHECK-NEXT: 1 1 0.50 * stzg sp, [x1]
+# CHECK-NEXT: 1 1 0.50 * U stg x0, [x1, #-4096]!
+# CHECK-NEXT: 1 1 0.50 * U stg x1, [x2, #4080]!
+# CHECK-NEXT: 1 1 0.50 * U stg x2, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stg sp, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stzg x0, [x1, #-4096]!
+# CHECK-NEXT: 1 1 0.50 * U stzg x1, [x2, #4080]!
+# CHECK-NEXT: 1 1 0.50 * U stzg x2, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stzg sp, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stg x0, [x1], #-4096
+# CHECK-NEXT: 1 1 0.50 * U stg x1, [x2], #4080
+# CHECK-NEXT: 1 1 0.50 * U stg x2, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stg sp, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stzg x0, [x1], #-4096
+# CHECK-NEXT: 1 1 0.50 * U stzg x1, [x2], #4080
+# CHECK-NEXT: 1 1 0.50 * U stzg x2, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stzg sp, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * st2g x0, [x1, #-4096]
+# CHECK-NEXT: 1 1 0.50 * st2g x1, [x2, #4080]
+# CHECK-NEXT: 1 1 0.50 * st2g x2, [sp, #16]
+# CHECK-NEXT: 1 1 0.50 * st2g x3, [x1]
+# CHECK-NEXT: 1 1 0.50 * st2g sp, [x1]
+# CHECK-NEXT: 1 1 0.50 * stz2g x0, [x1, #-4096]
+# CHECK-NEXT: 1 1 0.50 * stz2g x1, [x2, #4080]
+# CHECK-NEXT: 1 1 0.50 * stz2g x2, [sp, #16]
+# CHECK-NEXT: 1 1 0.50 * stz2g x3, [x1]
+# CHECK-NEXT: 1 1 0.50 * stz2g sp, [x1]
+# CHECK-NEXT: 1 1 0.50 * U st2g x0, [x1, #-4096]!
+# CHECK-NEXT: 1 1 0.50 * U st2g x1, [x2, #4080]!
+# CHECK-NEXT: 1 1 0.50 * U st2g x2, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U st2g sp, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stz2g x0, [x1, #-4096]!
+# CHECK-NEXT: 1 1 0.50 * U stz2g x1, [x2, #4080]!
+# CHECK-NEXT: 1 1 0.50 * U stz2g x2, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stz2g sp, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U st2g x0, [x1], #-4096
+# CHECK-NEXT: 1 1 0.50 * U st2g x1, [x2], #4080
+# CHECK-NEXT: 1 1 0.50 * U st2g x2, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U st2g sp, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stz2g x0, [x1], #-4096
+# CHECK-NEXT: 1 1 0.50 * U stz2g x1, [x2], #4080
+# CHECK-NEXT: 1 1 0.50 * U stz2g x2, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stz2g sp, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [x2, #-1024]
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [x2, #1008]
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [sp, #16]
+# CHECK-NEXT: 1 1 0.50 * stgp xzr, x1, [x2, #16]
+# CHECK-NEXT: 1 1 0.50 * stgp x0, xzr, [x2, #16]
+# CHECK-NEXT: 1 1 0.50 * stgp x0, xzr, [x2]
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [x2, #-1024]!
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [x2, #1008]!
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * stgp xzr, x1, [x2, #16]!
+# CHECK-NEXT: 1 1 0.50 * stgp x0, xzr, [x2, #16]!
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [x2], #-1024
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [x2], #1008
+# CHECK-NEXT: 1 1 0.50 * stgp x0, x1, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * stgp xzr, x1, [x2], #16
+# CHECK-NEXT: 1 1 0.50 * stgp x0, xzr, [x2], #16
+# CHECK-NEXT: 1 4 0.25 * ldg x0, [x1]
+# CHECK-NEXT: 1 4 0.25 * ldg x2, [sp, #-4096]
+# CHECK-NEXT: 1 4 0.25 * ldg x3, [x4, #4080]
+# CHECK-NEXT: 1 4 0.25 * U ldgm x0, [x1]
+# CHECK-NEXT: 1 4 0.25 * U ldgm x1, [sp]
+# CHECK-NEXT: 1 4 0.25 * U ldgm xzr, [x2]
+# CHECK-NEXT: 1 1 0.50 * U stgm x0, [x1]
+# CHECK-NEXT: 1 1 0.50 * U stgm x1, [sp]
+# CHECK-NEXT: 1 1 0.50 * U stgm xzr, [x2]
+# CHECK-NEXT: 1 1 0.50 * U stzgm x0, [x1]
+# CHECK-NEXT: 1 1 0.50 * U stzgm x1, [sp]
+# CHECK-NEXT: 1 1 0.50 * U stzgm xzr, [x2]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - 37.00 37.00 1.00 1.00 1.00 1.00 1.50 1.50 38.50 38.50 10.25 10.25 7.75 7.75 7.75 7.75 7.75 7.75 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - irg x0, x1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - irg sp, x1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - irg x0, sp
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - irg x0, x1, x2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - irg sp, x1, x2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - addg x0, x1, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - addg sp, x2, #32, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - addg x0, sp, #64, #5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - addg x3, x4, #1008, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - addg x5, x6, #112, #15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subg x0, x1, #0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subg sp, x2, #32, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subg x0, sp, #64, #5
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subg x3, x4, #1008, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subg x5, x6, #112, #15
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - gmi x0, x1, x2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - gmi x3, sp, x4
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - gmi xzr, x0, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - gmi x30, x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subp x0, x1, x2
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subps x0, x1, x2
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subp x0, sp, sp
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subps x0, sp, sp
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subps xzr, x0, x1
+# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - subps xzr, sp, sp
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stg x0, [x1, #-4096]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stg x1, [x2, #4080]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stg x2, [sp, #16]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stg x3, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stg sp, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzg x0, [x1, #-4096]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzg x1, [x2, #4080]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzg x2, [sp, #16]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzg x3, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzg sp, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg x1, [x2, #4080]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg x2, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg sp, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg x1, [x2, #4080]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg x2, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg sp, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg x0, [x1], #-4096
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg x1, [x2], #4080
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg x2, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stg sp, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg x0, [x1], #-4096
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg x1, [x2], #4080
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg x2, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stzg sp, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - st2g x0, [x1, #-4096]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - st2g x1, [x2, #4080]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - st2g x2, [sp, #16]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - st2g x3, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - st2g sp, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stz2g x0, [x1, #-4096]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stz2g x1, [x2, #4080]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stz2g x2, [sp, #16]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stz2g x3, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stz2g sp, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g x1, [x2, #4080]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g x2, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g sp, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g x1, [x2, #4080]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g x2, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g sp, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g x0, [x1], #-4096
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g x1, [x2], #4080
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g x2, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - st2g sp, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g x0, [x1], #-4096
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g x1, [x2], #4080
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g x2, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stz2g sp, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgp x0, x1, [x2, #-1024]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgp x0, x1, [x2, #1008]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgp x0, x1, [sp, #16]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgp xzr, x1, [x2, #16]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgp x0, xzr, [x2, #16]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgp x0, xzr, [x2]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, x1, [x2, #-1024]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, x1, [x2, #1008]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, x1, [sp, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp xzr, x1, [x2, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, xzr, [x2, #16]!
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, x1, [x2], #-1024
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, x1, [x2], #1008
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, x1, [sp], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp xzr, x1, [x2], #16
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - stgp x0, xzr, [x2], #16
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldg x0, [x1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldg x2, [sp, #-4096]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldg x3, [x4, #4080]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldgm x0, [x1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldgm x1, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldgm xzr, [x2]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgm x0, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgm x1, [sp]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stgm xzr, [x2]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzgm x0, [x1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzgm x1, [sp]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stzgm xzr, [x2]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
new file mode 100644
index 0000000..4af51ef
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
@@ -0,0 +1,3167 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.17 abs d29, d24
+# CHECK-NEXT: 1 2 0.17 abs v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 abs v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 abs v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 abs v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 abs v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 abs v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 abs v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 add d17, d31, d29
+# CHECK-NEXT: 1 2 0.17 add v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 addhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 addhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 addhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 addhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 addhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 addhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 addp v7.2s, v1.2s, v2.2s
+# CHECK-NEXT: 1 2 0.17 addp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 addp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 addp d1, v14.2d
+# CHECK-NEXT: 1 2 0.25 addv s0, v0.4s
+# CHECK-NEXT: 1 2 0.25 addv h0, v0.4h
+# CHECK-NEXT: 1 4 0.25 addv h0, v0.8h
+# CHECK-NEXT: 1 4 0.25 addv b0, v0.8b
+# CHECK-NEXT: 1 4 0.50 addv b0, v0.16b
+# CHECK-NEXT: 1 2 0.25 aesd v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.25 aese v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.25 aesimc v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.25 aesmc v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 and v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 bic v0.4h, #15, lsl #8
+# CHECK-NEXT: 1 2 0.17 bic v23.8h, #101
+# CHECK-NEXT: 1 2 0.17 bic v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 bic v25.16b, v10.16b, v9.16b
+# CHECK-NEXT: 1 2 0.17 bic v24.2s, #70
+# CHECK-NEXT: 1 2 0.17 bit v5.8b, v12.8b, v22.8b
+# CHECK-NEXT: 1 2 0.17 bif v0.8b, v25.8b, v4.8b
+# CHECK-NEXT: 1 2 0.17 bif v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 bit v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 bsl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 bsl v27.16b, v13.16b, v21.16b
+# CHECK-NEXT: 1 2 0.17 cls v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 cls v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 cls v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 cls v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 cls v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 cls v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 clz v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 clz v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 clz v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 clz v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 clz v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 clz v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 cmeq v9.8h, v16.8h, v24.8h
+# CHECK-NEXT: 1 2 0.17 cmeq v14.4h, v18.4h, #0
+# CHECK-NEXT: 1 2 0.17 cmeq d20, d21, #0
+# CHECK-NEXT: 1 2 0.17 cmeq d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 cmeq v0.16b, v0.16b, #0
+# CHECK-NEXT: 1 2 0.17 cmeq v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 cmge v22.8h, v16.8h, v3.8h
+# CHECK-NEXT: 1 2 0.17 cmge v22.16b, v30.16b, #0
+# CHECK-NEXT: 1 2 0.17 cmge d20, d21, #0
+# CHECK-NEXT: 1 2 0.17 cmge d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 cmge v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 cmge v0.8b, v0.8b, #0
+# CHECK-NEXT: 1 2 0.17 cmgt v3.2d, v29.2d, v11.2d
+# CHECK-NEXT: 1 2 0.17 cmgt d20, d21, #0
+# CHECK-NEXT: 1 2 0.17 cmgt d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 cmgt v0.2s, v0.2s, #0
+# CHECK-NEXT: 1 2 0.17 cmgt v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 cmhi v28.4h, v25.4h, v21.4h
+# CHECK-NEXT: 1 2 0.17 cmhi d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 cmhi v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 cmhs d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 cmhs v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 cmle v21.2s, v19.2s, #0
+# CHECK-NEXT: 1 2 0.17 cmle d20, d21, #0
+# CHECK-NEXT: 1 2 0.17 cmle v0.2d, v0.2d, #0
+# CHECK-NEXT: 1 2 0.17 cmlt v26.4h, v12.4h, #0
+# CHECK-NEXT: 1 2 0.17 cmlt d20, d21, #0
+# CHECK-NEXT: 1 2 0.17 cmlt v0.8h, v0.8h, #0
+# CHECK-NEXT: 1 2 0.17 cmtst d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 cmtst v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 cmtst v13.2d, v13.2d, v13.2d
+# CHECK-NEXT: 1 2 0.17 cnt v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 cnt v0.8b, v0.8b
+# CHECK-NEXT: 1 3 1.00 dup v0.16b, w28
+# CHECK-NEXT: 1 3 1.00 dup v0.2d, x28
+# CHECK-NEXT: 1 3 1.00 dup v0.2s, w28
+# CHECK-NEXT: 1 3 1.00 dup v0.4h, w28
+# CHECK-NEXT: 1 3 1.00 dup v0.4s, w28
+# CHECK-NEXT: 1 3 1.00 dup v0.8b, w28
+# CHECK-NEXT: 1 3 1.00 dup v0.8h, w28
+# CHECK-NEXT: 1 2 0.17 mov b0, v0.b[1]
+# CHECK-NEXT: 1 2 0.17 mov d0, v0.d[1]
+# CHECK-NEXT: 1 2 0.17 mov h0, v0.h[1]
+# CHECK-NEXT: 1 2 0.17 mov s0, v0.s[1]
+# CHECK-NEXT: 1 2 0.17 dup v0.16b, v0.b[1]
+# CHECK-NEXT: 1 2 0.17 dup v0.2d, v0.d[1]
+# CHECK-NEXT: 1 2 0.17 dup v0.2s, v0.s[1]
+# CHECK-NEXT: 1 2 0.17 dup v0.4h, v0.h[1]
+# CHECK-NEXT: 1 2 0.17 dup v0.4s, v0.s[1]
+# CHECK-NEXT: 1 2 0.17 dup v0.8b, v0.b[1]
+# CHECK-NEXT: 1 2 0.17 dup v0.8h, v0.h[1]
+# CHECK-NEXT: 1 2 0.17 eor v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 ext v0.16b, v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.17 ext v0.8b, v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.17 fabd d29, d24, d20
+# CHECK-NEXT: 1 2 0.17 fabd s29, s24, s20
+# CHECK-NEXT: 1 2 0.17 fabd h27, h20, h17
+# CHECK-NEXT: 1 2 0.17 fabd v13.8h, v28.8h, v12.8h
+# CHECK-NEXT: 1 2 0.17 fabd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 fabs h25, h7
+# CHECK-NEXT: 1 2 0.17 fabs v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 fabs v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 fabs v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 fabs v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 fabs v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 facge d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 facge s10, s11, s12
+# CHECK-NEXT: 1 2 0.17 facge h24, h26, h29
+# CHECK-NEXT: 1 2 0.17 facge v25.4h, v16.4h, v11.4h
+# CHECK-NEXT: 1 2 0.17 facge v19.2s, v24.2s, v5.2s
+# CHECK-NEXT: 1 2 0.17 facge v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 facgt d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 facgt s10, s11, s12
+# CHECK-NEXT: 1 2 0.17 facgt h0, h4, h10
+# CHECK-NEXT: 1 2 0.17 facgt v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 facgt v22.8h, v14.8h, v31.8h
+# CHECK-NEXT: 1 2 0.17 facgt v22.4s, v8.4s, v2.4s
+# CHECK-NEXT: 1 2 0.17 fadd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 faddp h10, v19.2h
+# CHECK-NEXT: 1 2 0.17 faddp d11, v28.2d
+# CHECK-NEXT: 1 2 0.17 faddp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 faddp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 faddp v16.2d, v11.2d, v5.2d
+# CHECK-NEXT: 1 2 0.17 fcmeq h30, h6, h1
+# CHECK-NEXT: 1 2 0.17 fcmeq h19, h23, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmeq d20, d21, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmeq d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 fcmeq s10, s11, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmeq s10, s11, s12
+# CHECK-NEXT: 1 2 0.17 fcmeq v0.2s, v0.2s, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmeq v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 fcmeq v12.4s, v11.4s, v26.4s
+# CHECK-NEXT: 1 2 0.17 fcmeq v18.2d, v17.2d, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmge h10, h23, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmge h1, h16, h12
+# CHECK-NEXT: 1 2 0.17 fcmge d20, d21, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmge d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 fcmge s10, s11, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmge s10, s11, s12
+# CHECK-NEXT: 1 2 0.17 fcmge v0.2d, v0.2d, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmge v17.2d, v11.2d, v13.2d
+# CHECK-NEXT: 1 2 0.17 fcmge v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 fcmge v18.4h, v27.4h, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmge v20.8h, v19.8h, v22.8h
+# CHECK-NEXT: 1 2 0.17 fcmge v17.2s, v11.2s, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmgt h4, h5, h0
+# CHECK-NEXT: 1 2 0.17 fcmgt h0, h18, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmgt d20, d21, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmgt d20, d21, d22
+# CHECK-NEXT: 1 2 0.17 fcmgt s10, s11, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmgt s10, s11, s12
+# CHECK-NEXT: 1 2 0.17 fcmgt v0.4s, v0.4s, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmgt v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 fcmgt v24.8h, v24.8h, v28.8h
+# CHECK-NEXT: 1 2 0.17 fcmgt v0.8h, v11.8h, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmgt v19.2d, v31.2d, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmle v16.8h, v11.8h, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmle v22.4s, v30.4s, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmle d20, d21, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmle s10, s11, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmle v0.2d, v0.2d, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmle h18, h28, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmlt h23, h7, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmlt d20, d21, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmlt s10, s11, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmlt v0.4s, v0.4s, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmlt v8.4h, v2.4h, #0.0
+# CHECK-NEXT: 1 2 0.17 fcmlt v7.2d, v16.2d, #0.0
+# CHECK-NEXT: 1 3 0.25 fcvtas d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtas s12, s13
+# CHECK-NEXT: 1 3 0.25 fcvtas h12, h13
+# CHECK-NEXT: 1 3 0.25 fcvtas v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtas v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtas v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtas v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtas v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtau d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtau s12, s13
+# CHECK-NEXT: 1 3 0.25 fcvtau h12, h13
+# CHECK-NEXT: 1 3 0.25 fcvtau v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtau v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtau v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtau v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtau v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtl v0.2d, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtl v0.4s, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtl2 v0.2d, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtl2 v0.4s, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtms d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtms s22, s13
+# CHECK-NEXT: 1 3 0.25 fcvtms h22, h13
+# CHECK-NEXT: 1 3 0.25 fcvtms v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtms v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtms v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtms v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtms v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtmu d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtmu s12, s13
+# CHECK-NEXT: 1 3 0.25 fcvtmu h12, h13
+# CHECK-NEXT: 1 3 0.25 fcvtmu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtmu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtmu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtmu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtmu v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtn v0.2s, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtn v0.4h, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtns d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtns s22, s13
+# CHECK-NEXT: 1 3 0.25 fcvtns h22, h13
+# CHECK-NEXT: 1 3 0.25 fcvtns v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtns v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtns v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtns v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtns v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtnu d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtnu s12, s13
+# CHECK-NEXT: 1 3 0.25 fcvtnu h12, h13
+# CHECK-NEXT: 1 3 0.25 fcvtnu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtnu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtnu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtnu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtnu v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtps d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtps s22, s13
+# CHECK-NEXT: 1 3 0.25 fcvtps h22, h13
+# CHECK-NEXT: 1 3 0.25 fcvtps v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtps v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtps v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtps v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtps v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtpu d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtpu s12, s13
+# CHECK-NEXT: 1 3 0.25 fcvtpu h12, h13
+# CHECK-NEXT: 1 3 0.25 fcvtpu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtpu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtpu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtpu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtpu v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtxn s22, d13
+# CHECK-NEXT: 1 3 0.25 fcvtxn v0.2s, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtxn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtzs d21, d12, #1
+# CHECK-NEXT: 1 3 0.25 fcvtzs d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtzs s12, s13
+# CHECK-NEXT: 1 3 0.25 fcvtzs s21, s12, #1
+# CHECK-NEXT: 1 3 0.25 fcvtzs h21, h14
+# CHECK-NEXT: 1 3 0.25 fcvtzs h21, h12, #1
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtzs v20.4h, v24.4h, #11
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.25 fcvtzs v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtzs v18.8h, v10.8h, #7
+# CHECK-NEXT: 1 3 0.25 fcvtzu d21, d12, #1
+# CHECK-NEXT: 1 3 0.25 fcvtzu d21, d14
+# CHECK-NEXT: 1 3 0.25 fcvtzu s12, s13
+# CHECK-NEXT: 1 3 0.25 fcvtzu s21, s12, #1
+# CHECK-NEXT: 1 3 0.25 fcvtzu h12, h13
+# CHECK-NEXT: 1 3 0.25 fcvtzu h21, h12, #1
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 fcvtzu v19.4h, v26.4h, #9
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.25 fcvtzu v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 fcvtzu v27.8h, v6.8h, #11
+# CHECK-NEXT: 1 13 2.00 fdiv v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 9 2.00 fdiv v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 8 4.00 fdiv v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 11 4.00 fdiv v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 12 8.00 fdiv v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 fmax v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 fmax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 fmax v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 fmaxnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 fmaxnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 fmaxnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.17 fmaxnmp h25, v19.2h
+# CHECK-NEXT: 1 3 0.17 fmaxnmp d17, v29.2d
+# CHECK-NEXT: 1 3 0.17 fmaxnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.17 fmaxnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.17 fmaxnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.33 fmaxnmv h0, v13.4h
+# CHECK-NEXT: 1 6 0.50 fmaxnmv h12, v11.8h
+# CHECK-NEXT: 1 4 0.33 fmaxnmv s28, v31.4s
+# CHECK-NEXT: 1 3 0.17 fmaxp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.17 fmaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.17 fmaxp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.17 fmaxp h15, v25.2h
+# CHECK-NEXT: 1 3 0.17 fmaxp s6, v2.2s
+# CHECK-NEXT: 1 4 0.33 fmaxv h0, v0.4h
+# CHECK-NEXT: 1 6 0.50 fmaxv h0, v0.8h
+# CHECK-NEXT: 1 4 0.33 fmaxv s0, v0.4s
+# CHECK-NEXT: 1 2 0.17 fmin v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 fmin v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 fmin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 fminnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 fminnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 fminnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.17 fminnmp h20, v14.2h
+# CHECK-NEXT: 1 3 0.17 fminnmp d15, v8.2d
+# CHECK-NEXT: 1 3 0.17 fminnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.17 fminnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.17 fminnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.33 fminnmv h19, v25.4h
+# CHECK-NEXT: 1 6 0.50 fminnmv h23, v17.8h
+# CHECK-NEXT: 1 4 0.33 fminnmv s29, v17.4s
+# CHECK-NEXT: 1 3 0.17 fminp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.17 fminp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.17 fminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.17 fminp h7, v10.2h
+# CHECK-NEXT: 1 3 0.17 fminp s17, v7.2s
+# CHECK-NEXT: 1 4 0.33 fminv h3, v30.4h
+# CHECK-NEXT: 1 6 0.50 fminv h29, v12.8h
+# CHECK-NEXT: 1 4 0.33 fminv s16, v19.4s
+# CHECK-NEXT: 1 4 0.17 fmla d0, d1, v0.d[1]
+# CHECK-NEXT: 1 4 0.17 fmla h23, h24, v15.h[4]
+# CHECK-NEXT: 1 4 0.17 fmla s0, s1, v0.s[3]
+# CHECK-NEXT: 1 4 0.17 fmla v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.17 fmla v29.8h, v15.8h, v10.h[4]
+# CHECK-NEXT: 1 4 0.17 fmla v2.2s, v16.2s, v28.s[0]
+# CHECK-NEXT: 1 4 0.17 fmla v14.4s, v14.4s, v5.s[3]
+# CHECK-NEXT: 1 4 0.17 fmla v1.4s, v24.4s, v12.4s
+# CHECK-NEXT: 1 4 0.17 fmla v10.2d, v14.2d, v21.d[1]
+# CHECK-NEXT: 1 4 0.17 fmls d0, d4, v0.d[1]
+# CHECK-NEXT: 1 4 0.17 fmls h8, h14, v7.h[4]
+# CHECK-NEXT: 1 4 0.17 fmls s3, s5, v0.s[3]
+# CHECK-NEXT: 1 4 0.17 fmls v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.17 fmls v30.8h, v18.8h, v4.h[6]
+# CHECK-NEXT: 1 4 0.17 fmls v10.2s, v27.2s, v0.s[0]
+# CHECK-NEXT: 1 4 0.17 fmls v27.4s, v7.4s, v24.s[0]
+# CHECK-NEXT: 1 4 0.17 fmls v10.2d, v22.2d, v29.d[0]
+# CHECK-NEXT: 1 4 0.17 fmls v6.8h, v15.8h, v23.8h
+# CHECK-NEXT: 1 2 0.17 fmov v0.2d, #-1.25000000
+# CHECK-NEXT: 1 2 0.17 fmov v0.2s, #13.00000000
+# CHECK-NEXT: 1 2 0.17 fmov v0.4s, #1.00000000
+# CHECK-NEXT: 1 3 0.17 fmul h18, h4, v7.h[3]
+# CHECK-NEXT: 1 3 0.17 fmul v10.4h, v2.4h, v7.h[5]
+# CHECK-NEXT: 1 3 0.17 fmul v5.2s, v12.2s, v9.s[0]
+# CHECK-NEXT: 1 3 0.17 fmul v15.4s, v30.4s, v2.s[3]
+# CHECK-NEXT: 1 3 0.17 fmul v11.2d, v31.2d, v24.d[1]
+# CHECK-NEXT: 1 3 0.17 fmul h28, h14, h3
+# CHECK-NEXT: 1 3 0.17 fmul d0, d1, v0.d[1]
+# CHECK-NEXT: 1 3 0.17 fmul s0, s1, v0.s[3]
+# CHECK-NEXT: 1 3 0.17 fmul v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.17 fmulx d0, d4, v0.d[1]
+# CHECK-NEXT: 1 3 0.17 fmulx d23, d11, d1
+# CHECK-NEXT: 1 3 0.17 fmulx s20, s22, s15
+# CHECK-NEXT: 1 3 0.17 fmulx h18, h17, v7.h[1]
+# CHECK-NEXT: 1 3 0.17 fmulx h20, h25, h0
+# CHECK-NEXT: 1 3 0.17 fmulx s3, s5, v0.s[3]
+# CHECK-NEXT: 1 3 0.17 fmulx v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.17 fmulx v28.4h, v25.4h, v15.h[1]
+# CHECK-NEXT: 1 3 0.17 fmulx v3.2s, v22.2s, v23.s[3]
+# CHECK-NEXT: 1 3 0.17 fmulx v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.17 fmulx v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.17 fmulx v5.4s, v28.4s, v15.s[3]
+# CHECK-NEXT: 1 3 0.17 fmulx v22.2d, v18.2d, v25.d[1]
+# CHECK-NEXT: 1 2 0.17 fneg v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 fneg v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 fneg v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 fneg v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 fneg v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frecpe h20, h8
+# CHECK-NEXT: 1 3 0.25 frecpe d13, d13
+# CHECK-NEXT: 1 3 0.25 frecpe s19, s14
+# CHECK-NEXT: 1 3 0.25 frecpe v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frecpe v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 frecpe v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.50 frecpe v0.4s, v0.4s
+# CHECK-NEXT: 1 6 1.00 frecpe v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 frecps h29, h19, h8
+# CHECK-NEXT: 1 3 0.25 frecpx h18, h11
+# CHECK-NEXT: 1 4 0.17 frecps v12.8h, v25.8h, v4.8h
+# CHECK-NEXT: 1 4 0.17 frecps v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 frecps d22, d30, d21
+# CHECK-NEXT: 1 4 0.17 frecps s21, s16, s13
+# CHECK-NEXT: 1 4 0.17 frecps v7.2d, v29.2d, v18.2d
+# CHECK-NEXT: 1 3 0.25 frecpx d16, d19
+# CHECK-NEXT: 1 3 0.25 frecpx s18, s10
+# CHECK-NEXT: 1 3 0.25 frinta v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frinta v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frinta v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 frinta v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frinta v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frinti v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frinti v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frinti v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 frinti v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frinti v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frintm v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frintm v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frintm v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 frintm v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frintm v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frintn v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frintn v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frintn v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 frintn v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frintn v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frintp v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frintp v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frintp v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 frintp v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frintp v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frintx v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frintx v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frintx v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 frintx v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frintx v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frintz v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frintz v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 frintz v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 frintz v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 frintz v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 frsqrte h23, h26
+# CHECK-NEXT: 1 3 0.25 frsqrte d21, d12
+# CHECK-NEXT: 1 3 0.25 frsqrte s22, s13
+# CHECK-NEXT: 1 3 0.25 frsqrte v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 frsqrte v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 frsqrte v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.50 frsqrte v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 frsqrts v20.4s, v26.4s, v27.4s
+# CHECK-NEXT: 1 4 0.17 frsqrts v8.4h, v9.4h, v30.4h
+# CHECK-NEXT: 1 6 1.00 frsqrte v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 frsqrts h28, h26, h1
+# CHECK-NEXT: 1 4 0.17 frsqrts d8, d22, d18
+# CHECK-NEXT: 1 4 0.17 frsqrts s21, s5, s12
+# CHECK-NEXT: 1 4 0.17 frsqrts v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 13 2.00 fsqrt v0.2d, v0.2d
+# CHECK-NEXT: 1 9 2.00 fsqrt v0.2s, v0.2s
+# CHECK-NEXT: 1 8 4.00 fsqrt v0.4h, v0.4h
+# CHECK-NEXT: 1 11 4.00 fsqrt v0.4s, v0.4s
+# CHECK-NEXT: 1 12 8.00 fsqrt v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 fsub v13.8h, v15.8h, v17.8h
+# CHECK-NEXT: 1 2 0.17 fsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 6 0.25 * ld1 { v0.16b }, [x0]
+# CHECK-NEXT: 1 6 0.50 * ld1 { v0.16b, v1.16b }, [x14]
+# CHECK-NEXT: 1 6 0.75 * ld1 { v19.16b, v20.16b, v21.16b }, [x10]
+# CHECK-NEXT: 1 6 1.00 * ld1 { v13.16b, v14.16b, v15.16b, v16.16b }, [x9]
+# CHECK-NEXT: 1 6 0.25 * ld1 { v24.8h }, [x27]
+# CHECK-NEXT: 1 6 0.50 * ld1 { v1.8h, v2.8h }, [x27]
+# CHECK-NEXT: 2 6 0.50 * ld1 { v0.8h, v1.8h }, [sp], #32
+# CHECK-NEXT: 1 6 0.75 * ld1 { v21.8h, v22.8h, v23.8h }, [x22]
+# CHECK-NEXT: 1 6 1.00 * ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x21]
+# CHECK-NEXT: 1 6 0.25 * ld1 { v3.4s }, [x4]
+# CHECK-NEXT: 1 6 0.50 * ld1 { v11.4s, v12.4s }, [x30]
+# CHECK-NEXT: 1 6 0.75 * ld1 { v0.4s, v1.4s, v2.4s }, [x24]
+# CHECK-NEXT: 1 6 1.00 * ld1 { v15.4s, v16.4s, v17.4s, v18.4s }, [x28]
+# CHECK-NEXT: 2 6 0.75 * ld1 { v0.4s, v1.4s, v2.4s }, [x0], #48
+# CHECK-NEXT: 1 6 0.25 * ld1 { v3.2d }, [x28]
+# CHECK-NEXT: 1 6 0.50 * ld1 { v13.2d, v14.2d }, [x13]
+# CHECK-NEXT: 1 6 0.75 * ld1 { v12.2d, v13.2d, v14.2d }, [x15]
+# CHECK-NEXT: 2 6 0.75 * ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: 1 6 1.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: 2 6 0.25 * ld1 { v0.1d }, [x15], x2
+# CHECK-NEXT: 1 6 0.50 * ld1 { v27.1d, v28.1d }, [x7]
+# CHECK-NEXT: 1 6 0.75 * ld1 { v14.1d, v15.1d, v16.1d }, [x3]
+# CHECK-NEXT: 1 6 1.00 * ld1 { v22.1d, v23.1d, v24.1d, v25.1d }, [x4]
+# CHECK-NEXT: 1 6 0.50 * ld1 { v0.2s, v1.2s }, [x15]
+# CHECK-NEXT: 1 6 0.75 * ld1 { v16.2s, v17.2s, v18.2s }, [x27]
+# CHECK-NEXT: 1 6 1.00 * ld1 { v21.2s, v22.2s, v23.2s, v24.2s }, [x21]
+# CHECK-NEXT: 1 6 0.50 * ld1 { v25.4h, v26.4h }, [x3]
+# CHECK-NEXT: 1 6 1.00 * ld1 { v20.4h, v21.4h, v22.4h, v23.4h }, [x15]
+# CHECK-NEXT: 1 6 0.75 * ld1 { v0.4h, v1.4h, v2.4h }, [sp]
+# CHECK-NEXT: 1 6 0.50 * ld1 { v24.8b, v25.8b }, [x6]
+# CHECK-NEXT: 1 6 0.75 * ld1 { v7.8b, v8.8b, v9.8b }, [x12]
+# CHECK-NEXT: 1 6 1.00 * ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x13]
+# CHECK-NEXT: 2 6 0.50 * ld1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: 1 6 0.75 * ld1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: 2 7 1.00 * ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: 1 6 0.25 * ld1 { v0.b }[7], [x0]
+# CHECK-NEXT: 2 6 0.25 * ld1 { v0.h }[3], [x0], #2
+# CHECK-NEXT: 1 6 0.25 * ld1 { v18.h }[3], [x1]
+# CHECK-NEXT: 1 6 0.25 * ld1 { v0.s }[1], [x15]
+# CHECK-NEXT: 2 6 0.25 * ld1 { v0.d }[0], [x15], #8
+# CHECK-NEXT: 1 6 0.25 * ld1 { v11.d }[0], [x13]
+# CHECK-NEXT: 2 6 0.25 * ld1 { v0.8h }, [x15], x2
+# CHECK-NEXT: 1 6 0.50 * ld1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: 1 6 0.25 * ld1 { v0.b }[9], [x0]
+# CHECK-NEXT: 2 6 0.25 * ld1 { v0.b }[9], [x0], #1
+# CHECK-NEXT: 1 6 0.25 * ld1r { v0.16b }, [x0]
+# CHECK-NEXT: 2 6 0.25 * ld1r { v0.8h }, [x0], #2
+# CHECK-NEXT: 1 6 0.25 * ld1r { v0.4s }, [x15]
+# CHECK-NEXT: 1 6 0.25 * ld1r { v3.1d }, [x15]
+# CHECK-NEXT: 2 6 0.25 * ld1r { v0.2d }, [x15], x16
+# CHECK-NEXT: 1 6 0.25 * ld1r { v18.2d }, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1r { v8.8b }, [x23]
+# CHECK-NEXT: 1 6 0.25 * ld1r { v28.4h }, [x9]
+# CHECK-NEXT: 1 6 0.25 * ld1r { v3.8h }, [x16]
+# CHECK-NEXT: 1 6 0.25 * ld1r { v10.2s }, [x20]
+# CHECK-NEXT: 1 8 0.33 * ld2 { v0.4h, v1.4h }, [x21]
+# CHECK-NEXT: 1 8 0.50 * ld2 { v8.8h, v9.8h }, [x28]
+# CHECK-NEXT: 1 8 0.33 * ld2 { v2.2s, v3.2s }, [x16]
+# CHECK-NEXT: 1 8 0.50 * ld2 { v22.4s, v23.4s }, [x4]
+# CHECK-NEXT: 1 8 0.50 * ld2 { v22.2d, v23.2d }, [x17]
+# CHECK-NEXT: 1 8 0.33 * ld2 { v29.b, v30.b }[3], [x1]
+# CHECK-NEXT: 1 8 0.33 * ld2 { v26.s, v27.s }[1], [x17]
+# CHECK-NEXT: 1 8 0.33 * ld2 { v1.d, v2.d }[0], [x10]
+# CHECK-NEXT: 1 8 0.50 * ld2 { v0.16b, v1.16b }, [x0]
+# CHECK-NEXT: 1 8 0.33 * ld2 { v13.8b, v14.8b }, [x4]
+# CHECK-NEXT: 2 8 0.33 * ld2 { v0.8b, v1.8b }, [x0], #16
+# CHECK-NEXT: 2 6 0.25 * ld1r { v0.16b }, [x0], #1
+# CHECK-NEXT: 1 6 0.25 * ld1r { v0.8h }, [x15]
+# CHECK-NEXT: 2 6 0.25 * ld1r { v0.8h }, [x15], #2
+# CHECK-NEXT: 2 8 0.50 * ld2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: 1 8 0.33 * ld2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: 1 8 0.33 * ld2 { v0.h, v1.h }[7], [x15]
+# CHECK-NEXT: 2 8 0.33 * ld2 { v0.h, v1.h }[7], [x15], x8
+# CHECK-NEXT: 2 8 0.33 * ld2 { v0.h, v1.h }[7], [x15], #4
+# CHECK-NEXT: 1 8 0.33 * ld2r { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: 1 8 0.33 * ld2r { v10.16b, v11.16b }, [x23]
+# CHECK-NEXT: 2 8 0.33 * ld2r { v0.4h, v1.4h }, [x0], #4
+# CHECK-NEXT: 1 8 0.33 * ld2r { v25.4h, v26.4h }, [x11]
+# CHECK-NEXT: 1 8 0.33 * ld2r { v23.8h, v24.8h }, [x10]
+# CHECK-NEXT: 1 8 0.33 * ld2r { v0.2s, v1.2s }, [sp]
+# CHECK-NEXT: 1 8 0.33 * ld2r { v8.4s, v9.4s }, [x17]
+# CHECK-NEXT: 2 8 0.33 * ld2r { v0.1d, v1.1d }, [sp], x8
+# CHECK-NEXT: 1 8 0.33 * ld2r { v9.1d, v10.1d }, [x25]
+# CHECK-NEXT: 1 8 0.33 * ld2r { v26.2d, v27.2d }, [x8]
+# CHECK-NEXT: 1 9 0.50 * ld3 { v8.8b, v9.8b, v10.8b }, [x0]
+# CHECK-NEXT: 1 9 0.75 * ld3 { v15.16b, v16.16b, v17.16b }, [x5]
+# CHECK-NEXT: 1 8 0.33 * ld2r { v0.2d, v1.2d }, [x0]
+# CHECK-NEXT: 2 8 0.33 * ld2r { v0.2d, v1.2d }, [x0], #16
+# CHECK-NEXT: 1 8 0.33 * ld2r { v0.4s, v1.4s }, [sp]
+# CHECK-NEXT: 2 8 0.33 * ld2r { v0.4s, v1.4s }, [sp], #8
+# CHECK-NEXT: 1 9 0.50 * ld3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 2 9 0.75 * ld3 { v0.8h, v1.8h, v2.8h }, [x15], #48
+# CHECK-NEXT: 1 9 0.75 * ld3 { v7.8h, v8.8h, v9.8h }, [x21]
+# CHECK-NEXT: 1 9 0.50 * ld3 { v16.2s, v17.2s, v18.2s }, [x0]
+# CHECK-NEXT: 1 9 0.75 * ld3 { v12.4s, v13.4s, v14.4s }, [x25]
+# CHECK-NEXT: 1 9 0.50 * ld3 { v17.b, v18.b, v19.b }[2], [x27]
+# CHECK-NEXT: 1 9 0.50 * ld3 { v18.h, v19.h, v20.h }[5], [x16]
+# CHECK-NEXT: 1 9 0.75 * ld3 { v10.2d, v11.2d, v12.2d }, [x18]
+# CHECK-NEXT: 2 9 0.75 * ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: 1 9 0.50 * ld3 { v0.s, v1.s, v2.s }[3], [sp]
+# CHECK-NEXT: 2 9 0.50 * ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
+# CHECK-NEXT: 1 9 0.50 * ld3 { v5.d, v6.d, v7.d }[1], [x14]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v0.8b, v1.8b, v2.8b }, [x15]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v17.16b, v18.16b, v19.16b }, [x3]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 2 8 0.50 * ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
+# CHECK-NEXT: 1 8 0.50 * ld3r { v3.4h, v4.4h, v5.4h }, [x1]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v6.8h, v7.8h, v8.8h }, [x28]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v0.2s, v1.2s, v2.2s }, [x0]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v28.4s, v29.4s, v30.4s }, [x2]
+# CHECK-NEXT: 2 8 0.50 * ld3r { v0.1d, v1.1d, v2.1d }, [x0], x0
+# CHECK-NEXT: 1 8 0.50 * ld3r { v1.1d, v2.1d, v3.1d }, [x28]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v8.2d, v9.2d, v10.2d }, [x3]
+# CHECK-NEXT: 1 8 0.67 * ld4 { v6.8b, v7.8b, v8.8b, v9.8b }, [x27]
+# CHECK-NEXT: 1 9 1.33 * ld4 { v11.16b, v12.16b, v13.16b, v14.16b }, [x5]
+# CHECK-NEXT: 1 8 0.67 * ld4 { v21.4h, v22.4h, v23.4h, v24.4h }, [x14]
+# CHECK-NEXT: 1 9 1.33 * ld4 { v9.8h, v10.8h, v11.8h, v12.8h }, [x1]
+# CHECK-NEXT: 1 9 1.33 * ld4 { v17.4s, v18.4s, v19.4s, v20.4s }, [x4]
+# CHECK-NEXT: 1 8 0.50 * ld3r { v0.8b, v1.8b, v2.8b }, [x0]
+# CHECK-NEXT: 2 8 0.50 * ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
+# CHECK-NEXT: 1 8 0.67 * ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 2 9 1.33 * ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: 1 8 0.67 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
+# CHECK-NEXT: 1 9 1.33 * ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x24]
+# CHECK-NEXT: 1 8 0.67 * ld4 { v4.b, v5.b, v6.b, v7.b }[12], [x27]
+# CHECK-NEXT: 1 8 0.67 * ld4 { v5.h, v6.h, v7.h, v8.h }[0], [x4]
+# CHECK-NEXT: 2 8 0.67 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
+# CHECK-NEXT: 2 8 0.67 * ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
+# CHECK-NEXT: 1 8 0.67 * ld4 { v0.s, v1.s, v2.s, v3.s }[0], [x26]
+# CHECK-NEXT: 1 8 0.67 * ld4r { v20.8b, v21.8b, v22.8b, v23.8b }, [x23]
+# CHECK-NEXT: 1 8 0.67 * ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x25]
+# CHECK-NEXT: 1 8 0.67 * ld4r { v16.4h, v17.4h, v18.4h, v19.4h }, [x6]
+# CHECK-NEXT: 1 8 0.67 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
+# CHECK-NEXT: 1 8 0.67 * ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
+# CHECK-NEXT: 1 8 0.67 * ld4r { v4.8h, v5.8h, v6.8h, v7.8h }, [x23]
+# CHECK-NEXT: 1 8 0.67 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x30]
+# CHECK-NEXT: 2 8 0.67 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #16
+# CHECK-NEXT: 1 8 0.67 * ld4r { v7.4s, v8.4s, v9.4s, v10.4s }, [x23]
+# CHECK-NEXT: 2 8 0.67 * ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], x8
+# CHECK-NEXT: 2 8 0.67 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
+# CHECK-NEXT: 1 8 0.67 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 2 8 0.67 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
+# CHECK-NEXT: 1 4 0.25 mla v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.25 mla v15.8h, v22.8h, v4.h[3]
+# CHECK-NEXT: 1 4 0.25 mla v28.2s, v10.2s, v2.s[0]
+# CHECK-NEXT: 1 4 0.25 mls v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 mls v25.8h, v29.8h, v0.h[4]
+# CHECK-NEXT: 1 4 0.25 mls v22.2s, v29.2s, v0.s[3]
+# CHECK-NEXT: 1 4 0.25 mls v26.4s, v5.4s, v28.4s
+# CHECK-NEXT: 1 2 0.17 mov b0, v0.b[15]
+# CHECK-NEXT: 1 2 0.17 mov d6, v0.d[1]
+# CHECK-NEXT: 1 2 0.17 mov h2, v0.h[5]
+# CHECK-NEXT: 1 2 0.17 mov s17, v0.s[2]
+# CHECK-NEXT: 1 2 0.17 mov w8, v8.s[0]
+# CHECK-NEXT: 1 2 0.17 mov x30, v18.d[0]
+# CHECK-NEXT: 1 2 0.17 mov v2.b[0], v0.b[0]
+# CHECK-NEXT: 1 2 0.17 mov v2.h[1], v0.h[1]
+# CHECK-NEXT: 1 2 0.17 mov v2.s[2], v0.s[2]
+# CHECK-NEXT: 1 2 0.17 mov v2.d[1], v0.d[1]
+# CHECK-NEXT: 1 2 0.17 mov v0.b[0], w8
+# CHECK-NEXT: 1 2 0.17 mov v0.h[1], w8
+# CHECK-NEXT: 1 2 0.17 mov v0.s[2], w8
+# CHECK-NEXT: 1 2 0.17 mov v0.d[1], x8
+# CHECK-NEXT: 1 2 0.17 mov v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 mov v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 movi d15, #0xff00ff00ff00ff
+# CHECK-NEXT: 1 2 0.17 movi v0.16b, #31
+# CHECK-NEXT: 1 2 0.17 movi v14.8h, #174
+# CHECK-NEXT: 1 2 0.17 movi v13.4h, #74, lsl #8
+# CHECK-NEXT: 1 2 0.17 movi v0.2d, #0xff0000ff0000ffff
+# CHECK-NEXT: 1 2 0.17 movi v0.2s, #8, msl #8
+# CHECK-NEXT: 1 2 0.17 movi v19.2s, #226
+# CHECK-NEXT: 1 2 0.17 movi v1.4s, #122, msl #8
+# CHECK-NEXT: 1 2 0.17 movi v0.4s, #255, lsl #24
+# CHECK-NEXT: 1 2 0.17 movi v0.8b, #255
+# CHECK-NEXT: 1 4 0.25 mul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.25 mul v26.4h, v20.4h, v14.h[5]
+# CHECK-NEXT: 1 4 0.25 mul v5.8h, v21.8h, v3.h[7]
+# CHECK-NEXT: 1 4 0.25 mul v29.2s, v10.2s, v3.s[1]
+# CHECK-NEXT: 1 4 0.25 mul v30.4s, v11.4s, v4.s[0]
+# CHECK-NEXT: 1 4 0.25 mul v30.4s, v11.4s, v4.4s
+# CHECK-NEXT: 1 4 0.25 mul v3.8h, v9.8h, v8.8h
+# CHECK-NEXT: 1 2 0.17 mvni v9.4h, #237
+# CHECK-NEXT: 1 2 0.17 mvni v8.8h, #171, lsl #8
+# CHECK-NEXT: 1 2 0.17 mvni v22.4s, #15, lsl #8
+# CHECK-NEXT: 1 2 0.17 mvni v0.2s, #0
+# CHECK-NEXT: 1 2 0.17 mvni v0.4s, #16, msl #16
+# CHECK-NEXT: 1 2 0.17 neg d29, d24
+# CHECK-NEXT: 1 2 0.17 neg v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 neg v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 neg v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 neg v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 neg v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 neg v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 neg v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 mvn v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 mvn v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 orn v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 orn v29.8b, v19.8b, v16.8b
+# CHECK-NEXT: 1 2 0.17 mov v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 orr v9.4h, #18
+# CHECK-NEXT: 1 2 0.17 orr v0.8h, #31
+# CHECK-NEXT: 1 2 0.17 orr v4.4s, #0
+# CHECK-NEXT: 1 2 0.25 pmul v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.25 pmul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.25 pmull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.25 pmull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 raddhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 raddhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 raddhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 raddhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 raddhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 raddhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 rbit v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 rbit v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 rev16 v21.8b, v1.8b
+# CHECK-NEXT: 1 2 0.17 rev16 v30.16b, v31.16b
+# CHECK-NEXT: 1 2 0.17 rev32 v0.4h, v9.4h
+# CHECK-NEXT: 1 2 0.17 rev32 v21.8b, v1.8b
+# CHECK-NEXT: 1 2 0.17 rev32 v30.16b, v31.16b
+# CHECK-NEXT: 1 2 0.17 rev32 v4.8h, v7.8h
+# CHECK-NEXT: 1 2 0.17 rev64 v0.16b, v31.16b
+# CHECK-NEXT: 1 2 0.17 rev64 v1.8b, v9.8b
+# CHECK-NEXT: 1 2 0.17 rev64 v13.4h, v21.4h
+# CHECK-NEXT: 1 2 0.17 rev64 v2.8h, v4.8h
+# CHECK-NEXT: 1 2 0.17 rev64 v4.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 rev64 v6.4s, v8.4s
+# CHECK-NEXT: 1 4 0.17 rshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 rshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 rshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 rshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 rshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 rshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 rsubhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 rsubhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 rsubhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 rsubhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 rsubhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 rsubhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 saba v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.17 sabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.17 sabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 sabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.17 sabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 sabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 sabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 sabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 sabd v12.2s, v11.2s, v27.2s
+# CHECK-NEXT: 1 2 0.17 sabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 sabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 sabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 sabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 sabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 sabdl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.17 sadalp v0.1d, v0.2s
+# CHECK-NEXT: 1 4 0.17 sadalp v0.2d, v0.4s
+# CHECK-NEXT: 1 4 0.17 sadalp v0.2s, v0.4h
+# CHECK-NEXT: 1 4 0.17 sadalp v0.4h, v0.8b
+# CHECK-NEXT: 1 4 0.17 sadalp v0.4s, v0.8h
+# CHECK-NEXT: 1 4 0.17 sadalp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.17 saddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 saddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 saddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 saddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 saddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 saddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 saddlp v0.1d, v0.2s
+# CHECK-NEXT: 1 2 0.17 saddlp v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.17 saddlp v0.2s, v0.4h
+# CHECK-NEXT: 1 2 0.17 saddlp v0.4h, v0.8b
+# CHECK-NEXT: 1 2 0.17 saddlp v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.17 saddlp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.25 saddlv d0, v0.4s
+# CHECK-NEXT: 1 2 0.25 saddlv s0, v0.4h
+# CHECK-NEXT: 1 4 0.25 saddlv s0, v0.8h
+# CHECK-NEXT: 1 4 0.25 saddlv h0, v0.8b
+# CHECK-NEXT: 1 4 0.50 saddlv h0, v0.16b
+# CHECK-NEXT: 1 2 0.17 saddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.17 saddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.17 saddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.17 saddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.17 saddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.17 saddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 1 3 0.25 scvtf h4, h8, #9
+# CHECK-NEXT: 1 3 0.25 scvtf h5, h14
+# CHECK-NEXT: 1 3 0.25 scvtf d21, d12
+# CHECK-NEXT: 1 3 0.25 scvtf d21, d12, #64
+# CHECK-NEXT: 1 3 0.25 scvtf s22, s13
+# CHECK-NEXT: 1 3 0.25 scvtf s22, s13, #32
+# CHECK-NEXT: 1 3 0.25 scvtf v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 scvtf v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.25 scvtf v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 scvtf v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.25 scvtf v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 scvtf v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 scvtf v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.25 scvtf v25.4h, v13.4h, #8
+# CHECK-NEXT: 1 3 0.25 scvtf v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 scvtf v4.8h, v8.8h, #10
+# CHECK-NEXT: 1 3 0.17 sdot v0.2s, v0.8b, v0.4b[2]
+# CHECK-NEXT: 1 3 0.17 sdot v0.2s, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.17 sdot v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.17 sdot v0.4s, v0.16b, v0.4b[2]
+# CHECK-NEXT: 1 2 0.17 shadd v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 shadd v25.16b, v1.16b, v10.16b
+# CHECK-NEXT: 1 2 0.17 shl d7, d10, #12
+# CHECK-NEXT: 1 2 0.17 shl v23.8b, v18.8b, #6
+# CHECK-NEXT: 1 2 0.17 shl v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.17 shl v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.17 shl v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.17 shl v0.8h, v23.8h, #10
+# CHECK-NEXT: 1 2 0.17 shl v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 shll v0.4s, v0.4h, #16
+# CHECK-NEXT: 1 2 0.17 shll v0.8h, v0.8b, #8
+# CHECK-NEXT: 1 2 0.17 shll v0.2d, v0.2s, #32
+# CHECK-NEXT: 1 2 0.17 shll2 v0.2d, v0.4s, #32
+# CHECK-NEXT: 1 2 0.17 shll2 v0.4s, v0.8h, #16
+# CHECK-NEXT: 1 2 0.17 shll2 v0.8h, v0.16b, #8
+# CHECK-NEXT: 1 2 0.17 shrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.17 shrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 shrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 shrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 shrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.17 shrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 shsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 shsub v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 shsub v15.8h, v5.8h, v27.8h
+# CHECK-NEXT: 1 2 0.17 sli d10, d14, #12
+# CHECK-NEXT: 1 2 0.17 sli v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.17 sli v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.17 sli v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.17 sli v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.17 sli v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 sli v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.17 sli v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 smax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 smax v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 smax v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 smax v30.16b, v3.16b, v30.16b
+# CHECK-NEXT: 1 2 0.17 smaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 smaxp v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 smaxp v21.8h, v16.8h, v7.8h
+# CHECK-NEXT: 1 2 0.17 smaxp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.33 smaxv b0, v0.8b
+# CHECK-NEXT: 1 4 0.50 smaxv b0, v0.16b
+# CHECK-NEXT: 1 2 0.25 smaxv h0, v0.4h
+# CHECK-NEXT: 1 4 0.33 smaxv h0, v0.8h
+# CHECK-NEXT: 1 2 0.25 smaxv s0, v0.4s
+# CHECK-NEXT: 1 2 0.17 smin v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 smin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 smin v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 sminp v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 sminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 sminp v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.33 sminv b0, v0.8b
+# CHECK-NEXT: 1 4 0.50 sminv b0, v0.16b
+# CHECK-NEXT: 1 2 0.25 sminv h0, v0.4h
+# CHECK-NEXT: 1 4 0.33 sminv h0, v0.8h
+# CHECK-NEXT: 1 2 0.25 sminv s0, v0.4s
+# CHECK-NEXT: 1 4 0.25 smlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 smlal v0.2d, v25.2s, v1.s[1]
+# CHECK-NEXT: 1 4 0.25 smlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 smlal v16.4s, v9.4h, v11.h[4]
+# CHECK-NEXT: 1 4 0.25 smlal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.25 smlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.25 smlal2 v30.2d, v22.4s, v7.s[2]
+# CHECK-NEXT: 1 4 0.25 smlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.25 smlal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.25 smlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 smlsl v25.2d, v27.2s, v1.s[1]
+# CHECK-NEXT: 1 4 0.25 smlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 smlsl v14.4s, v23.4h, v12.h[7]
+# CHECK-NEXT: 1 4 0.25 smlsl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.25 smlal2 v1.4s, v9.8h, v0.h[6]
+# CHECK-NEXT: 1 4 0.25 smlsl2 v12.4s, v11.8h, v12.h[0]
+# CHECK-NEXT: 1 4 0.25 smlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.25 smlsl2 v11.2d, v28.4s, v7.s[2]
+# CHECK-NEXT: 1 4 0.25 smlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.25 smlsl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.25 smull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 smull v31.2d, v23.2s, v6.s[2]
+# CHECK-NEXT: 1 3 0.25 smull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 smull v3.4s, v26.4h, v1.h[5]
+# CHECK-NEXT: 1 3 0.25 smull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.25 smull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 smull2 v11.2d, v1.4s, v7.s[0]
+# CHECK-NEXT: 1 3 0.25 smull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 smull2 v13.4s, v18.8h, v0.h[3]
+# CHECK-NEXT: 1 3 0.25 smull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 sqabs b19, b14
+# CHECK-NEXT: 1 2 0.17 sqabs d18, d12
+# CHECK-NEXT: 1 2 0.17 sqabs h21, h15
+# CHECK-NEXT: 1 2 0.17 sqabs s20, s12
+# CHECK-NEXT: 1 2 0.17 sqabs v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 sqabs v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 sqabs v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 sqabs v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 sqabs v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 sqabs v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 sqabs v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 sqadd b20, b11, b15
+# CHECK-NEXT: 1 2 0.17 sqadd h12, h18, h10
+# CHECK-NEXT: 1 2 0.17 sqadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 sqadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 sqdmlal d19, s24, s12
+# CHECK-NEXT: 1 4 0.25 sqdmlal d8, s9, v0.s[1]
+# CHECK-NEXT: 1 4 0.25 sqdmlal s0, h0, v0.h[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlal s17, h27, h12
+# CHECK-NEXT: 1 4 0.25 sqdmlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 sqdmlal v11.2d, v24.2s, v0.s[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 sqdmlal v20.4s, v30.4h, v12.h[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.25 sqdmlal2 v23.2d, v30.4s, v6.s[0]
+# CHECK-NEXT: 1 4 0.25 sqdmlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.25 sqdmlal2 v2.4s, v17.8h, v5.h[6]
+# CHECK-NEXT: 1 4 0.25 sqdmulh v8.4h, v16.4h, v5.h[4]
+# CHECK-NEXT: 1 4 0.25 sqdmulh v16.2s, v24.2s, v7.s[2]
+# CHECK-NEXT: 1 3 0.25 sqdmull v8.4s, v19.4h, v1.h[2]
+# CHECK-NEXT: 1 3 0.25 sqdmull v20.2d, v10.2s, v6.s[2]
+# CHECK-NEXT: 1 3 0.25 sqdmull2 v10.4s, v25.8h, v0.h[7]
+# CHECK-NEXT: 1 3 0.25 sqdmull2 v4.2d, v29.4s, v2.s[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh v0.8h, v15.8h, v0.h[5]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh v6.2s, v29.2s, v4.s[2]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh v31.2s, v17.2s, v4.2s
+# CHECK-NEXT: 1 4 0.25 sqdmlsl d12, s23, s13
+# CHECK-NEXT: 1 4 0.25 sqdmlsl d8, s9, v0.s[1]
+# CHECK-NEXT: 1 4 0.25 sqdmlsl s0, h0, v0.h[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlsl s14, h12, h25
+# CHECK-NEXT: 1 4 0.25 sqdmlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 sqdmlsl v26.2d, v7.2s, v3.s[0]
+# CHECK-NEXT: 1 4 0.25 sqdmlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 sqdmlsl v4.4s, v22.4h, v13.h[2]
+# CHECK-NEXT: 1 4 0.25 sqdmlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.25 sqdmlsl2 v4.2d, v3.4s, v3.s[2]
+# CHECK-NEXT: 1 4 0.25 sqdmlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.25 sqdmlsl2 v2.4s, v28.8h, v4.h[6]
+# CHECK-NEXT: 1 4 0.25 sqdmulh h10, h11, h12
+# CHECK-NEXT: 1 4 0.25 sqdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: 1 4 0.25 sqdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: 1 4 0.25 sqdmulh s20, s21, s2
+# CHECK-NEXT: 1 4 0.25 sqdmulh v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 sqdmulh v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 sqdmull d1, s1, v0.s[1]
+# CHECK-NEXT: 1 3 0.25 sqdmull d15, s22, s12
+# CHECK-NEXT: 1 3 0.25 sqdmull s1, h1, v0.h[3]
+# CHECK-NEXT: 1 3 0.25 sqdmull s12, h22, h12
+# CHECK-NEXT: 1 3 0.25 sqdmull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 sqdmull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 sqdmull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 sqdmull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 sqneg b19, b14
+# CHECK-NEXT: 1 2 0.17 sqneg d18, d12
+# CHECK-NEXT: 1 2 0.17 sqneg h21, h15
+# CHECK-NEXT: 1 2 0.17 sqneg s20, s12
+# CHECK-NEXT: 1 2 0.17 sqneg v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 sqneg v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 sqneg v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 sqneg v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 sqneg v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 sqneg v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 sqneg v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.25 sqrdmlah h0, h1, v2.h[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.4h, v1.4h, v2.h[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.8h, v1.8h, v2.h[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah s0, s1, v2.s[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.2s, v1.2s, v2.s[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.4s, v1.4s, v2.s[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah h0, h1, h2
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.4h, v1.4h, v2.4h
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: 1 4 0.25 sqrdmlah s0, s1, s2
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.2s, v1.2s, v2.2s
+# CHECK-NEXT: 1 4 0.25 sqrdmlah v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh h0, h1, v2.h[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.4h, v1.4h, v2.h[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.8h, v1.8h, v2.h[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh s0, s1, v2.s[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.2s, v1.2s, v2.s[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.4s, v1.4s, v2.s[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh h0, h1, h2
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.4h, v1.4h, v2.4h
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh s0, s1, s2
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.2s, v1.2s, v2.2s
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: 1 4 0.25 sqrdmulh h10, h11, h12
+# CHECK-NEXT: 1 4 0.25 sqrdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh s20, s21, s2
+# CHECK-NEXT: 1 4 0.25 sqrdmulh v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 sqrdmulh v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 sqrshl d31, d31, d31
+# CHECK-NEXT: 1 4 0.17 sqrshl h3, h4, h15
+# CHECK-NEXT: 1 4 0.17 sqrshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.17 sqrshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 sqrshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.17 sqshl s17, s4, s23
+# CHECK-NEXT: 1 2 0.17 sqsub b3, b13, b12
+# CHECK-NEXT: 1 2 0.17 sqsub v20.8h, v18.8h, v12.8h
+# CHECK-NEXT: 1 4 0.17 sqrshrn b10, h13, #2
+# CHECK-NEXT: 1 4 0.17 sqrshrn h15, s10, #6
+# CHECK-NEXT: 1 4 0.17 sqrshrn s15, d12, #9
+# CHECK-NEXT: 1 4 0.17 sqrshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrun b17, h10, #6
+# CHECK-NEXT: 1 4 0.17 sqrshrun h10, s13, #15
+# CHECK-NEXT: 1 4 0.17 sqrshrun s22, d16, #31
+# CHECK-NEXT: 1 4 0.17 sqrshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqrshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqshl b11, b19, #7
+# CHECK-NEXT: 1 4 0.17 sqshl d15, d16, #51
+# CHECK-NEXT: 1 4 0.17 sqshl d31, d31, d31
+# CHECK-NEXT: 1 4 0.17 sqshl h13, h18, #11
+# CHECK-NEXT: 1 4 0.17 sqshl h3, h4, h15
+# CHECK-NEXT: 1 4 0.17 sqshl s14, s17, #22
+# CHECK-NEXT: 1 4 0.17 sqshl v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 sqshl v23.16b, v23.16b, v23.16b
+# CHECK-NEXT: 1 4 0.17 sqshl v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqshl v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 sqshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.17 sqshl v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 sqshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 sqshl v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqshl v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 sqshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.17 sqshl v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqshlu b15, b18, #6
+# CHECK-NEXT: 1 4 0.17 sqshlu d11, d13, #32
+# CHECK-NEXT: 1 4 0.17 sqshlu h19, h17, #6
+# CHECK-NEXT: 1 4 0.17 sqshlu s16, s14, #25
+# CHECK-NEXT: 1 4 0.17 sqshlu v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 sqshlu v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqshlu v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 sqshlu v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 sqshlu v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqshlu v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 sqshlu v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqshrn b10, h15, #5
+# CHECK-NEXT: 1 4 0.17 sqshrn h17, s10, #4
+# CHECK-NEXT: 1 4 0.17 sqshrn s18, d10, #31
+# CHECK-NEXT: 1 4 0.17 sqshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqshrun b15, h10, #7
+# CHECK-NEXT: 1 4 0.17 sqshrun h20, s14, #3
+# CHECK-NEXT: 1 4 0.17 sqshrun s10, d15, #15
+# CHECK-NEXT: 1 4 0.17 sqshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 sqshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 sqshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 sqshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 sqsub s20, s10, s7
+# CHECK-NEXT: 1 2 0.17 sqsub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 sqsub v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 sqsub v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.17 sqxtn b18, h18
+# CHECK-NEXT: 1 4 0.17 sqxtn h20, s17
+# CHECK-NEXT: 1 4 0.17 sqxtn s19, d14
+# CHECK-NEXT: 1 4 0.17 sqxtn v0.2s, v0.2d
+# CHECK-NEXT: 1 4 0.17 sqxtn v0.4h, v0.4s
+# CHECK-NEXT: 1 4 0.17 sqxtn v0.8b, v0.8h
+# CHECK-NEXT: 1 4 0.17 sqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 4 0.17 sqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.17 sqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.17 sqxtun b19, h14
+# CHECK-NEXT: 1 4 0.17 sqxtun h21, s15
+# CHECK-NEXT: 1 4 0.17 sqxtun s20, d12
+# CHECK-NEXT: 1 4 0.17 sqxtun v0.2s, v0.2d
+# CHECK-NEXT: 1 4 0.17 sqxtun v0.4h, v0.4s
+# CHECK-NEXT: 1 4 0.17 sqxtun v0.8b, v0.8h
+# CHECK-NEXT: 1 4 0.17 sqxtun2 v0.16b, v0.8h
+# CHECK-NEXT: 1 4 0.17 sqxtun2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.17 sqxtun2 v0.8h, v0.4s
+# CHECK-NEXT: 1 2 0.17 srhadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 srhadd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 srhadd v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 sri d10, d12, #14
+# CHECK-NEXT: 1 2 0.17 sri v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.17 sri v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.17 sri v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.17 sri v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.17 sri v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 sri v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.17 sri v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 srshl d16, d16, d16
+# CHECK-NEXT: 1 4 0.17 srshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.17 srshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 srshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.17 srshr d19, d18, #7
+# CHECK-NEXT: 1 4 0.17 srshr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 srshr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 srshr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 srshr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 srshr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 srshr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 srshr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 srsra d15, d11, #19
+# CHECK-NEXT: 1 4 0.17 srsra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 srsra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 srsra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 srsra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 srsra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 srsra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 srsra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 sshl d31, d31, d31
+# CHECK-NEXT: 1 2 0.17 sshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 sshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 sshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 sshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 sshll v9.8h, v2.8b, #0
+# CHECK-NEXT: 1 2 0.17 sshll v12.4s, v3.4h, #4
+# CHECK-NEXT: 1 2 0.17 sshll v0.2d, v0.2s, #3
+# CHECK-NEXT: 1 2 0.17 sshll2 v28.8h, v12.16b, #7
+# CHECK-NEXT: 1 2 0.17 sshll2 v0.4s, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 sshll2 v17.2d, v13.4s, #22
+# CHECK-NEXT: 1 2 0.17 sshr d15, d16, #12
+# CHECK-NEXT: 1 2 0.17 sshr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.17 sshr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.17 sshr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.17 sshr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.17 sshr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 sshr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.17 sshr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 ssra d18, d12, #21
+# CHECK-NEXT: 1 4 0.17 ssra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 ssra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 ssra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 ssra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 ssra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 ssra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 ssra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 ssubl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 ssubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 ssubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 ssubl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 ssubl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 ssubl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 ssubw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.17 ssubw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.17 ssubw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.17 ssubw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.17 ssubw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.17 ssubw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.50 * st1 { v18.8b }, [x15]
+# CHECK-NEXT: 1 2 0.50 * st1 { v8.8b, v9.8b }, [x18]
+# CHECK-NEXT: 1 2 1.00 * st1 { v15.8b, v16.8b, v17.8b }, [x0]
+# CHECK-NEXT: 1 2 1.00 * st1 { v21.8b, v22.8b, v23.8b, v24.8b }, [x14]
+# CHECK-NEXT: 1 2 0.50 * st1 { v0.16b }, [x0]
+# CHECK-NEXT: 1 2 1.00 * st1 { v1.16b, v2.16b }, [x4]
+# CHECK-NEXT: 1 2 1.50 * st1 { v27.16b, v28.16b, v29.16b }, [x18]
+# CHECK-NEXT: 1 2 2.00 * st1 { v18.16b, v19.16b, v20.16b, v21.16b }, [x29]
+# CHECK-NEXT: 1 2 0.50 * st1 { v19.4h }, [x7]
+# CHECK-NEXT: 1 2 0.50 * st1 { v22.4h, v23.4h }, [x22]
+# CHECK-NEXT: 1 2 1.00 * st1 { v13.4h, v14.4h, v15.4h }, [x7]
+# CHECK-NEXT: 1 2 1.00 * st1 { v23.4h, v24.4h, v25.4h, v26.4h }, [x24]
+# CHECK-NEXT: 1 2 0.50 * st1 { v27.8h }, [x17]
+# CHECK-NEXT: 1 2 1.50 * st1 { v8.8h, v9.8h, v10.8h }, [x16]
+# CHECK-NEXT: 1 2 2.00 * st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x19]
+# CHECK-NEXT: 1 2 0.50 * st1 { v25.2s }, [x6]
+# CHECK-NEXT: 1 2 0.50 * st1 { v13.2s, v14.2s }, [x9]
+# CHECK-NEXT: 1 2 1.00 * st1 { v12.2s, v13.2s, v14.2s }, [x3]
+# CHECK-NEXT: 1 2 1.00 * st1 { v6.2s, v7.2s, v8.2s, v9.2s }, [x13]
+# CHECK-NEXT: 2 2 1.00 * st1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: 1 2 0.50 * st1 { v22.4s }, [x19]
+# CHECK-NEXT: 1 2 1.00 * st1 { v15.4s, v16.4s }, [x12]
+# CHECK-NEXT: 1 2 2.00 * st1 { v26.4s, v27.4s, v28.4s, v29.4s }, [x12]
+# CHECK-NEXT: 1 2 0.50 * st1 { v20.1d }, [x10]
+# CHECK-NEXT: 1 2 0.50 * st1 { v21.1d, v22.1d }, [x29]
+# CHECK-NEXT: 1 2 1.00 * st1 { v5.1d, v6.1d, v7.1d }, [x3]
+# CHECK-NEXT: 1 2 1.00 * st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x10]
+# CHECK-NEXT: 1 2 1.00 * st1 { v26.2d, v27.2d }, [x28]
+# CHECK-NEXT: 2 2 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: 1 2 1.50 * st1 { v13.2d, v14.2d, v15.2d }, [x27]
+# CHECK-NEXT: 1 2 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: 1 2 0.50 * st1 { v8.2d }, [x15]
+# CHECK-NEXT: 2 2 0.50 * st1 { v0.8h }, [x15], x2
+# CHECK-NEXT: 1 2 1.00 * st1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: 2 2 1.00 * st1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: 1 2 1.50 * st1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: 2 2 1.00 * st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: 1 4 0.50 * st1 { v1.b }[5], [x1]
+# CHECK-NEXT: 1 4 0.50 * st1 { v0.h }[2], [x1]
+# CHECK-NEXT: 1 4 0.50 * st1 { v31.s }[1], [x16]
+# CHECK-NEXT: 2 2 0.50 * st1 { v0.8h }, [x15], x2
+# CHECK-NEXT: 1 2 1.00 * st1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: 1 4 0.50 * st1 { v0.d }[1], [x0]
+# CHECK-NEXT: 2 4 0.50 * st1 { v0.d }[1], [x0], #8
+# CHECK-NEXT: 2 4 1.00 * st2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: 1 4 1.00 * st2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: 1 4 1.00 * st2 { v6.16b, v7.16b }, [x23]
+# CHECK-NEXT: 1 4 1.00 * st2 { v10.4h, v11.4h }, [x18]
+# CHECK-NEXT: 1 4 1.00 * st2 { v10.8h, v11.8h }, [x18]
+# CHECK-NEXT: 1 4 1.00 * st2 { v25.2s, v26.2s }, [x29]
+# CHECK-NEXT: 1 4 1.00 * st2 { v26.4s, v27.4s }, [x14]
+# CHECK-NEXT: 1 4 1.00 * st2 { v10.2d, v11.2d }, [x1]
+# CHECK-NEXT: 1 4 0.50 * st2 { v21.b, v22.b }[15], [x15]
+# CHECK-NEXT: 1 4 0.50 * st2 { v28.h, v29.h }[2], [x6]
+# CHECK-NEXT: 1 4 0.50 * st2 { v0.s, v1.s }[3], [sp]
+# CHECK-NEXT: 2 4 0.50 * st2 { v0.s, v1.s }[3], [sp], #8
+# CHECK-NEXT: 1 4 0.50 * st2 { v17.d, v18.d }[1], [x1]
+# CHECK-NEXT: 1 4 1.00 * st3 { v10.8b, v11.8b, v12.8b }, [x18]
+# CHECK-NEXT: 1 5 2.00 * st3 { v26.16b, v27.16b, v28.16b }, [x4]
+# CHECK-NEXT: 1 4 1.00 * st3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 2 5 2.00 * st3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: 1 5 2.00 * st3 { v0.8h, v1.8h, v2.8h }, [x0]
+# CHECK-NEXT: 1 4 1.00 * st3 { v19.2s, v20.2s, v21.2s }, [x30]
+# CHECK-NEXT: 1 5 2.00 * st3 { v24.4s, v25.4s, v26.4s }, [x8]
+# CHECK-NEXT: 1 5 2.00 * st3 { v24.2d, v25.2d, v26.2d }, [x25]
+# CHECK-NEXT: 1 4 1.00 * st3 { v8.b, v9.b, v10.b }[4], [x18]
+# CHECK-NEXT: 1 4 1.00 * st3 { v0.h, v1.h, v2.h }[7], [x15]
+# CHECK-NEXT: 2 4 1.00 * st3 { v0.h, v1.h, v2.h }[7], [x15], #6
+# CHECK-NEXT: 1 4 1.00 * st3 { v9.s, v10.s, v11.s }[2], [x20]
+# CHECK-NEXT: 1 4 1.00 * st3 { v16.d, v17.d, v18.d }[0], [x13]
+# CHECK-NEXT: 1 6 3.00 * st4 { v17.8b, v18.8b, v19.8b, v20.8b }, [x8]
+# CHECK-NEXT: 1 7 6.00 * st4 { v7.16b, v8.16b, v9.16b, v10.16b }, [x15]
+# CHECK-NEXT: 1 6 3.00 * st4 { v5.4h, v6.4h, v7.4h, v8.4h }, [x13]
+# CHECK-NEXT: 1 7 6.00 * st4 { v11.8h, v12.8h, v13.8h, v14.8h }, [x1]
+# CHECK-NEXT: 1 6 3.00 * st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 2 7 6.00 * st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: 1 7 6.00 * st4 { v21.4s, v22.4s, v23.4s, v24.4s }, [x6]
+# CHECK-NEXT: 1 6 4.00 * st4 { v25.2d, v26.2d, v27.2d, v28.2d }, [x16]
+# CHECK-NEXT: 1 6 0.50 * st4 { v0.b, v1.b, v2.b, v3.b }[15], [x0]
+# CHECK-NEXT: 1 6 0.50 * st4 { v5.h, v6.h, v7.h, v8.h }[4], [x13]
+# CHECK-NEXT: 1 6 0.50 * st4 { v22.s, v23.s, v24.s, v25.s }[0], [x7]
+# CHECK-NEXT: 1 6 0.50 * st4 { v23.d, v24.d, v25.d, v26.d }[1], [x5]
+# CHECK-NEXT: 1 6 0.50 * st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
+# CHECK-NEXT: 2 6 0.50 * st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
+# CHECK-NEXT: 2 6 0.50 * st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], x5
+# CHECK-NEXT: 1 2 0.17 sub d15, d5, d16
+# CHECK-NEXT: 1 2 0.17 sub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 sub v15.2s, v14.2s, v11.2s
+# CHECK-NEXT: 1 2 0.17 subhn v7.4h, v10.4s, v13.4s
+# CHECK-NEXT: 1 2 0.17 subhn2 v24.4s, v24.2d, v8.2d
+# CHECK-NEXT: 1 2 0.17 suqadd b19, b14
+# CHECK-NEXT: 1 2 0.17 suqadd d18, d22
+# CHECK-NEXT: 1 2 0.17 suqadd h20, h15
+# CHECK-NEXT: 1 2 0.17 suqadd s21, s12
+# CHECK-NEXT: 1 2 0.17 suqadd v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 suqadd v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 suqadd v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 suqadd v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 suqadd v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 suqadd v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 suqadd v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 tbl v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: 1 2 0.17 tbl v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: 1 4 0.33 tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: 1 4 0.50 tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: 1 2 0.17 tbl v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: 1 2 0.17 tbl v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: 1 4 0.33 tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: 1 4 0.50 tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: 1 2 0.17 tbx v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: 1 4 0.33 tbx v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: 1 6 0.50 tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: 1 6 0.83 tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: 1 2 0.17 tbx v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: 1 4 0.33 tbx v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: 1 6 0.50 tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: 1 6 0.83 tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: 1 2 0.17 trn1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 trn1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 trn1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 trn1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 trn1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 trn1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 trn1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 trn2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 trn2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 trn2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 trn2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 trn2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 trn2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 trn2 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 uaba v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.17 uaba v13.16b, v14.16b, v19.16b
+# CHECK-NEXT: 1 4 0.17 uabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.17 uabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.17 uabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.17 uabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 uabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 uabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 uabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 uabd v23.4s, v4.4s, v30.4s
+# CHECK-NEXT: 1 2 0.17 uabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 uabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 uabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 uabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 uabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 uabdl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.17 uadalp v0.1d, v0.2s
+# CHECK-NEXT: 1 4 0.17 uadalp v0.2d, v0.4s
+# CHECK-NEXT: 1 4 0.17 uadalp v0.2s, v0.4h
+# CHECK-NEXT: 1 4 0.17 uadalp v0.4h, v0.8b
+# CHECK-NEXT: 1 4 0.17 uadalp v0.4s, v0.8h
+# CHECK-NEXT: 1 4 0.17 uadalp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.17 uaddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 uaddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 uaddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 uaddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 uaddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 uaddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 uaddlp v0.1d, v0.2s
+# CHECK-NEXT: 1 2 0.17 uaddlp v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.17 uaddlp v0.2s, v0.4h
+# CHECK-NEXT: 1 2 0.17 uaddlp v0.4h, v0.8b
+# CHECK-NEXT: 1 2 0.17 uaddlp v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.17 uaddlp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.25 uaddlv d0, v0.4s
+# CHECK-NEXT: 1 2 0.25 uaddlv s0, v0.4h
+# CHECK-NEXT: 1 4 0.25 uaddlv s0, v0.8h
+# CHECK-NEXT: 1 4 0.25 uaddlv h0, v0.8b
+# CHECK-NEXT: 1 4 0.50 uaddlv h0, v0.16b
+# CHECK-NEXT: 1 2 0.17 uaddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.17 uaddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.17 uaddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.17 uaddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.17 uaddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.17 uaddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 1 3 1.00 ucvtf h17, x12
+# CHECK-NEXT: 1 3 0.25 ucvtf h22, h16, #11
+# CHECK-NEXT: 1 3 0.25 ucvtf h7, h21
+# CHECK-NEXT: 1 3 0.25 ucvtf d21, d14
+# CHECK-NEXT: 1 3 0.25 ucvtf d21, d14, #64
+# CHECK-NEXT: 1 3 1.00 ucvtf s8, x0
+# CHECK-NEXT: 1 3 0.25 ucvtf s22, s13
+# CHECK-NEXT: 1 3 0.25 ucvtf s22, s13, #32
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.25 ucvtf v18.4h, v11.4h, #7
+# CHECK-NEXT: 1 3 0.25 ucvtf v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 ucvtf v22.8h, v20.8h, #10
+# CHECK-NEXT: 1 3 0.17 udot v0.2s, v0.8b, v0.4b[2]
+# CHECK-NEXT: 1 3 0.17 udot v0.2s, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.17 udot v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.17 udot v0.4s, v0.16b, v0.4b[2]
+# CHECK-NEXT: 1 2 0.17 uhadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 uhadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 uhsub v12.4h, v16.4h, v28.4h
+# CHECK-NEXT: 1 2 0.17 uhsub v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 umax v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 umax v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 umax v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 umaxp v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 umaxp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 umaxp v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.33 umaxv b0, v0.8b
+# CHECK-NEXT: 1 4 0.50 umaxv b0, v0.16b
+# CHECK-NEXT: 1 2 0.25 umaxv h0, v0.4h
+# CHECK-NEXT: 1 4 0.33 umaxv h0, v0.8h
+# CHECK-NEXT: 1 2 0.25 umaxv s0, v0.4s
+# CHECK-NEXT: 1 2 0.17 umin v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 umin v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 umin v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 umin v0.16b, v26.16b, v2.16b
+# CHECK-NEXT: 1 2 0.17 uminp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 uminp v28.4s, v16.4s, v15.4s
+# CHECK-NEXT: 1 2 0.17 uminp v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 uminp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.33 uminv b0, v0.8b
+# CHECK-NEXT: 1 4 0.50 uminv b0, v0.16b
+# CHECK-NEXT: 1 2 0.25 uminv h0, v0.4h
+# CHECK-NEXT: 1 4 0.33 uminv h0, v0.8h
+# CHECK-NEXT: 1 2 0.25 uminv s0, v0.4s
+# CHECK-NEXT: 1 4 0.25 umlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 umlal v28.2d, v31.2s, v0.s[1]
+# CHECK-NEXT: 1 4 0.25 umlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 umlal v22.4s, v14.4h, v0.h[6]
+# CHECK-NEXT: 1 4 0.25 umlal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.25 umlal2 v10.2d, v4.4s, v3.s[2]
+# CHECK-NEXT: 1 4 0.25 umlal2 v31.4s, v7.8h, v15.h[5]
+# CHECK-NEXT: 1 4 0.25 umlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.25 umlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.25 umlal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.25 umlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.25 umlsl v20.2d, v20.2s, v2.s[0]
+# CHECK-NEXT: 1 4 0.25 umlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 4 0.25 umlsl v21.4s, v12.4h, v7.h[5]
+# CHECK-NEXT: 1 4 0.25 umlsl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.25 umlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.25 umlsl2 v30.2d, v23.4s, v1.s[2]
+# CHECK-NEXT: 1 4 0.25 umlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.25 umlsl2 v27.4s, v28.8h, v6.h[4]
+# CHECK-NEXT: 1 4 0.25 umlsl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 umov w6, v22.b[0]
+# CHECK-NEXT: 1 2 0.50 umov w0, v0.b[1]
+# CHECK-NEXT: 1 2 0.50 umov w10, v25.h[0]
+# CHECK-NEXT: 1 2 0.50 umov w0, v0.h[1]
+# CHECK-NEXT: 1 2 0.17 mov w0, v0.s[1]
+# CHECK-NEXT: 1 2 0.17 mov x0, v0.d[1]
+# CHECK-NEXT: 1 3 0.25 umull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.25 umull v22.2d, v28.2s, v6.s[1]
+# CHECK-NEXT: 1 3 0.25 umull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.25 umull v27.4s, v1.4h, v8.h[6]
+# CHECK-NEXT: 1 3 0.25 umull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.25 umull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.25 umull2 v28.2d, v21.4s, v1.s[0]
+# CHECK-NEXT: 1 3 0.25 umull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.25 umull2 v18.4s, v26.8h, v10.h[1]
+# CHECK-NEXT: 1 3 0.25 umull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 uqadd h0, h1, h5
+# CHECK-NEXT: 1 2 0.17 uqadd s0, s24, s30
+# CHECK-NEXT: 1 2 0.17 uqadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 uqadd v14.2d, v22.2d, v20.2d
+# CHECK-NEXT: 1 4 0.17 uqrshl b11, b20, b30
+# CHECK-NEXT: 1 4 0.17 uqrshl s23, s20, s16
+# CHECK-NEXT: 1 4 0.17 uqrshl v25.8b, v13.8b, v23.8b
+# CHECK-NEXT: 1 4 0.17 uqrshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.17 uqrshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 uqrshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 uqrshrn b10, h12, #5
+# CHECK-NEXT: 1 4 0.17 uqrshrn h12, s10, #14
+# CHECK-NEXT: 1 4 0.17 uqrshrn s10, d10, #25
+# CHECK-NEXT: 1 4 0.17 uqrshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 uqrshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 uqrshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 uqrshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 uqrshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 uqrshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 uqshl b11, b20, b30
+# CHECK-NEXT: 1 4 0.17 uqshl b18, b15, #6
+# CHECK-NEXT: 1 4 0.17 uqshl d15, d12, #19
+# CHECK-NEXT: 1 4 0.17 uqshl h11, h18, #7
+# CHECK-NEXT: 1 4 0.17 uqshl s14, s19, #18
+# CHECK-NEXT: 1 4 0.17 uqshl s23, s20, s16
+# CHECK-NEXT: 1 4 0.17 uqshl v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 uqshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.17 uqshl v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 uqshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 4 0.17 uqshl v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 uqshl v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 uqshl v8.4h, v17.4h, v13.4h
+# CHECK-NEXT: 1 4 0.17 uqshl v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 uqshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 uqshl v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 uqshl v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 uqshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 uqshrn b12, h10, #7
+# CHECK-NEXT: 1 4 0.17 uqshrn h10, s14, #5
+# CHECK-NEXT: 1 4 0.17 uqshrn s10, d12, #13
+# CHECK-NEXT: 1 4 0.17 uqshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 uqshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 uqshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 uqshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 4 0.17 uqshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 uqshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 uqsub s16, s21, s6
+# CHECK-NEXT: 1 2 0.17 uqsub d16, d16, d16
+# CHECK-NEXT: 1 2 0.17 uqsub v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 uqsub v19.4s, v0.4s, v5.4s
+# CHECK-NEXT: 1 4 0.17 uqxtn b18, h18
+# CHECK-NEXT: 1 4 0.17 uqxtn h20, s17
+# CHECK-NEXT: 1 4 0.17 uqxtn s19, d14
+# CHECK-NEXT: 1 4 0.17 uqxtn v0.2s, v0.2d
+# CHECK-NEXT: 1 4 0.17 uqxtn v0.4h, v0.4s
+# CHECK-NEXT: 1 4 0.17 uqxtn v0.8b, v0.8h
+# CHECK-NEXT: 1 4 0.17 uqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 4 0.17 uqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 4 0.17 uqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 4 0.50 urecpe v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 urecpe v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 urhadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 urhadd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 urhadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 urhadd v16.2s, v19.2s, v2.2s
+# CHECK-NEXT: 1 4 0.17 urshl d8, d7, d4
+# CHECK-NEXT: 1 4 0.17 urshl v31.8b, v5.8b, v3.8b
+# CHECK-NEXT: 1 4 0.17 urshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 4 0.17 urshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 4 0.17 urshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 urshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 urshr d20, d23, #31
+# CHECK-NEXT: 1 4 0.17 urshr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 urshr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 urshr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 urshr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 urshr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 urshr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 urshr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 4 0.50 ursqrte v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 ursqrte v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.17 ursra d18, d10, #13
+# CHECK-NEXT: 1 4 0.17 ursra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 ursra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 ursra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 ursra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 ursra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 ursra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 ursra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 ushl d0, d0, d0
+# CHECK-NEXT: 1 2 0.17 ushl v6.8b, v26.8b, v6.8b
+# CHECK-NEXT: 1 2 0.17 ushl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 ushl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 ushl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 ushll v0.4s, v0.4h, #3
+# CHECK-NEXT: 1 2 0.17 ushll v18.8h, v24.8b, #4
+# CHECK-NEXT: 1 2 0.17 ushll v16.2d, v16.2s, #31
+# CHECK-NEXT: 1 2 0.17 ushll2 v31.2d, v12.4s, #11
+# CHECK-NEXT: 1 2 0.17 ushll2 v18.4s, v22.8h, #13
+# CHECK-NEXT: 1 2 0.17 ushll2 v0.8h, v0.16b, #3
+# CHECK-NEXT: 1 2 0.17 ushr d10, d17, #18
+# CHECK-NEXT: 1 2 0.17 ushr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.17 ushr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.17 ushr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.17 ushr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.17 ushr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.17 ushr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.17 ushr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 U smov w15, v22.b[0]
+# CHECK-NEXT: 1 2 0.50 U smov w26, v27.h[0]
+# CHECK-NEXT: 1 2 0.50 U smov x21, v0.b[0]
+# CHECK-NEXT: 1 2 0.50 U smov x9, v27.h[0]
+# CHECK-NEXT: 1 2 0.50 U smov x15, v3.s[0]
+# CHECK-NEXT: 1 2 0.50 smov w0, v0.b[1]
+# CHECK-NEXT: 1 2 0.50 smov w0, v0.h[1]
+# CHECK-NEXT: 1 2 0.50 smov x0, v0.b[1]
+# CHECK-NEXT: 1 2 0.50 smov x0, v0.h[1]
+# CHECK-NEXT: 1 2 0.50 smov x0, v0.s[1]
+# CHECK-NEXT: 1 2 0.17 usqadd b19, b14
+# CHECK-NEXT: 1 2 0.17 usqadd d18, d22
+# CHECK-NEXT: 1 2 0.17 usqadd h20, h15
+# CHECK-NEXT: 1 2 0.17 usqadd s21, s12
+# CHECK-NEXT: 1 2 0.17 usqadd v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 usqadd v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 usqadd v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 usqadd v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 usqadd v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 usqadd v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 usqadd v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.17 usra d20, d13, #61
+# CHECK-NEXT: 1 4 0.17 usra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 4 0.17 usra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 4 0.17 usra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 4 0.17 usra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 4 0.17 usra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 4 0.17 usra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 4 0.17 usra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.17 usubl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 usubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 usubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 usubl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 usubl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 usubl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 usubw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.17 usubw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.17 usubw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.17 usubw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.17 usubw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.17 usubw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.17 uzp1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 uzp1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 uzp1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 uzp1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 uzp1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 uzp1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 uzp1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 uzp2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 uzp2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 uzp2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 uzp2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 uzp2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 uzp2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 uzp2 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 xtn v0.2s, v0.2d
+# CHECK-NEXT: 1 2 0.17 xtn v0.4h, v0.4s
+# CHECK-NEXT: 1 2 0.17 xtn v0.8b, v0.8h
+# CHECK-NEXT: 1 2 0.17 xtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 2 0.17 xtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 2 0.17 xtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 2 0.17 zip1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 zip1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 zip1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 zip1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 zip1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 zip1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 zip1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.17 zip2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.17 zip2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.17 zip2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.17 zip2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.17 zip2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.17 zip2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.17 zip2 v0.8h, v0.8h, v0.8h
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - 69.25 69.25 179.25 179.25 15.13 6.13 6.13 6.13 6.13 6.13 6.13 6.13 450.83 490.83 237.83 340.83 340.83 237.83
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs d29, d24
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add d17, d31, d29
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addp v7.2s, v1.2s, v2.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 addp d1, v14.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - addv s0, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - addv h0, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - addv h0, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - addv b0, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - addv b0, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - aesd v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - aese v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - aesimc v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - aesmc v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 and v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bic v0.4h, #15, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bic v23.8h, #101
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bic v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bic v25.16b, v10.16b, v9.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bic v24.2s, #70
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bit v5.8b, v12.8b, v22.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bif v0.8b, v25.8b, v4.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bif v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bit v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bsl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 bsl v27.16b, v13.16b, v21.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cls v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cls v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cls v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cls v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cls v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cls v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 clz v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 clz v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 clz v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 clz v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 clz v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 clz v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmeq v9.8h, v16.8h, v24.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmeq v14.4h, v18.4h, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmeq d20, d21, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmeq d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmeq v0.16b, v0.16b, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmeq v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmge v22.8h, v16.8h, v3.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmge v22.16b, v30.16b, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmge d20, d21, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmge d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmge v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmge v0.8b, v0.8b, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmgt v3.2d, v29.2d, v11.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 cmgt d20, d21, #0
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtau v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtl v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtl v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtl2 v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtl2 v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms s22, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms h22, h13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtms v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu s12, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu h12, h13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtmu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtn v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns s22, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns h22, h13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtns v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu s12, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu h12, h13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtnu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps s22, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps h22, h13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtps v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu s12, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu h12, h13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtpu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtxn s22, d13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtxn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtxn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs d21, d12, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs s12, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs s21, s12, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs h21, h14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs h21, h12, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v20.4h, v24.4h, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzs v18.8h, v10.8h, #7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu d21, d12, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu d21, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu s12, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu s21, s12, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu h12, h13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu h21, h12, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v19.4h, v26.4h, #9
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - fcvtzu v27.8h, v6.8h, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 2.00 - - - - fdiv v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 2.00 - - - - fdiv v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 4.00 - - - - fdiv v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 4.00 - - - - fdiv v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 8.00 - - - - fdiv v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmax v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmax v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp h25, v19.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp d17, v29.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fmaxnmv h0, v13.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fmaxnmv h12, v11.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fmaxnmv s28, v31.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp h15, v25.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp s6, v2.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fmaxv h0, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fmaxv h0, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fmaxv s0, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp h20, v14.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp d15, v8.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fminnmv h19, v25.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fminnmv h23, v17.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fminnmv s29, v17.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp h7, v10.2h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp s17, v7.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fminv h3, v30.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fminv h29, v12.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fminv s16, v19.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla d0, d1, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla h23, h24, v15.h[4]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla s0, s1, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla v29.8h, v15.8h, v10.h[4]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla v2.2s, v16.2s, v28.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla v14.4s, v14.4s, v5.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla v1.4s, v24.4s, v12.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla v10.2d, v14.2d, v21.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls d0, d4, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls h8, h14, v7.h[4]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls s3, s5, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls v30.8h, v18.8h, v4.h[6]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls v10.2s, v27.2s, v0.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls v27.4s, v7.4s, v24.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls v10.2d, v22.2d, v29.d[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls v6.8h, v15.8h, v23.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov v0.2d, #-1.25000000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov v0.2s, #13.00000000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov v0.4s, #1.00000000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul h18, h4, v7.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul v10.4h, v2.4h, v7.h[5]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul v5.2s, v12.2s, v9.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul v15.4s, v30.4s, v2.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul v11.2d, v31.2d, v24.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul h28, h14, h3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul d0, d1, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul s0, s1, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx d0, d4, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx d23, d11, d1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx s20, s22, s15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx h18, h17, v7.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx h20, h25, h0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx s3, s5, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx v28.4h, v25.4h, v15.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx v3.2s, v22.2s, v23.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx v5.4s, v28.4s, v15.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx v22.2d, v18.2d, v25.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpe h20, h8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpe d13, d13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpe s19, s14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpe v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpe v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - frecpe v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - frecpe v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 1.00 1.00 - 1.00 1.00 - frecpe v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frecps h29, h19, h8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpx h18, h11
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frecps v12.8h, v25.8h, v4.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frecps v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frecps d22, d30, d21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frecps s21, s16, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frecps v7.2d, v29.2d, v18.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpx d16, d19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frecpx s18, s10
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinta v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinta v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinta v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinta v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinta v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinti v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinti v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinti v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinti v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frinti v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintm v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintm v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintm v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintm v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintm v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintn v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintn v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintn v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintn v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintn v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintp v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintp v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintp v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintp v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintp v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintx v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintx v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintx v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintx v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintx v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintz v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintz v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintz v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintz v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frintz v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frsqrte h23, h26
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frsqrte d21, d12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frsqrte s22, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frsqrte v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - frsqrte v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - frsqrte v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - frsqrte v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frsqrts v20.4s, v26.4s, v27.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frsqrts v8.4h, v9.4h, v30.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 1.00 1.00 - 1.00 1.00 - frsqrte v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frsqrts h28, h26, h1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frsqrts d8, d22, d18
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frsqrts s21, s5, s12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 frsqrts v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 2.00 - - - - fsqrt v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 2.00 - - - - fsqrt v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 4.00 - - - - fsqrt v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 4.00 - - - - fsqrt v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 8.00 - - - - fsqrt v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fsub v13.8h, v15.8h, v17.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1 { v0.16b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v0.16b, v1.16b }, [x14]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v19.16b, v20.16b, v21.16b }, [x10]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v13.16b, v14.16b, v15.16b, v16.16b }, [x9]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1 { v24.8h }, [x27]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v1.8h, v2.8h }, [x27]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ld1 { v0.8h, v1.8h }, [sp], #32
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v21.8h, v22.8h, v23.8h }, [x22]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x21]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1 { v3.4s }, [x4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v11.4s, v12.4s }, [x30]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v0.4s, v1.4s, v2.4s }, [x24]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v15.4s, v16.4s, v17.4s, v18.4s }, [x28]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ld1 { v0.4s, v1.4s, v2.4s }, [x0], #48
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1 { v3.2d }, [x28]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v13.2d, v14.2d }, [x13]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v12.2d, v13.2d, v14.2d }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ld1 { v0.1d }, [x15], x2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v27.1d, v28.1d }, [x7]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v14.1d, v15.1d, v16.1d }, [x3]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v22.1d, v23.1d, v24.1d, v25.1d }, [x4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v0.2s, v1.2s }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v16.2s, v17.2s, v18.2s }, [x27]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v21.2s, v22.2s, v23.2s, v24.2s }, [x21]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v25.4h, v26.4h }, [x3]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v20.4h, v21.4h, v22.4h, v23.4h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v0.4h, v1.4h, v2.4h }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v24.8b, v25.8b }, [x6]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v7.8b, v8.8b, v9.8b }, [x12]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x13]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ld1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - - - - - - - ld1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v0.b }[7], [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v0.h }[3], [x0], #2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v18.h }[3], [x1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v0.s }[1], [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v0.d }[0], [x15], #8
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v11.d }[0], [x13]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 - - - - - - ld1 { v0.8h }, [x15], x2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - ld1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v0.b }[9], [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.17 0.17 0.17 0.17 0.17 0.17 ld1 { v0.b }[9], [x0], #1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v0.16b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v0.8h }, [x0], #2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v0.4s }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v3.1d }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v0.2d }, [x15], x16
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v18.2d }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v8.8b }, [x23]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v28.4h }, [x9]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v3.8h }, [x16]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v10.2s }, [x20]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.4h, v1.4h }, [x21]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v8.8h, v9.8h }, [x28]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v2.2s, v3.2s }, [x16]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v22.4s, v23.4s }, [x4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v22.2d, v23.2d }, [x17]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v29.b, v30.b }[3], [x1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v26.s, v27.s }[1], [x17]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v1.d, v2.d }[0], [x10]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.16b, v1.16b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v13.8b, v14.8b }, [x4]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.8b, v1.8b }, [x0], #16
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v0.16b }, [x0], #1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v0.8h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.17 0.17 0.17 0.17 0.17 0.17 ld1r { v0.8h }, [x15], #2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.h, v1.h }[7], [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.h, v1.h }[7], [x15], x8
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2 { v0.h, v1.h }[7], [x15], #4
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v10.16b, v11.16b }, [x23]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.4h, v1.4h }, [x0], #4
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v25.4h, v26.4h }, [x11]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v23.8h, v24.8h }, [x10]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.2s, v1.2s }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v8.4s, v9.4s }, [x17]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.1d, v1.1d }, [sp], x8
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v9.1d, v10.1d }, [x25]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v26.2d, v27.2d }, [x8]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v8.8b, v9.8b, v10.8b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v15.16b, v16.16b, v17.16b }, [x5]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.2d, v1.2d }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.2d, v1.2d }, [x0], #16
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.4s, v1.4s }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2r { v0.4s, v1.4s }, [sp], #8
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v0.8h, v1.8h, v2.8h }, [x15], #48
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v7.8h, v8.8h, v9.8h }, [x21]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v16.2s, v17.2s, v18.2s }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v12.4s, v13.4s, v14.4s }, [x25]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v17.b, v18.b, v19.b }[2], [x27]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v18.h, v19.h, v20.h }[5], [x16]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v10.2d, v11.2d, v12.2d }, [x18]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v0.s, v1.s, v2.s }[3], [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3 { v5.d, v6.d, v7.d }[1], [x14]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v0.8b, v1.8b, v2.8b }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v17.16b, v18.16b, v19.16b }, [x3]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v3.4h, v4.4h, v5.4h }, [x1]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v6.8h, v7.8h, v8.8h }, [x28]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v0.2s, v1.2s, v2.2s }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v28.4s, v29.4s, v30.4s }, [x2]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v0.1d, v1.1d, v2.1d }, [x0], x0
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v1.1d, v2.1d, v3.1d }, [x28]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v8.2d, v9.2d, v10.2d }, [x3]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v6.8b, v7.8b, v8.8b, v9.8b }, [x27]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4 { v11.16b, v12.16b, v13.16b, v14.16b }, [x5]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v21.4h, v22.4h, v23.4h, v24.4h }, [x14]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4 { v9.8h, v10.8h, v11.8h, v12.8h }, [x1]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4 { v17.4s, v18.4s, v19.4s, v20.4s }, [x4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v0.8b, v1.8b, v2.8b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x24]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v4.b, v5.b, v6.b, v7.b }[12], [x27]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v5.h, v6.h, v7.h, v8.h }[0], [x4]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4 { v0.s, v1.s, v2.s, v3.s }[0], [x26]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v20.8b, v21.8b, v22.8b, v23.8b }, [x23]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x25]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v16.4h, v17.4h, v18.4h, v19.4h }, [x6]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v4.8h, v5.8h, v6.8h, v7.8h }, [x23]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x30]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #16
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v7.4s, v8.4s, v9.4s, v10.4s }, [x23]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], x8
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.67 0.67 0.67 0.67 ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mla v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mla v15.8h, v22.8h, v4.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mla v28.2s, v10.2s, v2.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mls v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mls v25.8h, v29.8h, v0.h[4]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mls v22.2s, v29.2s, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mls v26.4s, v5.4s, v28.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov b0, v0.b[15]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov d6, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov h2, v0.h[5]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov s17, v0.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov w8, v8.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov x30, v18.d[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v2.b[0], v0.b[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v2.h[1], v0.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v2.s[2], v0.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v2.d[1], v0.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v0.b[0], w8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v0.h[1], w8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v0.s[2], w8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v0.d[1], x8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi d15, #0xff00ff00ff00ff
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v0.16b, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v14.8h, #174
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v13.4h, #74, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v0.2d, #0xff0000ff0000ffff
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v0.2s, #8, msl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v19.2s, #226
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v1.4s, #122, msl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v0.4s, #255, lsl #24
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 movi v0.8b, #255
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mul v26.4h, v20.4h, v14.h[5]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mul v5.8h, v21.8h, v3.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mul v29.2s, v10.2s, v3.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mul v30.4s, v11.4s, v4.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mul v30.4s, v11.4s, v4.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - mul v3.8h, v9.8h, v8.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mvni v9.4h, #237
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mvni v8.8h, #171, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mvni v22.4s, #15, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mvni v0.2s, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mvni v0.4s, #16, msl #16
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg d29, d24
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 neg v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mvn v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mvn v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 orn v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 orn v29.8b, v19.8b, v16.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 mov v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 orr v9.4h, #18
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 orr v0.8h, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 orr v4.4s, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - pmul v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - pmul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - pmull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - pmull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 raddhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 raddhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 raddhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 raddhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 raddhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 raddhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rbit v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rbit v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev16 v21.8b, v1.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev16 v30.16b, v31.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev32 v0.4h, v9.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev32 v21.8b, v1.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev32 v30.16b, v31.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev32 v4.8h, v7.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev64 v0.16b, v31.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev64 v1.8b, v9.8b
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rev64 v6.4s, v8.4s
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 rsubhn v0.2s, v0.2d, v0.2d
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabd v12.2s, v11.2s, v27.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sabdl2 v0.8h, v0.16b, v0.16b
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sadalp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sadalp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sadalp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sadalp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sadalp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddlp v0.1d, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddlp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddlp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddlp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddlp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddlp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - saddlv d0, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - saddlv s0, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - saddlv s0, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - saddlv h0, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - saddlv h0, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 saddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf h4, h8, #9
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf h5, h14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf d21, d12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf d21, d12, #64
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf s22, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf s22, s13, #32
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v25.4h, v13.4h, #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - scvtf v4.8h, v8.8h, #10
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sdot v0.2s, v0.8b, v0.4b[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sdot v0.2s, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sdot v0.4s, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sdot v0.4s, v0.16b, v0.4b[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shadd v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shadd v25.16b, v1.16b, v10.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shl d7, d10, #12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shl v23.8b, v18.8b, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shl v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shl v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shl v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shl v0.8h, v23.8h, #10
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shl v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shll v0.4s, v0.4h, #16
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shll v0.8h, v0.8b, #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shll v0.2d, v0.2s, #32
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shll2 v0.2d, v0.4s, #32
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shll2 v0.4s, v0.8h, #16
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shll2 v0.8h, v0.16b, #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shsub v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 shsub v15.8h, v5.8h, v27.8h
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sli v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sli v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sli v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sli v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sli v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sli v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sli v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smax v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smax v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smax v30.16b, v3.16b, v30.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smaxp v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smaxp v21.8h, v16.8h, v7.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smaxp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.42 0.42 0.17 0.42 0.42 0.17 smaxv b0, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - smaxv b0, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smaxv h0, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.42 0.42 0.17 0.42 0.42 0.17 smaxv h0, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smaxv s0, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smin v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 smin v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sminp v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sminp v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.42 0.42 0.17 0.42 0.42 0.17 sminv b0, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - sminv b0, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sminv h0, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.42 0.42 0.17 0.42 0.42 0.17 sminv h0, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sminv s0, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal v0.2d, v25.2s, v1.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal v16.4s, v9.4h, v11.h[4]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal2 v30.2d, v22.4s, v7.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl v25.2d, v27.2s, v1.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl v14.4s, v23.4h, v12.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlal2 v1.4s, v9.8h, v0.h[6]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl2 v12.4s, v11.8h, v12.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl2 v11.2d, v28.4s, v7.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smlsl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull v31.2d, v23.2s, v6.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull v3.4s, v26.4h, v1.h[5]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull2 v11.2d, v1.4s, v7.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull2 v13.4s, v18.8h, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - smull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs b19, b14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs d18, d12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs h21, h15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs s20, s12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqabs v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqadd b20, b11, b15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqadd h12, h18, h10
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal d19, s24, s12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal d8, s9, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal s0, h0, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal s17, h27, h12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal v11.2d, v24.2s, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal v20.4s, v30.4h, v12.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal2 v23.2d, v30.4s, v6.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlal2 v2.4s, v17.8h, v5.h[6]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh v8.4h, v16.4h, v5.h[4]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh v16.2s, v24.2s, v7.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull v8.4s, v19.4h, v1.h[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull v20.2d, v10.2s, v6.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull2 v10.4s, v25.8h, v0.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull2 v4.2d, v29.4s, v2.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh v0.8h, v15.8h, v0.h[5]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh v6.2s, v29.2s, v4.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh v31.2s, v17.2s, v4.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl d12, s23, s13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl d8, s9, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl s0, h0, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl s14, h12, h25
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl v26.2d, v7.2s, v3.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl v4.4s, v22.4h, v13.h[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl2 v4.2d, v3.4s, v3.s[2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmlsl2 v2.4s, v28.8h, v4.h[6]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh h10, h11, h12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh s20, s21, s2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmulh v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull d1, s1, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull d15, s22, s12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull s1, h1, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull s12, h22, h12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqdmull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg b19, b14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg d18, d12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg h21, h15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg s20, s12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqneg v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah h0, h1, v2.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.4h, v1.4h, v2.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.8h, v1.8h, v2.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah s0, s1, v2.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.2s, v1.2s, v2.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.4s, v1.4s, v2.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah h0, h1, h2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.4h, v1.4h, v2.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah s0, s1, s2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.2s, v1.2s, v2.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlah v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh h0, h1, v2.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.4h, v1.4h, v2.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.8h, v1.8h, v2.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh s0, s1, v2.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.2s, v1.2s, v2.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.4s, v1.4s, v2.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh h0, h1, h2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.4h, v1.4h, v2.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.8h, v1.8h, v2.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh s0, s1, s2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.2s, v1.2s, v2.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmlsh v0.4s, v1.4s, v2.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh h10, h11, h12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh s20, s21, s2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - sqrdmulh v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshl d31, d31, d31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshl h3, h4, h15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl s17, s4, s23
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqsub b3, b13, b12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqsub v20.8h, v18.8h, v12.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn b10, h13, #2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn h15, s10, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn s15, d12, #9
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun b17, h10, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun h10, s13, #15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun s22, d16, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqrshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl b11, b19, #7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl d15, d16, #51
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl d31, d31, d31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl h13, h18, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl h3, h4, h15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl s14, s17, #22
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v23.16b, v23.16b, v23.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshl v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu b15, b18, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu d11, d13, #32
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu h19, h17, #6
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu s16, s14, #25
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshlu v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn b10, h15, #5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn h17, s10, #4
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn s18, d10, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun b15, h10, #7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun h20, s14, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun s10, d15, #15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqsub s20, s10, s7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqsub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqsub v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqsub v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn b18, h18
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn h20, s17
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn s19, d14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn v0.8b, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun b19, h14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun h21, s15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun s20, d12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun v0.8b, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun2 v0.16b, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sqxtun2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srhadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srhadd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srhadd v0.8b, v0.8b, v0.8b
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sri v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sri v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sri v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sri v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sri v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sri v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sri v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshl d16, d16, d16
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshl v0.2s, v0.2s, v0.2s
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr d19, d18, #7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srshr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra d15, d11, #19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 srsra v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshl d31, d31, d31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshll v9.8h, v2.8b, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshll v12.4s, v3.4h, #4
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshll v0.2d, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshll2 v28.8h, v12.16b, #7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshll2 v0.4s, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshll2 v17.2d, v13.4s, #22
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr d15, d16, #12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sshr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra d18, d12, #21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssra v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ssubw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v18.8b }, [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v8.8b, v9.8b }, [x18]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v15.8b, v16.8b, v17.8b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v21.8b, v22.8b, v23.8b, v24.8b }, [x14]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v0.16b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v1.16b, v2.16b }, [x4]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - st1 { v27.16b, v28.16b, v29.16b }, [x18]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st1 { v18.16b, v19.16b, v20.16b, v21.16b }, [x29]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v19.4h }, [x7]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v22.4h, v23.4h }, [x22]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v13.4h, v14.4h, v15.4h }, [x7]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v23.4h, v24.4h, v25.4h, v26.4h }, [x24]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v27.8h }, [x17]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - st1 { v8.8h, v9.8h, v10.8h }, [x16]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x19]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v25.2s }, [x6]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v13.2s, v14.2s }, [x9]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v12.2s, v13.2s, v14.2s }, [x3]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v6.2s, v7.2s, v8.2s, v9.2s }, [x13]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.00 1.00 - - - - st1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v22.4s }, [x19]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v15.4s, v16.4s }, [x12]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st1 { v26.4s, v27.4s, v28.4s, v29.4s }, [x12]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v20.1d }, [x10]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v21.1d, v22.1d }, [x29]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v5.1d, v6.1d, v7.1d }, [x3]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x10]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v26.2d, v27.2d }, [x28]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.50 1.50 - - - - st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - st1 { v13.2d, v14.2d, v15.2d }, [x27]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - st1 { v8.2d }, [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 - - - - st1 { v0.8h }, [x15], x2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.00 1.00 - - - - st1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - st1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.00 1.00 - - - - st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st1 { v1.b }[5], [x1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st1 { v0.h }[2], [x1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st1 { v31.s }[1], [x16]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 - - - - st1 { v0.8h }, [x15], x2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.00 1.00 - - - - st1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st1 { v0.d }[1], [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.17 0.17 0.17 0.17 st1 { v0.d }[1], [x0], #8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v6.16b, v7.16b }, [x23]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v10.4h, v11.4h }, [x18]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v10.8h, v11.8h }, [x18]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v25.2s, v26.2s }, [x29]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v26.4s, v27.4s }, [x14]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st2 { v10.2d, v11.2d }, [x1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st2 { v21.b, v22.b }[15], [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st2 { v28.h, v29.h }[2], [x6]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st2 { v0.s, v1.s }[3], [sp]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.17 0.17 0.17 0.17 st2 { v0.s, v1.s }[3], [sp], #8
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st2 { v17.d, v18.d }[1], [x1]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v10.8b, v11.8b, v12.8b }, [x18]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.67 2.67 0.67 0.67 0.67 0.67 st3 { v26.16b, v27.16b, v28.16b }, [x4]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.67 2.67 0.67 0.67 0.67 0.67 st3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.67 2.67 0.67 0.67 0.67 0.67 st3 { v0.8h, v1.8h, v2.8h }, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v19.2s, v20.2s, v21.2s }, [x30]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.67 2.67 0.67 0.67 0.67 0.67 st3 { v24.4s, v25.4s, v26.4s }, [x8]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.67 2.67 0.67 0.67 0.67 0.67 st3 { v24.2d, v25.2d, v26.2d }, [x25]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v8.b, v9.b, v10.b }[4], [x18]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v0.h, v1.h, v2.h }[7], [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v0.h, v1.h, v2.h }[7], [x15], #6
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v9.s, v10.s, v11.s }[2], [x20]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - 1.33 1.33 0.33 0.33 0.33 0.33 st3 { v16.d, v17.d, v18.d }[0], [x13]
+# CHECK-NEXT: - - - - - - - - - - - - 3.00 3.00 - - - - - - - - 4.00 4.00 1.00 1.00 1.00 1.00 st4 { v17.8b, v18.8b, v19.8b, v20.8b }, [x8]
+# CHECK-NEXT: - - - - - - - - - - - - 6.00 6.00 - - - - - - - - 8.00 8.00 2.00 2.00 2.00 2.00 st4 { v7.16b, v8.16b, v9.16b, v10.16b }, [x15]
+# CHECK-NEXT: - - - - - - - - - - - - 3.00 3.00 - - - - - - - - 4.00 4.00 1.00 1.00 1.00 1.00 st4 { v5.4h, v6.4h, v7.4h, v8.4h }, [x13]
+# CHECK-NEXT: - - - - - - - - - - - - 6.00 6.00 - - - - - - - - 8.00 8.00 2.00 2.00 2.00 2.00 st4 { v11.8h, v12.8h, v13.8h, v14.8h }, [x1]
+# CHECK-NEXT: - - - - - - - - - - - - 3.00 3.00 - - - - - - - - 4.00 4.00 1.00 1.00 1.00 1.00 st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - - - - - - - - 6.00 6.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 8.00 8.00 2.00 2.00 2.00 2.00 st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: - - - - - - - - - - - - 6.00 6.00 - - - - - - - - 8.00 8.00 2.00 2.00 2.00 2.00 st4 { v21.4s, v22.4s, v23.4s, v24.4s }, [x6]
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 4.00 - - - - - - - - 5.33 5.33 1.33 1.33 1.33 1.33 st4 { v25.2d, v26.2d, v27.2d, v28.2d }, [x16]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st4 { v0.b, v1.b, v2.b, v3.b }[15], [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st4 { v5.h, v6.h, v7.h, v8.h }[4], [x13]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st4 { v22.s, v23.s, v24.s, v25.s }[0], [x7]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st4 { v23.d, v24.d, v25.d, v26.d }[1], [x5]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.67 0.67 0.17 0.17 0.17 0.17 st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.17 0.17 0.17 0.17 st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.67 0.67 0.17 0.17 0.17 0.17 st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], x5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub d15, d5, d16
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub v15.2s, v14.2s, v11.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 subhn v7.4h, v10.4s, v13.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 subhn2 v24.4s, v24.2d, v8.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd b19, b14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd d18, d22
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd h20, h15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd s21, s12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 suqadd v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 tbl v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 tbl v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 tbl v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 tbl v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 tbx v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 tbx v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.83 0.83 0.83 0.83 0.83 0.83 tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 tbx v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 tbx v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.83 0.83 0.83 0.83 0.83 0.83 tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 trn2 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaba v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaba v13.16b, v14.16b, v19.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabd v23.4s, v4.4s, v30.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uabdl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uadalp v0.1d, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uadalp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uadalp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uadalp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uadalp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uadalp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddlp v0.1d, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddlp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddlp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddlp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddlp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddlp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - uaddlv d0, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - uaddlv s0, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - uaddlv s0, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - uaddlv h0, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - uaddlv h0, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uaddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - - - - - - - ucvtf h17, x12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - ucvtf h22, h16, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - ucvtf h7, h21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - ucvtf d21, d14
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uqsub d16, d16, d16
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uqxtn h20, s17
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uqxtn s19, d14
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - urecpe v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - urecpe v0.4s, v0.4s
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 urshr v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 urshr v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 urshr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - ursqrte v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 - 0.50 0.50 - ursqrte v0.4s, v0.4s
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ursra v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ursra v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ursra v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ursra v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ursra v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ursra v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ursra v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushl d0, d0, d0
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushll v18.8h, v24.8b, #4
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushll v16.2d, v16.2s, #31
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushll2 v31.2d, v12.4s, #11
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushll2 v18.4s, v22.8h, #13
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushll2 v0.8h, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushr d10, d17, #18
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushr v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushr v0.2d, v0.2d, #3
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushr v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushr v0.4s, v0.4s, #3
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 ushr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov w15, v22.b[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov w26, v27.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov x21, v0.b[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov x9, v27.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov x15, v3.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov w0, v0.b[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov w0, v0.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov x0, v0.b[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov x0, v0.h[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 smov x0, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usqadd b19, b14
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usqadd d18, d22
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usqadd h20, h15
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usqadd s21, s12
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usqadd v0.16b, v0.16b
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 usubl2 v0.2d, v0.4s, v0.4s
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 v0.8h, v0.8h, v0.8h
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-rcpc-immo-instructions.s
new file mode 100644
index 0000000..e42b161
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-rcpc-immo-instructions.s
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -instruction-tables < %p/../Inputs/rcpc-immo-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.25 * ldapur w7, [x24]
+# CHECK-NEXT: 1 4 0.25 * ldapur x20, [x13]
+# CHECK-NEXT: 1 4 0.25 * ldapurb w13, [x17]
+# CHECK-NEXT: 1 4 0.25 * ldapurh w3, [x22]
+# CHECK-NEXT: 1 4 0.25 * U ldapursb w7, [x8]
+# CHECK-NEXT: 1 4 0.25 * U ldapursb x29, [x7]
+# CHECK-NEXT: 1 4 0.25 * U ldapursh w17, [x19]
+# CHECK-NEXT: 1 4 0.25 * U ldapursh x3, [x3]
+# CHECK-NEXT: 1 4 0.25 * U ldapursw x3, [x18]
+# CHECK-NEXT: 1 1 0.50 * stlur w3, [x27]
+# CHECK-NEXT: 1 1 0.50 * stlur x23, [x25]
+# CHECK-NEXT: 1 1 0.50 * stlurb w30, [x17]
+# CHECK-NEXT: 1 1 0.50 * stlurh w9, [x29]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - 2.00 2.00 - - - - 2.25 2.25 4.25 4.25 - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapur w7, [x24]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapur x20, [x13]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapurb w13, [x17]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapurh w3, [x22]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapursb w7, [x8]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapursb x29, [x7]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapursh w17, [x19]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapursh x3, [x3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldapursw x3, [x18]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stlur w3, [x27]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stlur x23, [x25]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stlurb w30, [x17]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - 0.50 0.50 - - - - - - - - - - - - - - stlurh w9, [x29]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
new file mode 100644
index 0000000..60d131b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
@@ -0,0 +1,6877 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/../Inputs/sve-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.17 abs z0.b, p0/m, z0.b
+# CHECK-NEXT: 1 2 0.17 abs z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 abs z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 0.17 abs z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.17 abs z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 abs z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 abs z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 abs z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 adclb z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 adclb z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 adclt z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 adclt z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 add z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 add z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 add z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 add z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 add z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 add z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 add z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 add z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 add z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 add z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 add z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 add z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 add z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 add z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 add z0.s, z1.s, z2.s
+# CHECK-NEXT: 1 2 0.17 add z21.b, p5/m, z21.b, z10.b
+# CHECK-NEXT: 1 2 0.17 add z21.b, z10.b, z21.b
+# CHECK-NEXT: 1 2 0.17 add z21.d, p5/m, z21.d, z10.d
+# CHECK-NEXT: 1 2 0.17 add z21.d, z10.d, z21.d
+# CHECK-NEXT: 1 2 0.17 add z21.h, p5/m, z21.h, z10.h
+# CHECK-NEXT: 1 2 0.17 add z21.h, z10.h, z21.h
+# CHECK-NEXT: 1 2 0.17 add z21.s, p5/m, z21.s, z10.s
+# CHECK-NEXT: 1 2 0.17 add z21.s, z10.s, z21.s
+# CHECK-NEXT: 1 2 0.17 add z23.b, p3/m, z23.b, z13.b
+# CHECK-NEXT: 1 2 0.17 add z23.b, z13.b, z8.b
+# CHECK-NEXT: 1 2 0.17 add z23.d, p3/m, z23.d, z13.d
+# CHECK-NEXT: 1 2 0.17 add z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.17 add z23.h, p3/m, z23.h, z13.h
+# CHECK-NEXT: 1 2 0.17 add z23.h, z13.h, z8.h
+# CHECK-NEXT: 1 2 0.17 add z23.s, p3/m, z23.s, z13.s
+# CHECK-NEXT: 1 2 0.17 add z23.s, z13.s, z8.s
+# CHECK-NEXT: 1 2 0.17 add z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 add z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 add z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 add z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 add z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.17 add z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 add z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 add z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.17 add z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 add z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 add z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.17 add z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 addhnb z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 addhnb z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 addhnb z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 addhnt z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 addhnt z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 addhnt z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 addp z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 addp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 addp z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 addp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 1 0.13 addpl sp, sp, #31
+# CHECK-NEXT: 1 1 0.13 addpl x0, x0, #-32
+# CHECK-NEXT: 1 1 0.13 addpl x21, x21, #0
+# CHECK-NEXT: 1 1 0.13 addpl x23, x8, #-1
+# CHECK-NEXT: 1 1 0.13 addvl sp, sp, #31
+# CHECK-NEXT: 1 1 0.13 addvl x0, x0, #-32
+# CHECK-NEXT: 1 1 0.13 addvl x21, x21, #0
+# CHECK-NEXT: 1 1 0.13 addvl x23, x8, #-1
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, lsl #1]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, lsl #2]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, lsl #3]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, sxtw #1]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, sxtw #2]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, sxtw #3]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, sxtw]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, uxtw #1]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, uxtw #2]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, uxtw #3]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d, uxtw]
+# CHECK-NEXT: 1 2 0.17 adr z0.d, [z0.d, z0.d]
+# CHECK-NEXT: 1 2 0.17 adr z0.s, [z0.s, z0.s, lsl #1]
+# CHECK-NEXT: 1 2 0.17 adr z0.s, [z0.s, z0.s, lsl #2]
+# CHECK-NEXT: 1 2 0.17 adr z0.s, [z0.s, z0.s, lsl #3]
+# CHECK-NEXT: 1 2 0.17 adr z0.s, [z0.s, z0.s]
+# CHECK-NEXT: 1 2 0.25 aesd z0.b, z0.b, z31.b
+# CHECK-NEXT: 1 2 0.25 aese z0.b, z0.b, z31.b
+# CHECK-NEXT: 1 2 0.25 aesimc z0.b, z0.b
+# CHECK-NEXT: 1 2 0.25 aesimc z31.b, z31.b
+# CHECK-NEXT: 1 2 0.25 aesmc z0.b, z0.b
+# CHECK-NEXT: 1 2 0.25 aesmc z31.b, z31.b
+# CHECK-NEXT: 1 2 1.00 and p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 2 0.17 and z0.d, z0.d, #0x6
+# CHECK-NEXT: 1 2 0.17 and z0.d, z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.17 and z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 and z0.s, z0.s, #0x6
+# CHECK-NEXT: 1 2 0.17 and z0.s, z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.17 and z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.17 and z23.h, z23.h, #0x6
+# CHECK-NEXT: 1 2 0.17 and z23.h, z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.17 and z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 and z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 and z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 and z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 and z5.b, z5.b, #0x6
+# CHECK-NEXT: 1 2 0.17 and z5.b, z5.b, #0xf9
+# CHECK-NEXT: 1 2 1.00 ands p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 4 0.33 andv b0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 andv d0, p7, z31.d
+# CHECK-NEXT: 1 4 0.33 andv h0, p7, z31.h
+# CHECK-NEXT: 1 4 0.33 andv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 asr z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 asr z0.b, p0/m, z0.b, z1.d
+# CHECK-NEXT: 1 2 0.17 asr z0.b, z0.b, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.b, z1.b, z2.d
+# CHECK-NEXT: 1 2 0.17 asr z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 asr z0.d, z0.d, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 asr z0.h, p0/m, z0.h, z1.d
+# CHECK-NEXT: 1 2 0.17 asr z0.h, z0.h, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.h, z1.h, z2.d
+# CHECK-NEXT: 1 2 0.17 asr z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 asr z0.s, p0/m, z0.s, z1.d
+# CHECK-NEXT: 1 2 0.17 asr z0.s, z0.s, #1
+# CHECK-NEXT: 1 2 0.17 asr z0.s, z1.s, z2.d
+# CHECK-NEXT: 1 2 0.17 asr z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 2 0.17 asr z31.b, z31.b, #8
+# CHECK-NEXT: 1 2 0.17 asr z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 2 0.17 asr z31.d, z31.d, #64
+# CHECK-NEXT: 1 2 0.17 asr z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 2 0.17 asr z31.h, z31.h, #16
+# CHECK-NEXT: 1 2 0.17 asr z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 asr z31.s, z31.s, #32
+# CHECK-NEXT: 1 4 0.17 asrd z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 4 0.17 asrd z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 asrd z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 asrd z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 asrd z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 4 0.17 asrd z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 4 0.17 asrd z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 4 0.17 asrd z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 asrr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 asrr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 asrr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 asrr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 bcax z29.d, z29.d, z30.d, z31.d
+# CHECK-NEXT: 1 6 2.00 bdep z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 6 2.00 bdep z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 6 2.00 bdep z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 6 2.00 bdep z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 6 2.00 bext z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 6 2.00 bext z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 6 2.00 bext z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 6 2.00 bext z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.25 bfcvt z0.h, p0/m, z1.s
+# CHECK-NEXT: 1 3 0.25 bfcvtnt z0.h, p0/m, z1.s
+# CHECK-NEXT: 1 4 0.17 bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 4 0.17 bfdot z0.s, z1.h, z2.h[0]
+# CHECK-NEXT: 1 4 0.17 bfdot z0.s, z1.h, z2.h[3]
+# CHECK-NEXT: 1 5 0.17 bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 5 0.17 bfmlalb z0.s, z1.h, z2.h[0]
+# CHECK-NEXT: 1 5 0.17 bfmlalb z0.s, z1.h, z2.h[7]
+# CHECK-NEXT: 1 5 0.17 bfmlalb z10.s, z21.h, z14.h
+# CHECK-NEXT: 1 5 0.17 bfmlalb z21.s, z14.h, z3.h[2]
+# CHECK-NEXT: 1 5 0.17 bfmlalt z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 5 0.17 bfmlalt z0.s, z1.h, z2.h[0]
+# CHECK-NEXT: 1 5 0.17 bfmlalt z0.s, z1.h, z2.h[7]
+# CHECK-NEXT: 1 5 0.17 bfmlalt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 5 0.17 bfmlalt z14.s, z10.h, z21.h
+# CHECK-NEXT: 1 5 0.17 bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 6 2.00 bgrp z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 6 2.00 bgrp z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 6 2.00 bgrp z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 6 2.00 bgrp z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 1.00 bic p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 bic p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.17 bic z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 bic z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.17 bic z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 bic z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 bic z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 bic z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 1.00 bics p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 bics p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 1 0.50 brka p0.b, p15/m, p15.b
+# CHECK-NEXT: 1 1 0.50 brka p0.b, p15/z, p15.b
+# CHECK-NEXT: 1 1 0.50 brkas p0.b, p15/z, p15.b
+# CHECK-NEXT: 1 1 0.50 brkb p0.b, p15/m, p15.b
+# CHECK-NEXT: 1 1 0.50 brkb p0.b, p15/z, p15.b
+# CHECK-NEXT: 1 1 0.50 brkbs p0.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 1.00 brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1 2 1.00 brkn p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1 2 1.00 brkns p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 brkpa p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 1 2 1.00 brkpa p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 brkpas p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 1 2 1.00 brkpas p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 brkpb p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 1 2 1.00 brkpb p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 brkpbs p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 1 2 1.00 brkpbs p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.17 bsl z0.d, z0.d, z1.d, z2.d
+# CHECK-NEXT: 1 2 0.17 bsl1n z0.d, z0.d, z1.d, z2.d
+# CHECK-NEXT: 1 2 0.17 bsl2n z0.d, z0.d, z1.d, z2.d
+# CHECK-NEXT: 1 2 0.17 cadd z0.b, z0.b, z0.b, #90
+# CHECK-NEXT: 1 2 0.17 cadd z0.d, z0.d, z0.d, #90
+# CHECK-NEXT: 1 2 0.17 cadd z0.h, z0.h, z0.h, #90
+# CHECK-NEXT: 1 2 0.17 cadd z0.s, z0.s, z0.s, #90
+# CHECK-NEXT: 1 2 0.17 cadd z31.b, z31.b, z31.b, #270
+# CHECK-NEXT: 1 2 0.17 cadd z31.d, z31.d, z31.d, #270
+# CHECK-NEXT: 1 2 0.17 cadd z31.h, z31.h, z31.h, #270
+# CHECK-NEXT: 1 2 0.17 cadd z31.s, z31.s, z31.s, #270
+# CHECK-NEXT: 1 3 0.25 cdot z0.d, z1.h, z15.h[1], #0
+# CHECK-NEXT: 1 3 0.25 cdot z0.d, z1.h, z31.h, #0
+# CHECK-NEXT: 1 3 0.25 cdot z0.d, z1.h, z31.h, #180
+# CHECK-NEXT: 1 3 0.25 cdot z0.d, z1.h, z31.h, #270
+# CHECK-NEXT: 1 3 0.25 cdot z0.d, z1.h, z31.h, #90
+# CHECK-NEXT: 1 3 0.17 cdot z0.s, z1.b, z31.b, #0
+# CHECK-NEXT: 1 3 0.17 cdot z0.s, z1.b, z7.b[3], #0
+# CHECK-NEXT: 1 3 0.25 cdot z29.d, z30.h, z0.h[0], #180
+# CHECK-NEXT: 1 3 0.25 cdot z31.d, z30.h, z7.h[1], #270
+# CHECK-NEXT: 1 3 0.25 cdot z5.d, z6.h, z3.h[0], #90
+# CHECK-NEXT: 1 3 1.00 clasta b0, p7, b0, z31.b
+# CHECK-NEXT: 1 3 1.00 clasta d0, p7, d0, z31.d
+# CHECK-NEXT: 1 3 1.00 clasta h0, p7, h0, z31.h
+# CHECK-NEXT: 1 3 1.00 clasta s0, p7, s0, z31.s
+# CHECK-NEXT: 1 8 1.00 clasta w0, p7, w0, z31.b
+# CHECK-NEXT: 1 8 1.00 clasta w0, p7, w0, z31.h
+# CHECK-NEXT: 1 8 1.00 clasta w0, p7, w0, z31.s
+# CHECK-NEXT: 1 8 1.00 clasta x0, p7, x0, z31.d
+# CHECK-NEXT: 1 3 1.00 clasta z0.b, p7, z0.b, z31.b
+# CHECK-NEXT: 1 3 1.00 clasta z0.d, p7, z0.d, z31.d
+# CHECK-NEXT: 1 3 1.00 clasta z0.h, p7, z0.h, z31.h
+# CHECK-NEXT: 1 3 1.00 clasta z0.s, p7, z0.s, z31.s
+# CHECK-NEXT: 1 3 1.00 clastb b0, p7, b0, z31.b
+# CHECK-NEXT: 1 3 1.00 clastb d0, p7, d0, z31.d
+# CHECK-NEXT: 1 3 1.00 clastb h0, p7, h0, z31.h
+# CHECK-NEXT: 1 3 1.00 clastb s0, p7, s0, z31.s
+# CHECK-NEXT: 1 8 1.00 clastb w0, p7, w0, z31.b
+# CHECK-NEXT: 1 8 1.00 clastb w0, p7, w0, z31.h
+# CHECK-NEXT: 1 8 1.00 clastb w0, p7, w0, z31.s
+# CHECK-NEXT: 1 8 1.00 clastb x0, p7, x0, z31.d
+# CHECK-NEXT: 1 3 1.00 clastb z0.b, p7, z0.b, z31.b
+# CHECK-NEXT: 1 3 1.00 clastb z0.d, p7, z0.d, z31.d
+# CHECK-NEXT: 1 3 1.00 clastb z0.h, p7, z0.h, z31.h
+# CHECK-NEXT: 1 3 1.00 clastb z0.s, p7, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 cls z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 cls z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 cls z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 cls z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 clz z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 clz z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 clz z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 clz z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 4 0.25 cmla z0.b, z1.b, z2.b, #0
+# CHECK-NEXT: 1 4 0.25 cmla z0.d, z1.d, z2.d, #0
+# CHECK-NEXT: 1 4 0.25 cmla z0.h, z1.h, z2.h, #0
+# CHECK-NEXT: 1 4 0.25 cmla z0.h, z1.h, z2.h[0], #0
+# CHECK-NEXT: 1 4 0.25 cmla z0.s, z1.s, z2.s, #0
+# CHECK-NEXT: 1 4 0.25 cmla z0.s, z1.s, z2.s[0], #0
+# CHECK-NEXT: 1 4 0.25 cmla z15.b, z16.b, z17.b, #270
+# CHECK-NEXT: 1 4 0.25 cmla z15.d, z16.d, z17.d, #270
+# CHECK-NEXT: 1 4 0.25 cmla z15.h, z16.h, z17.h, #270
+# CHECK-NEXT: 1 4 0.25 cmla z15.s, z16.s, z17.s, #270
+# CHECK-NEXT: 1 4 0.25 cmla z29.b, z30.b, z31.b, #90
+# CHECK-NEXT: 1 4 0.25 cmla z29.d, z30.d, z31.d, #90
+# CHECK-NEXT: 1 4 0.25 cmla z29.h, z30.h, z31.h, #90
+# CHECK-NEXT: 1 4 0.25 cmla z29.s, z30.s, z31.s, #90
+# CHECK-NEXT: 1 4 0.25 cmla z31.b, z31.b, z31.b, #180
+# CHECK-NEXT: 1 4 0.25 cmla z31.d, z31.d, z31.d, #180
+# CHECK-NEXT: 1 4 0.25 cmla z31.h, z30.h, z7.h[0], #180
+# CHECK-NEXT: 1 4 0.25 cmla z31.h, z31.h, z31.h, #180
+# CHECK-NEXT: 1 4 0.25 cmla z31.s, z30.s, z7.s[0], #180
+# CHECK-NEXT: 1 4 0.25 cmla z31.s, z31.s, z31.s, #180
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpeq p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmpge p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 1 2 1.00 cmpge p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 1 2 1.00 cmpge p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmpge p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpge p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmpge p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 1 2 1.00 cmpge p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 1 2 1.00 cmpge p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpge p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpge p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 1 2 1.00 cmpge p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 1 2 1.00 cmpge p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpge p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmpge p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmpge p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 1 2 1.00 cmpge p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 1 2 1.00 cmpge p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpge p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmpge p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmpgt p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmphi p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 1 2 1.00 cmphi p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 1 2 1.00 cmphi p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmphi p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphi p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmphi p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 1 2 1.00 cmphi p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 1 2 1.00 cmphi p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphi p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphi p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 1 2 1.00 cmphi p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 1 2 1.00 cmphi p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphi p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmphi p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmphi p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 1 2 1.00 cmphi p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 1 2 1.00 cmphi p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphi p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmphi p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmphs p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 1 2 1.00 cmphs p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 1 2 1.00 cmphs p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmphs p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphs p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmphs p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 1 2 1.00 cmphs p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 1 2 1.00 cmphs p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphs p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphs p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 1 2 1.00 cmphs p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 1 2 1.00 cmphs p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphs p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmphs p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmphs p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 1 2 1.00 cmphs p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 1 2 1.00 cmphs p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmphs p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmphs p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 cmple p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 1 2 1.00 cmple p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 1 2 1.00 cmple p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmple p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 1 2 1.00 cmple p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 1 2 1.00 cmple p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 1 2 1.00 cmple p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 1 2 1.00 cmple p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmple p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 1 2 1.00 cmple p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 1 2 1.00 cmple p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmplo p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 1 2 1.00 cmplo p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 1 2 1.00 cmplo p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmplo p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 1 2 1.00 cmplo p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 1 2 1.00 cmplo p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 1 2 1.00 cmplo p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 1 2 1.00 cmplo p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmplo p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 1 2 1.00 cmplo p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 1 2 1.00 cmplo p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpls p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 1 2 1.00 cmpls p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 1 2 1.00 cmpls p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpls p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 1 2 1.00 cmpls p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 1 2 1.00 cmpls p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 1 2 1.00 cmpls p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 1 2 1.00 cmpls p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpls p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 1 2 1.00 cmpls p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 1 2 1.00 cmpls p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmplt p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 1 2 1.00 cmplt p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 1 2 1.00 cmplt p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmplt p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 1 2 1.00 cmplt p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 1 2 1.00 cmplt p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 1 2 1.00 cmplt p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 1 2 1.00 cmplt p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmplt p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 1 2 1.00 cmplt p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 1 2 1.00 cmplt p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpne p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 1 2 1.00 cmpne p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 1 2 1.00 cmpne p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 cmpne p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpne p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 1 2 1.00 cmpne p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 1 2 1.00 cmpne p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpne p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 1 2 1.00 cmpne p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 1 2 1.00 cmpne p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpne p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 cmpne p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 1 2 1.00 cmpne p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 1 2 1.00 cmpne p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 1 2 1.00 cmpne p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 cnot z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 cnot z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 cnot z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 cnot z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 cnt z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 cnt z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 cnt z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 cnt z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 1 0.13 cntb x0
+# CHECK-NEXT: 1 1 0.13 cntb x0, #28
+# CHECK-NEXT: 1 1 0.13 cntb x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 cntb x0, pow2
+# CHECK-NEXT: 1 1 0.13 cntd x0
+# CHECK-NEXT: 1 1 0.13 cntd x0, #28
+# CHECK-NEXT: 1 1 0.13 cntd x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 cntd x0, pow2
+# CHECK-NEXT: 1 1 0.13 cnth x0
+# CHECK-NEXT: 1 1 0.13 cnth x0, #28
+# CHECK-NEXT: 1 1 0.13 cnth x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 cnth x0, pow2
+# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.b
+# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.d
+# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.h
+# CHECK-NEXT: 1 2 0.50 cntp x0, p15, p0.s
+# CHECK-NEXT: 1 1 0.13 cntw x0
+# CHECK-NEXT: 1 1 0.13 cntw x0, #28
+# CHECK-NEXT: 1 1 0.13 cntw x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 cntw x0, pow2
+# CHECK-NEXT: 1 3 1.00 compact z31.d, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 compact z31.s, p7, z31.s
+# CHECK-NEXT: 1 1 1.00 ctermeq w30, wzr
+# CHECK-NEXT: 1 1 1.00 ctermeq wzr, w30
+# CHECK-NEXT: 1 1 1.00 ctermeq x30, xzr
+# CHECK-NEXT: 1 1 1.00 ctermeq xzr, x30
+# CHECK-NEXT: 1 1 1.00 ctermne w30, wzr
+# CHECK-NEXT: 1 1 1.00 ctermne wzr, w30
+# CHECK-NEXT: 1 1 1.00 ctermne x30, xzr
+# CHECK-NEXT: 1 1 1.00 ctermne xzr, x30
+# CHECK-NEXT: 1 1 0.13 decb x0
+# CHECK-NEXT: 1 1 0.13 decb x0, #14
+# CHECK-NEXT: 1 1 0.13 decb x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 decb x0, pow2
+# CHECK-NEXT: 1 1 0.13 decb x0, vl1
+# CHECK-NEXT: 1 1 0.13 decd x0
+# CHECK-NEXT: 1 1 0.13 decd x0, #14
+# CHECK-NEXT: 1 1 0.13 decd x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 decd x0, pow2
+# CHECK-NEXT: 1 1 0.13 decd x0, vl1
+# CHECK-NEXT: 1 1 0.13 dech x0
+# CHECK-NEXT: 1 1 0.13 dech x0, #14
+# CHECK-NEXT: 1 1 0.13 dech x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 dech x0, pow2
+# CHECK-NEXT: 1 1 0.13 dech x0, vl1
+# CHECK-NEXT: 1 2 0.50 decp x0, p0.b
+# CHECK-NEXT: 1 2 0.50 decp x0, p0.d
+# CHECK-NEXT: 1 2 0.50 decp x0, p0.h
+# CHECK-NEXT: 1 2 0.50 decp x0, p0.s
+# CHECK-NEXT: 1 2 0.50 decp xzr, p15.b
+# CHECK-NEXT: 1 2 0.50 decp xzr, p15.d
+# CHECK-NEXT: 1 2 0.50 decp xzr, p15.h
+# CHECK-NEXT: 1 2 0.50 decp xzr, p15.s
+# CHECK-NEXT: 1 7 1.00 decp z31.d, p15.d
+# CHECK-NEXT: 1 7 1.00 decp z31.h, p15.h
+# CHECK-NEXT: 1 7 1.00 decp z31.s, p15.s
+# CHECK-NEXT: 1 1 0.13 decw x0
+# CHECK-NEXT: 1 1 0.13 decw x0, #14
+# CHECK-NEXT: 1 1 0.13 decw x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 decw x0, pow2
+# CHECK-NEXT: 1 1 0.13 decw x0, vl1
+# CHECK-NEXT: 1 2 0.17 dupm z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.17 dupm z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.17 dupm z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.17 dupm z5.b, #0xf9
+# CHECK-NEXT: 1 2 1.00 eor p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 2 0.17 eor z0.d, z0.d, #0x6
+# CHECK-NEXT: 1 2 0.17 eor z0.d, z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.17 eor z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 eor z0.s, z0.s, #0x6
+# CHECK-NEXT: 1 2 0.17 eor z0.s, z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.17 eor z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.17 eor z23.h, z23.h, #0x6
+# CHECK-NEXT: 1 2 0.17 eor z23.h, z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.17 eor z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 eor z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 eor z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 eor z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 eor z5.b, z5.b, #0x6
+# CHECK-NEXT: 1 2 0.17 eor z5.b, z5.b, #0xf9
+# CHECK-NEXT: 1 2 0.17 eor3 z29.d, z29.d, z30.d, z31.d
+# CHECK-NEXT: 1 2 0.17 eorbt z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 2 0.17 eorbt z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 eorbt z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 eorbt z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 1.00 eors p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 2 0.17 eortb z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 2 0.17 eortb z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 eortb z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 eortb z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.33 eorv b0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 eorv d0, p7, z31.d
+# CHECK-NEXT: 1 4 0.33 eorv h0, p7, z31.h
+# CHECK-NEXT: 1 4 0.33 eorv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 ext z0.b, { z1.b, z2.b }, #0
+# CHECK-NEXT: 1 2 0.17 ext z31.b, z31.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 ext z31.b, z31.b, z0.b, #255
+# CHECK-NEXT: 1 2 0.17 ext z31.b, { z30.b, z31.b }, #255
+# CHECK-NEXT: 1 2 0.17 fabd z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fabd z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fabd z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fabs z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 fabs z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 fabs z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 facge p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 facge p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 facge p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 facge p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 facge p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 facge p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 facgt p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 facgt p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 facgt p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 facgt p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 facgt p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 facgt p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 0.17 fadd z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 2 0.17 fadd z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fadd z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fadd z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 2 0.17 fadd z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fadd z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fadd z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 2 0.17 fadd z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fadd z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fadd z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.17 fadd z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.17 fadd z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 4 0.33 fadda d0, p7, d0, z31.d
+# CHECK-NEXT: 1 10 10.00 fadda h0, p7, h0, z31.h
+# CHECK-NEXT: 1 6 6.00 fadda s0, p7, s0, z31.s
+# CHECK-NEXT: 1 2 0.17 faddp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 faddp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 faddp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.33 faddv d0, p7, z31.d
+# CHECK-NEXT: 1 8 0.67 faddv h0, p7, z31.h
+# CHECK-NEXT: 1 6 0.50 faddv s0, p7, z31.s
+# CHECK-NEXT: 1 3 0.17 fcadd z0.d, p0/m, z0.d, z0.d, #90
+# CHECK-NEXT: 1 3 0.17 fcadd z0.h, p0/m, z0.h, z0.h, #90
+# CHECK-NEXT: 1 3 0.17 fcadd z0.s, p0/m, z0.s, z0.s, #90
+# CHECK-NEXT: 1 3 0.17 fcadd z31.d, p7/m, z31.d, z31.d, #270
+# CHECK-NEXT: 1 3 0.17 fcadd z31.h, p7/m, z31.h, z31.h, #270
+# CHECK-NEXT: 1 3 0.17 fcadd z31.s, p7/m, z31.s, z31.s, #270
+# CHECK-NEXT: 1 2 1.00 fcmeq p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmeq p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 fcmeq p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmeq p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 fcmeq p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmeq p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 5 0.17 fcmla z0.d, p0/m, z0.d, z0.d, #0
+# CHECK-NEXT: 1 5 0.17 fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: 1 5 0.17 fcmla z0.h, p0/m, z0.h, z0.h, #0
+# CHECK-NEXT: 1 5 0.17 fcmla z0.h, p0/m, z1.h, z2.h, #90
+# CHECK-NEXT: 1 5 0.17 fcmla z0.h, z0.h, z0.h[0], #0
+# CHECK-NEXT: 1 5 0.17 fcmla z0.s, p0/m, z0.s, z0.s, #0
+# CHECK-NEXT: 1 5 0.17 fcmla z0.s, p0/m, z1.s, z2.s, #90
+# CHECK-NEXT: 1 5 0.17 fcmla z21.s, z10.s, z5.s[1], #90
+# CHECK-NEXT: 1 5 0.17 fcmla z23.s, z13.s, z8.s[0], #270
+# CHECK-NEXT: 1 5 0.17 fcmla z29.d, p7/m, z30.d, z31.d, #180
+# CHECK-NEXT: 1 5 0.17 fcmla z29.h, p7/m, z30.h, z31.h, #180
+# CHECK-NEXT: 1 5 0.17 fcmla z29.s, p7/m, z30.s, z31.s, #180
+# CHECK-NEXT: 1 5 0.17 fcmla z31.d, p7/m, z31.d, z31.d, #270
+# CHECK-NEXT: 1 5 0.17 fcmla z31.h, p7/m, z31.h, z31.h, #270
+# CHECK-NEXT: 1 5 0.17 fcmla z31.h, z31.h, z7.h[3], #270
+# CHECK-NEXT: 1 5 0.17 fcmla z31.s, p7/m, z31.s, z31.s, #270
+# CHECK-NEXT: 1 2 1.00 fcmle p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmle p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmle p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmlt p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmlt p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmlt p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmne p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmne p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 fcmne p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmne p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 fcmne p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 fcmne p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 fcmuo p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 fcmuo p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 fcmuo p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 3 0.25 fcvt z0.d, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 fcvt z0.d, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 fcvt z0.h, p0/m, z0.d
+# CHECK-NEXT: 1 4 0.25 fcvt z0.h, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 fcvt z0.s, p0/m, z0.d
+# CHECK-NEXT: 1 4 0.25 fcvt z0.s, p0/m, z0.h
+# CHECK-NEXT: 1 4 0.25 fcvtlt z0.s, p0/m, z1.h
+# CHECK-NEXT: 1 3 0.25 fcvtlt z30.d, p7/m, z31.s
+# CHECK-NEXT: 1 4 0.25 fcvtnt z0.h, p0/m, z1.s
+# CHECK-NEXT: 1 3 0.25 fcvtnt z30.s, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 fcvtx z0.s, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 fcvtx z30.s, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 fcvtxnt z0.s, p0/m, z1.d
+# CHECK-NEXT: 1 3 0.25 fcvtxnt z30.s, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 fcvtzs z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 fcvtzs z0.d, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 fcvtzs z0.d, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 fcvtzs z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 fcvtzs z0.s, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 fcvtzs z0.s, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 fcvtzs z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 fcvtzu z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 fcvtzu z0.d, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 fcvtzu z0.d, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 fcvtzu z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 fcvtzu z0.s, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 fcvtzu z0.s, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 fcvtzu z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 13 2.00 fdiv z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 8.00 fdiv z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 11 4.00 fdiv z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 13 2.00 fdivr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 8.00 fdivr z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 11 4.00 fdivr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 3 1.00 fexpa z0.d, z31.d
+# CHECK-NEXT: 1 3 1.00 fexpa z0.h, z31.h
+# CHECK-NEXT: 1 3 1.00 fexpa z0.s, z31.s
+# CHECK-NEXT: 1 3 0.25 flogb z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 flogb z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 flogb z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 4 0.17 fmad z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fmad z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fmad z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fmax z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.17 fmax z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fmax z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.17 fmax z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fmax z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.17 fmax z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fmax z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.17 fmax z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.17 fmax z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.17 fmaxnm z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.17 fmaxnm z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fmaxnm z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.17 fmaxnm z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fmaxnm z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.17 fmaxnm z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fmaxnm z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.17 fmaxnm z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.17 fmaxnm z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.17 fmaxnmp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 fmaxnmp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 fmaxnmp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.33 fmaxnmv d0, p7, z31.d
+# CHECK-NEXT: 1 8 0.67 fmaxnmv h0, p7, z31.h
+# CHECK-NEXT: 1 6 0.50 fmaxnmv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 fmaxp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 fmaxp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 fmaxp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.33 fmaxv d0, p7, z31.d
+# CHECK-NEXT: 1 8 0.67 fmaxv h0, p7, z31.h
+# CHECK-NEXT: 1 6 0.50 fmaxv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 fmin z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.17 fmin z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fmin z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.17 fmin z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fmin z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.17 fmin z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fmin z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.17 fmin z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.17 fmin z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.17 fminnm z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.17 fminnm z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fminnm z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.17 fminnm z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fminnm z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.17 fminnm z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fminnm z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.17 fminnm z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.17 fminnm z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.17 fminnmp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 fminnmp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 fminnmp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.33 fminnmv d0, p7, z31.d
+# CHECK-NEXT: 1 8 0.67 fminnmv h0, p7, z31.h
+# CHECK-NEXT: 1 6 0.50 fminnmv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 fminp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 fminp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 fminp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.33 fminv d0, p7, z31.d
+# CHECK-NEXT: 1 8 0.67 fminv h0, p7, z31.h
+# CHECK-NEXT: 1 6 0.50 fminv s0, p7, z31.s
+# CHECK-NEXT: 1 4 0.17 fmla z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fmla z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: 1 4 0.17 fmla z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fmla z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.17 fmla z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 fmla z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 5 0.17 fmlalb z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: 1 5 0.17 fmlalb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 5 0.17 fmlalb z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: 1 5 0.17 fmlalt z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: 1 5 0.17 fmlalt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 5 0.17 fmlalt z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.17 fmls z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fmls z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: 1 4 0.17 fmls z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fmls z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.17 fmls z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 fmls z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 5 0.17 fmlslb z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: 1 5 0.17 fmlslb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 5 0.17 fmlslb z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: 1 5 0.17 fmlslt z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: 1 5 0.17 fmlslt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 5 0.17 fmlslt z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: 1 2 0.17 fmov z0.d, #-10.00000000
+# CHECK-NEXT: 1 2 0.17 fmov z0.d, #0.12500000
+# CHECK-NEXT: 1 2 0.17 fmov z0.d, p0/m, #-10.00000000
+# CHECK-NEXT: 1 2 0.17 fmov z0.d, p0/m, #0.12500000
+# CHECK-NEXT: 1 2 0.17 fmov z0.h, #-0.12500000
+# CHECK-NEXT: 1 2 0.17 fmov z0.h, p0/m, #-0.12500000
+# CHECK-NEXT: 1 2 0.17 fmov z0.s, #-0.12500000
+# CHECK-NEXT: 1 2 0.17 fmov z0.s, p0/m, #-0.12500000
+# CHECK-NEXT: 1 4 0.17 fmsb z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fmsb z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fmsb z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.17 fmul z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 3 0.17 fmul z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 3 0.17 fmul z0.d, z0.d, z0.d[0]
+# CHECK-NEXT: 1 3 0.17 fmul z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 3 0.17 fmul z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 3 0.17 fmul z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 3 0.17 fmul z0.h, z0.h, z0.h[0]
+# CHECK-NEXT: 1 3 0.17 fmul z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.17 fmul z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 3 0.17 fmul z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 3 0.17 fmul z0.s, z0.s, z0.s[0]
+# CHECK-NEXT: 1 3 0.17 fmul z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.17 fmul z31.d, p7/m, z31.d, #2.0
+# CHECK-NEXT: 1 3 0.17 fmul z31.d, z31.d, z15.d[1]
+# CHECK-NEXT: 1 3 0.17 fmul z31.h, p7/m, z31.h, #2.0
+# CHECK-NEXT: 1 3 0.17 fmul z31.h, z31.h, z7.h[7]
+# CHECK-NEXT: 1 3 0.17 fmul z31.s, p7/m, z31.s, #2.0
+# CHECK-NEXT: 1 3 0.17 fmul z31.s, z31.s, z7.s[3]
+# CHECK-NEXT: 1 3 0.17 fmulx z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 3 0.17 fmulx z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 3 0.17 fmulx z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fneg z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 fneg z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 fneg z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 4 0.17 fnmad z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fnmad z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fnmad z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 fnmla z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fnmla z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fnmla z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 fnmls z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fnmls z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fnmls z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 fnmsb z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 fnmsb z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 fnmsb z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.25 frecpe z0.d, z31.d
+# CHECK-NEXT: 1 6 0.25 frecpe z0.h, z31.h
+# CHECK-NEXT: 1 4 0.25 frecpe z0.s, z31.s
+# CHECK-NEXT: 1 4 0.17 frecps z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 frecps z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 frecps z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.25 frecpx z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 0.25 frecpx z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 0.25 frecpx z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frinta z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 frinta z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 frinta z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frinti z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 frinti z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 frinti z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frintm z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 frintm z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 frintm z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frintn z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 frintn z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 frintn z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frintp z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 frintp z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 frintp z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frintx z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 frintx z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 frintx z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frintz z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 0.25 frintz z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 0.25 frintz z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 0.25 frsqrte z0.d, z31.d
+# CHECK-NEXT: 1 6 0.25 frsqrte z0.h, z31.h
+# CHECK-NEXT: 1 4 0.25 frsqrte z0.s, z31.s
+# CHECK-NEXT: 1 4 0.17 frsqrts z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 frsqrts z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 frsqrts z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.17 fscale z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 3 0.17 fscale z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 3 0.17 fscale z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 13 2.00 fsqrt z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 12 8.00 fsqrt z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 11 4.00 fsqrt z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 fsub z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 2 0.17 fsub z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fsub z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fsub z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 2 0.17 fsub z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fsub z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fsub z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 2 0.17 fsub z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fsub z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fsub z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.17 fsub z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.17 fsub z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.17 fsubr z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 2 0.17 fsubr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 fsubr z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 2 0.17 fsubr z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 fsubr z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 2 0.17 fsubr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 fsubr z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.17 fsubr z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.17 fsubr z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 4 0.17 ftmad z0.d, z0.d, z31.d, #7
+# CHECK-NEXT: 1 4 0.17 ftmad z0.h, z0.h, z31.h, #7
+# CHECK-NEXT: 1 4 0.17 ftmad z0.s, z0.s, z31.s, #7
+# CHECK-NEXT: 1 3 0.17 ftsmul z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 3 0.17 ftsmul z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.17 ftsmul z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.17 ftssel z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 3 0.17 ftssel z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.17 ftssel z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 histcnt z0.s, p0/z, z1.s, z2.s
+# CHECK-NEXT: 1 2 0.17 histcnt z29.d, p7/z, z30.d, z31.d
+# CHECK-NEXT: 1 2 0.17 histseg z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 1 0.13 incb x0
+# CHECK-NEXT: 1 1 0.13 incb x0, #14
+# CHECK-NEXT: 1 1 0.13 incb x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 incb x0, pow2
+# CHECK-NEXT: 1 1 0.13 incb x0, vl1
+# CHECK-NEXT: 1 1 0.13 incd x0
+# CHECK-NEXT: 1 1 0.13 incd x0, #14
+# CHECK-NEXT: 1 1 0.13 incd x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 incd x0, pow2
+# CHECK-NEXT: 1 1 0.13 incd x0, vl1
+# CHECK-NEXT: 1 2 0.17 incd z0.d
+# CHECK-NEXT: 1 2 0.17 incd z0.d, all, mul #16
+# CHECK-NEXT: 1 1 0.13 inch x0
+# CHECK-NEXT: 1 1 0.13 inch x0, #14
+# CHECK-NEXT: 1 1 0.13 inch x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 inch x0, pow2
+# CHECK-NEXT: 1 1 0.13 inch x0, vl1
+# CHECK-NEXT: 1 2 0.17 inch z0.h
+# CHECK-NEXT: 1 2 0.17 inch z0.h, all, mul #16
+# CHECK-NEXT: 1 7 1.00 incp x0, p0.b
+# CHECK-NEXT: 1 7 1.00 incp x0, p0.d
+# CHECK-NEXT: 1 7 1.00 incp x0, p0.h
+# CHECK-NEXT: 1 7 1.00 incp x0, p0.s
+# CHECK-NEXT: 1 7 1.00 incp xzr, p15.b
+# CHECK-NEXT: 1 7 1.00 incp xzr, p15.d
+# CHECK-NEXT: 1 7 1.00 incp xzr, p15.h
+# CHECK-NEXT: 1 7 1.00 incp xzr, p15.s
+# CHECK-NEXT: 1 7 1.00 incp z31.d, p15.d
+# CHECK-NEXT: 1 7 1.00 incp z31.h, p15.h
+# CHECK-NEXT: 1 7 1.00 incp z31.s, p15.s
+# CHECK-NEXT: 1 1 0.13 incw x0
+# CHECK-NEXT: 1 1 0.13 incw x0, #14
+# CHECK-NEXT: 1 1 0.13 incw x0, all, mul #16
+# CHECK-NEXT: 1 1 0.13 incw x0, pow2
+# CHECK-NEXT: 1 1 0.13 incw x0, vl1
+# CHECK-NEXT: 1 2 0.17 incw z0.s
+# CHECK-NEXT: 1 2 0.17 incw z0.s, all, mul #16
+# CHECK-NEXT: 1 4 0.25 index z0.b, #0, #0
+# CHECK-NEXT: 1 4 0.25 index z0.d, #0, #0
+# CHECK-NEXT: 1 4 0.25 index z0.h, #0, #0
+# CHECK-NEXT: 1 7 1.00 index z0.h, w0, w0
+# CHECK-NEXT: 1 4 0.25 index z0.s, #0, #0
+# CHECK-NEXT: 1 7 1.00 index z21.b, w10, w21
+# CHECK-NEXT: 1 7 1.00 index z21.d, x10, x21
+# CHECK-NEXT: 1 7 1.00 index z21.s, w10, w21
+# CHECK-NEXT: 1 7 1.00 index z23.b, #13, w8
+# CHECK-NEXT: 1 7 1.00 index z23.b, w13, #8
+# CHECK-NEXT: 1 7 1.00 index z23.d, #13, x8
+# CHECK-NEXT: 1 7 1.00 index z23.d, x13, #8
+# CHECK-NEXT: 1 7 1.00 index z23.h, #13, w8
+# CHECK-NEXT: 1 7 1.00 index z23.h, w13, #8
+# CHECK-NEXT: 1 7 1.00 index z23.s, #13, w8
+# CHECK-NEXT: 1 7 1.00 index z23.s, w13, #8
+# CHECK-NEXT: 1 4 0.25 index z31.b, #-1, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.b, #-1, wzr
+# CHECK-NEXT: 1 7 1.00 index z31.b, wzr, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.b, wzr, wzr
+# CHECK-NEXT: 1 4 0.25 index z31.d, #-1, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.d, #-1, xzr
+# CHECK-NEXT: 1 7 1.00 index z31.d, xzr, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.d, xzr, xzr
+# CHECK-NEXT: 1 4 0.25 index z31.h, #-1, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.h, #-1, wzr
+# CHECK-NEXT: 1 7 1.00 index z31.h, wzr, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.h, wzr, wzr
+# CHECK-NEXT: 1 4 0.25 index z31.s, #-1, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.s, #-1, wzr
+# CHECK-NEXT: 1 7 1.00 index z31.s, wzr, #-1
+# CHECK-NEXT: 1 7 1.00 index z31.s, wzr, wzr
+# CHECK-NEXT: 1 5 1.00 insr z0.b, w0
+# CHECK-NEXT: 1 5 1.00 insr z0.d, x0
+# CHECK-NEXT: 1 5 1.00 insr z0.h, w0
+# CHECK-NEXT: 1 5 1.00 insr z0.s, w0
+# CHECK-NEXT: 1 2 0.17 insr z31.b, b31
+# CHECK-NEXT: 1 5 1.00 insr z31.b, wzr
+# CHECK-NEXT: 1 2 0.17 insr z31.d, d31
+# CHECK-NEXT: 1 5 1.00 insr z31.d, xzr
+# CHECK-NEXT: 1 2 0.17 insr z31.h, h31
+# CHECK-NEXT: 1 5 1.00 insr z31.h, wzr
+# CHECK-NEXT: 1 2 0.17 insr z31.s, s31
+# CHECK-NEXT: 1 5 1.00 insr z31.s, wzr
+# CHECK-NEXT: 1 3 1.00 lasta b0, p7, z31.b
+# CHECK-NEXT: 1 3 1.00 lasta d0, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 lasta h0, p7, z31.h
+# CHECK-NEXT: 1 3 1.00 lasta s0, p7, z31.s
+# CHECK-NEXT: 1 5 1.00 lasta w0, p7, z31.b
+# CHECK-NEXT: 1 5 1.00 lasta w0, p7, z31.h
+# CHECK-NEXT: 1 5 1.00 lasta w0, p7, z31.s
+# CHECK-NEXT: 1 5 1.00 lasta x0, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 lastb b0, p7, z31.b
+# CHECK-NEXT: 1 3 1.00 lastb d0, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 lastb h0, p7, z31.h
+# CHECK-NEXT: 1 3 1.00 lastb s0, p7, z31.s
+# CHECK-NEXT: 1 5 1.00 lastb w0, p7, z31.b
+# CHECK-NEXT: 1 5 1.00 lastb w0, p7, z31.h
+# CHECK-NEXT: 1 5 1.00 lastb w0, p7, z31.s
+# CHECK-NEXT: 1 5 1.00 lastb x0, p7, z31.d
+# CHECK-NEXT: 1 6 0.25 * ld1b { z0.b }, p0/z, [sp, x0]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z21.b }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z21.s }, p5/z, [x10, x21]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z23.d }, p3/z, [x13, x8]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z31.b }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1b { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 1 6 0.25 * ld1b { z5.h }, p3/z, [x17, x16]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: 1 6 0.25 * ld1d { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.25 * ld1d { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1d { z23.d }, p3/z, [sp, x8, lsl #3]
+# CHECK-NEXT: 1 6 0.25 * ld1d { z23.d }, p3/z, [x13, x8, lsl #3]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+# CHECK-NEXT: 1 6 0.25 * ld1d { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * ld1d { z31.d }, p7/z, [z31.d, #248]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z21.s }, p5/z, [x10, x21, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z23.d }, p3/z, [x13, x8, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 1 9 0.50 * ld1h { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z5.h }, p3/z, [sp, x16, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1h { z5.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z31.b }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z31.d }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z31.h }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.25 * ld1rb { z31.s }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.25 * ld1rd { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rd { z31.d }, p7/z, [sp, #504]
+# CHECK-NEXT: 1 6 0.25 * ld1rh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rh { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rh { z31.d }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.25 * ld1rh { z31.h }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.25 * ld1rh { z31.s }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.25 * ld1rqb { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rqb { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rqb { z21.b }, p5/z, [x10, #112]
+# CHECK-NEXT: 1 6 0.25 * ld1rqb { z23.b }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.25 * ld1rqb { z31.b }, p7/z, [sp, #-16]
+# CHECK-NEXT: 1 6 0.25 * ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 6 0.25 * ld1rqd { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rqd { z23.d }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.25 * ld1rqd { z23.d }, p3/z, [x13, #112]
+# CHECK-NEXT: 1 6 0.25 * ld1rqd { z31.d }, p7/z, [sp, #-16]
+# CHECK-NEXT: 1 6 0.25 * ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1rqh { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rqh { z23.h }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.25 * ld1rqh { z23.h }, p3/z, [x13, #112]
+# CHECK-NEXT: 1 6 0.25 * ld1rqh { z31.h }, p7/z, [sp, #-16]
+# CHECK-NEXT: 1 6 0.25 * ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 6 0.25 * ld1rqw { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rqw { z23.s }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.25 * ld1rqw { z23.s }, p3/z, [x13, #112]
+# CHECK-NEXT: 1 6 0.25 * ld1rqw { z31.s }, p7/z, [sp, #-16]
+# CHECK-NEXT: 1 6 0.25 * ld1rsb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rsb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rsb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rsb { z31.d }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.25 * ld1rsb { z31.h }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.25 * ld1rsb { z31.s }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.25 * ld1rsh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rsh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rsh { z31.d }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.25 * ld1rsh { z31.s }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.25 * ld1rsw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rsw { z31.d }, p7/z, [sp, #252]
+# CHECK-NEXT: 1 6 0.25 * ld1rw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rw { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ld1rw { z31.d }, p7/z, [sp, #252]
+# CHECK-NEXT: 1 6 0.25 * ld1rw { z31.s }, p7/z, [sp, #252]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z0.h }, p0/z, [sp, x0]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z21.s }, p5/z, [x10, x21]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z23.d }, p3/z, [x13, x8]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sb { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 1 6 0.25 * ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 1 9 0.50 * ld1sh { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 1 6 0.25 * ld1sw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.25 * ld1sw { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]
+# CHECK-NEXT: 1 6 0.25 * ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 1 6 0.25 * ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * ld1sw { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z21.s }, p5/z, [sp, x21, lsl #2]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z21.s }, p5/z, [x10, x21, lsl #2]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z23.d }, p3/z, [x13, x8, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 1 6 0.25 * ld1w { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+# CHECK-NEXT: 1 9 0.50 * ld1w { z31.s }, p7/z, [z31.s, #124]
+# CHECK-NEXT: 1 9 0.50 * ld2b { z0.b, z1.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 8 0.50 * ld2b { z0.b, z1.b }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.50 * ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 1 8 0.50 * ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld2b { z5.b, z6.b }, p3/z, [x17, x16]
+# CHECK-NEXT: 1 9 0.50 * ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 8 0.50 * ld2d { z0.d, z1.d }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.50 * ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 1 8 0.50 * ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: 1 9 0.50 * ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 8 0.50 * ld2h { z0.h, z1.h }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.50 * ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 1 8 0.50 * ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 8 0.50 * ld2w { z0.s, z1.s }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.50 * ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 1 8 0.50 * ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: 1 9 0.75 * ld3b { z0.b - z2.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 8 0.75 * ld3b { z0.b - z2.b }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.75 * ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 1 8 0.75 * ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 9 0.75 * ld3b { z5.b - z7.b }, p3/z, [x17, x16]
+# CHECK-NEXT: 1 9 0.75 * ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 8 0.75 * ld3d { z0.d - z2.d }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.75 * ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 1 8 0.75 * ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 9 0.75 * ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: 1 9 0.75 * ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 8 0.75 * ld3h { z0.h - z2.h }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.75 * ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 1 8 0.75 * ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 9 0.75 * ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 9 0.75 * ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 8 0.75 * ld3w { z0.s - z2.s }, p0/z, [x0]
+# CHECK-NEXT: 1 8 0.75 * ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 1 8 0.75 * ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 9 0.75 * ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: 1 11 1.33 * ld4b { z0.b - z3.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 10 1.33 * ld4b { z0.b - z3.b }, p0/z, [x0]
+# CHECK-NEXT: 1 10 1.33 * ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 1 10 1.33 * ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 11 1.33 * ld4b { z5.b - z8.b }, p3/z, [x17, x16]
+# CHECK-NEXT: 1 11 1.33 * ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 10 1.33 * ld4d { z0.d - z3.d }, p0/z, [x0]
+# CHECK-NEXT: 1 10 1.33 * ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 1 10 1.33 * ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 11 1.33 * ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: 1 11 1.33 * ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 10 1.33 * ld4h { z0.h - z3.h }, p0/z, [x0]
+# CHECK-NEXT: 1 10 1.33 * ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 1 10 1.33 * ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 11 1.33 * ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 11 1.33 * ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 10 1.33 * ld4w { z0.s - z3.s }, p0/z, [x0]
+# CHECK-NEXT: 1 10 1.33 * ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 1 10 1.33 * ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 11 1.33 * ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z0.d }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z0.s }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z31.b }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z31.h }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1b { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1d { z31.d }, p7/z, [z31.d, #248]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.s }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.h }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1h { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z0.d }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z0.s }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z31.h }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sb { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sh { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1sw { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 1 9 0.50 * U ldff1w { z31.s }, p7/z, [z31.s, #124]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z21.b }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1d { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1w { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1w { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1w { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * U ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldnt1b { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.25 * ldnt1b { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1b { z0.d }, p0/z, [z1.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1b { z0.s }, p0/z, [z1.s]
+# CHECK-NEXT: 1 6 0.25 * ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ldnt1b { z31.d }, p7/z, [z31.d, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1b { z31.d }, p7/z, [z31.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1b { z31.s }, p7/z, [z31.s, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1b { z31.s }, p7/z, [z31.s]
+# CHECK-NEXT: 1 6 0.25 * ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 6 0.25 * ldnt1d { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.25 * ldnt1d { z0.d }, p0/z, [z1.d]
+# CHECK-NEXT: 1 6 0.25 * ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldnt1d { z31.d }, p7/z, [z31.d, x0]
+# CHECK-NEXT: 1 6 0.25 * ldnt1d { z31.d }, p7/z, [z31.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1h { z0.d }, p0/z, [z1.d]
+# CHECK-NEXT: 1 6 0.25 * ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 6 0.25 * ldnt1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1h { z0.s }, p0/z, [z1.s]
+# CHECK-NEXT: 1 6 0.25 * ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ldnt1h { z31.d }, p7/z, [z31.d, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1h { z31.d }, p7/z, [z31.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1h { z31.s }, p7/z, [z31.s, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1h { z31.s }, p7/z, [z31.s]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sb { z0.d }, p0/z, [z1.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sb { z0.s }, p0/z, [z1.s]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sb { z31.d }, p7/z, [z31.d, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sb { z31.d }, p7/z, [z31.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sb { z31.s }, p7/z, [z31.s, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sb { z31.s }, p7/z, [z31.s]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sh { z0.d }, p0/z, [z1.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sh { z0.s }, p0/z, [z1.s]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sh { z31.d }, p7/z, [z31.d, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sh { z31.d }, p7/z, [z31.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sh { z31.s }, p7/z, [z31.s, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sh { z31.s }, p7/z, [z31.s]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sw { z0.d }, p0/z, [z1.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sw { z31.d }, p7/z, [z31.d, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1sw { z31.d }, p7/z, [z31.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1w { z0.d }, p0/z, [z1.d]
+# CHECK-NEXT: 1 6 0.25 * ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 6 0.25 * ldnt1w { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1w { z0.s }, p0/z, [z1.s]
+# CHECK-NEXT: 1 6 0.25 * ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 9 0.50 * ldnt1w { z31.d }, p7/z, [z31.d, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1w { z31.d }, p7/z, [z31.d]
+# CHECK-NEXT: 1 9 0.50 * ldnt1w { z31.s }, p7/z, [z31.s, x0]
+# CHECK-NEXT: 1 9 0.50 * ldnt1w { z31.s }, p7/z, [z31.s]
+# CHECK-NEXT: 1 6 0.50 * ldr p0, [x0]
+# CHECK-NEXT: 1 6 0.50 * ldr p5, [x10, #255, mul vl]
+# CHECK-NEXT: 1 6 0.50 * ldr p7, [x13, #-256, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldr z0, [x0]
+# CHECK-NEXT: 1 6 0.25 * ldr z23, [x13, #255, mul vl]
+# CHECK-NEXT: 1 6 0.25 * ldr z31, [sp, #-256, mul vl]
+# CHECK-NEXT: 1 2 0.17 lsl z0.b, p0/m, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 lsl z0.b, p0/m, z0.b, z1.d
+# CHECK-NEXT: 1 2 0.17 lsl z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.b, z1.b, z2.d
+# CHECK-NEXT: 1 2 0.17 lsl z0.d, p0/m, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 lsl z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.h, p0/m, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 lsl z0.h, p0/m, z0.h, z1.d
+# CHECK-NEXT: 1 2 0.17 lsl z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.h, z1.h, z2.d
+# CHECK-NEXT: 1 2 0.17 lsl z0.s, p0/m, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 lsl z0.s, p0/m, z0.s, z1.d
+# CHECK-NEXT: 1 2 0.17 lsl z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 lsl z0.s, z1.s, z2.d
+# CHECK-NEXT: 1 2 0.17 lsl z31.b, p0/m, z31.b, #7
+# CHECK-NEXT: 1 2 0.17 lsl z31.b, z31.b, #7
+# CHECK-NEXT: 1 2 0.17 lsl z31.d, p0/m, z31.d, #63
+# CHECK-NEXT: 1 2 0.17 lsl z31.d, z31.d, #63
+# CHECK-NEXT: 1 2 0.17 lsl z31.h, p0/m, z31.h, #15
+# CHECK-NEXT: 1 2 0.17 lsl z31.h, z31.h, #15
+# CHECK-NEXT: 1 2 0.17 lsl z31.s, p0/m, z31.s, #31
+# CHECK-NEXT: 1 2 0.17 lsl z31.s, z31.s, #31
+# CHECK-NEXT: 1 2 0.17 lslr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 lslr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 lslr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 lslr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 lsr z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 lsr z0.b, p0/m, z0.b, z1.d
+# CHECK-NEXT: 1 2 0.17 lsr z0.b, z0.b, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.b, z1.b, z2.d
+# CHECK-NEXT: 1 2 0.17 lsr z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 lsr z0.d, z0.d, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 lsr z0.h, p0/m, z0.h, z1.d
+# CHECK-NEXT: 1 2 0.17 lsr z0.h, z0.h, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.h, z1.h, z2.d
+# CHECK-NEXT: 1 2 0.17 lsr z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 lsr z0.s, p0/m, z0.s, z1.d
+# CHECK-NEXT: 1 2 0.17 lsr z0.s, z0.s, #1
+# CHECK-NEXT: 1 2 0.17 lsr z0.s, z1.s, z2.d
+# CHECK-NEXT: 1 2 0.17 lsr z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 2 0.17 lsr z31.b, z31.b, #8
+# CHECK-NEXT: 1 2 0.17 lsr z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 2 0.17 lsr z31.d, z31.d, #64
+# CHECK-NEXT: 1 2 0.17 lsr z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 2 0.17 lsr z31.h, z31.h, #16
+# CHECK-NEXT: 1 2 0.17 lsr z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 lsr z31.s, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 lsrr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 lsrr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 lsrr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 lsrr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 4 0.25 mad z0.b, p7/m, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 mad z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.25 mad z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 mad z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 2 1.00 match p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 match p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 match p15.b, p7/z, z30.b, z31.b
+# CHECK-NEXT: 1 2 1.00 match p15.h, p7/z, z30.h, z31.h
+# CHECK-NEXT: 1 4 0.25 mla z0.b, p7/m, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 mla z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.25 mla z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: 1 4 0.25 mla z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 mla z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 mla z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 mla z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 4 0.25 mls z0.b, p7/m, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 mls z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.25 mls z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: 1 4 0.25 mls z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 mls z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 mls z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 mls z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 2 1.00 mov p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 mov p0.b, p0/m, p0.b
+# CHECK-NEXT: 1 2 1.00 mov p0.b, p0/z, p0.b
+# CHECK-NEXT: 1 2 1.00 mov p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 mov p15.b, p15/m, p15.b
+# CHECK-NEXT: 1 2 1.00 mov p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 0.17 mov z0.b, #127
+# CHECK-NEXT: 1 2 0.17 mov z0.b, b0
+# CHECK-NEXT: 1 2 0.17 mov z0.b, p0/m, b0
+# CHECK-NEXT: 1 3 1.00 mov z0.b, p0/m, w0
+# CHECK-NEXT: 1 2 0.17 mov z0.b, p0/z, #127
+# CHECK-NEXT: 1 3 1.00 mov z0.b, w0
+# CHECK-NEXT: 1 2 0.17 mov z0.d, #0
+# CHECK-NEXT: 1 2 0.17 mov z0.d, #0xe0000000000003ff
+# CHECK-NEXT: 1 2 0.17 mov z0.d, #0xffffffffffff7fff
+# CHECK-NEXT: 1 2 0.17 mov z0.d, #32768
+# CHECK-NEXT: 1 2 0.17 mov z0.d, d0
+# CHECK-NEXT: 1 2 0.17 mov z0.d, p0/m, d0
+# CHECK-NEXT: 1 3 1.00 mov z0.d, p0/m, x0
+# CHECK-NEXT: 1 3 1.00 mov z0.d, x0
+# CHECK-NEXT: 1 2 0.17 mov z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 mov z0.h, #-256
+# CHECK-NEXT: 1 2 0.17 mov z0.h, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z0.h, #0
+# CHECK-NEXT: 1 2 0.17 mov z0.h, #32512
+# CHECK-NEXT: 1 2 0.17 mov z0.h, #32767
+# CHECK-NEXT: 1 2 0.17 mov z0.h, h0
+# CHECK-NEXT: 1 2 0.17 mov z0.h, p0/m, h0
+# CHECK-NEXT: 1 3 1.00 mov z0.h, p0/m, w0
+# CHECK-NEXT: 1 2 0.17 mov z0.h, p0/z, #32512
+# CHECK-NEXT: 1 3 1.00 mov z0.h, w0
+# CHECK-NEXT: 1 2 0.17 mov z0.q, q0
+# CHECK-NEXT: 1 2 0.17 mov z0.s, #0
+# CHECK-NEXT: 1 2 0.17 mov z0.s, #0xffff7fff
+# CHECK-NEXT: 1 2 0.17 mov z0.s, #32768
+# CHECK-NEXT: 1 2 0.17 mov z0.s, p0/m, s0
+# CHECK-NEXT: 1 3 1.00 mov z0.s, p0/m, w0
+# CHECK-NEXT: 1 2 0.17 mov z0.s, s0
+# CHECK-NEXT: 1 3 1.00 mov z0.s, w0
+# CHECK-NEXT: 1 2 0.17 mov z21.d, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.d, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.d, #127
+# CHECK-NEXT: 1 2 0.17 mov z21.d, #32512
+# CHECK-NEXT: 1 2 0.17 mov z21.d, p0/z, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.d, p0/z, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.d, p0/z, #127
+# CHECK-NEXT: 1 2 0.17 mov z21.d, p0/z, #32512
+# CHECK-NEXT: 1 2 0.17 mov z21.d, p15/m, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.d, p15/m, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.h, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.h, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.h, #127
+# CHECK-NEXT: 1 2 0.17 mov z21.h, #32512
+# CHECK-NEXT: 1 2 0.17 mov z21.h, p0/z, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.h, p0/z, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.h, p0/z, #127
+# CHECK-NEXT: 1 2 0.17 mov z21.h, p0/z, #32512
+# CHECK-NEXT: 1 2 0.17 mov z21.h, p15/m, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.h, p15/m, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.s, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.s, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.s, #127
+# CHECK-NEXT: 1 2 0.17 mov z21.s, #32512
+# CHECK-NEXT: 1 2 0.17 mov z21.s, p0/z, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.s, p0/z, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z21.s, p0/z, #127
+# CHECK-NEXT: 1 2 0.17 mov z21.s, p0/z, #32512
+# CHECK-NEXT: 1 2 0.17 mov z21.s, p15/m, #-128
+# CHECK-NEXT: 1 2 0.17 mov z21.s, p15/m, #-32768
+# CHECK-NEXT: 1 2 0.17 mov z31.b, p15/m, z31.b
+# CHECK-NEXT: 1 2 0.17 mov z31.b, p7/m, b31
+# CHECK-NEXT: 1 2 0.17 movprfx z31, z6
+# CHECK-NEXT: 1 3 1.00 mov z31.b, p7/m, wsp
+# CHECK-NEXT: 1 3 1.00 mov z31.b, wsp
+# CHECK-NEXT: 1 2 0.17 mov z31.b, z31.b[63]
+# CHECK-NEXT: 1 2 0.17 mov z31.d, p15/m, z31.d
+# CHECK-NEXT: 1 2 0.17 mov z31.d, p7/m, d31
+# CHECK-NEXT: 1 2 0.17 movprfx z31.d, p7/z, z6.d
+# CHECK-NEXT: 1 3 1.00 mov z31.d, p7/m, sp
+# CHECK-NEXT: 1 3 1.00 mov z31.d, sp
+# CHECK-NEXT: 1 2 0.17 mov z31.d, z0.d
+# CHECK-NEXT: 1 2 0.17 mov z31.d, z31.d[7]
+# CHECK-NEXT: 1 2 0.17 mov z31.h, p15/m, z31.h
+# CHECK-NEXT: 1 2 0.17 mov z31.h, p7/m, h31
+# CHECK-NEXT: 1 3 1.00 mov z31.h, p7/m, wsp
+# CHECK-NEXT: 1 3 1.00 mov z31.h, wsp
+# CHECK-NEXT: 1 2 0.17 mov z31.h, z31.h[31]
+# CHECK-NEXT: 1 2 0.17 mov z31.s, p15/m, z31.s
+# CHECK-NEXT: 1 2 0.17 mov z31.s, p7/m, s31
+# CHECK-NEXT: 1 3 1.00 mov z31.s, p7/m, wsp
+# CHECK-NEXT: 1 3 1.00 mov z31.s, wsp
+# CHECK-NEXT: 1 2 0.17 mov z31.s, z31.s[15]
+# CHECK-NEXT: 1 2 0.17 mov z5.b, #-1
+# CHECK-NEXT: 1 2 0.17 mov z5.b, #-128
+# CHECK-NEXT: 1 2 0.17 mov z5.b, #127
+# CHECK-NEXT: 1 2 0.17 mov z5.b, p0/z, #-1
+# CHECK-NEXT: 1 2 0.17 mov z5.b, p0/z, #-128
+# CHECK-NEXT: 1 2 0.17 mov z5.b, p0/z, #127
+# CHECK-NEXT: 1 2 0.17 mov z5.b, p15/m, #-128
+# CHECK-NEXT: 1 2 0.17 mov z5.d, #-6
+# CHECK-NEXT: 1 2 0.17 mov z5.h, #-6
+# CHECK-NEXT: 1 2 0.17 mov z5.q, z17.q[3]
+# CHECK-NEXT: 1 2 0.17 mov z5.s, #-6
+# CHECK-NEXT: 1 2 1.00 movs p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 movs p0.b, p0/z, p0.b
+# CHECK-NEXT: 1 2 1.00 movs p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 movs p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 1 0.10 U mrs x3, ID_AA64ZFR0_EL1
+# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL1
+# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL12
+# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL2
+# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL3
+# CHECK-NEXT: 1 4 0.25 msb z0.b, p7/m, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 msb z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.25 msb z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 msb z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL1, x3
+# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL12, x3
+# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL2, x3
+# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL3, x3
+# CHECK-NEXT: 1 4 0.25 mul z0.b, p7/m, z0.b, z31.b
+# CHECK-NEXT: 1 4 0.25 mul z0.b, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 mul z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 4 0.25 mul z0.d, z1.d, z15.d[1]
+# CHECK-NEXT: 1 4 0.25 mul z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 4 0.25 mul z0.h, z1.h, z2.h
+# CHECK-NEXT: 1 4 0.25 mul z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 mul z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 4 0.25 mul z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 4 0.25 mul z29.s, z30.s, z31.s
+# CHECK-NEXT: 1 4 0.25 mul z31.b, z31.b, #-128
+# CHECK-NEXT: 1 4 0.25 mul z31.b, z31.b, #127
+# CHECK-NEXT: 1 4 0.25 mul z31.d, z31.d, #-128
+# CHECK-NEXT: 1 4 0.25 mul z31.d, z31.d, #127
+# CHECK-NEXT: 1 4 0.25 mul z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 4 0.25 mul z31.h, z31.h, #-128
+# CHECK-NEXT: 1 4 0.25 mul z31.h, z31.h, #127
+# CHECK-NEXT: 1 4 0.25 mul z31.s, z31.s, #-128
+# CHECK-NEXT: 1 4 0.25 mul z31.s, z31.s, #127
+# CHECK-NEXT: 1 2 1.00 nand p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 nand p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 nands p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 nands p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.17 nbsl z0.d, z0.d, z1.d, z2.d
+# CHECK-NEXT: 1 2 0.17 neg z0.b, p0/m, z0.b
+# CHECK-NEXT: 1 2 0.17 neg z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 neg z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 0.17 neg z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.17 neg z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 neg z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 neg z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 neg z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 nmatch p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 nmatch p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 nmatch p15.b, p7/z, z30.b, z31.b
+# CHECK-NEXT: 1 2 1.00 nmatch p15.h, p7/z, z30.h, z31.h
+# CHECK-NEXT: 1 2 1.00 nor p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 nor p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 nors p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 nors p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 not p0.b, p0/z, p0.b
+# CHECK-NEXT: 1 2 1.00 not p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 0.17 not z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 not z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 not z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 not z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 nots p0.b, p0/z, p0.b
+# CHECK-NEXT: 1 2 1.00 nots p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 1.00 orn p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 orn p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 orns p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 orns p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 orr p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 2 0.17 orr z0.d, z0.d, #0x6
+# CHECK-NEXT: 1 2 0.17 orr z0.d, z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.17 orr z0.s, z0.s, #0x6
+# CHECK-NEXT: 1 2 0.17 orr z0.s, z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.17 orr z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.17 orr z23.h, z23.h, #0x6
+# CHECK-NEXT: 1 2 0.17 orr z23.h, z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.17 orr z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 orr z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 orr z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 orr z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 orr z5.b, z5.b, #0x6
+# CHECK-NEXT: 1 2 0.17 orr z5.b, z5.b, #0xf9
+# CHECK-NEXT: 1 2 1.00 orrs p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 4 0.33 orv b0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 orv d0, p7, z31.d
+# CHECK-NEXT: 1 4 0.33 orv h0, p7, z31.h
+# CHECK-NEXT: 1 4 0.33 orv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.50 pfalse p15.b
+# CHECK-NEXT: 1 2 0.50 pfirst p0.b, p15, p0.b
+# CHECK-NEXT: 1 2 0.50 pfirst p15.b, p15, p15.b
+# CHECK-NEXT: 1 2 0.25 pmul z0.b, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.25 pmul z29.b, z30.b, z31.b
+# CHECK-NEXT: 1 2 0.25 pmullb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.25 pmullb z29.q, z30.d, z31.d
+# CHECK-NEXT: 1 2 0.25 pmullb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.25 pmullt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.25 pmullt z29.q, z30.d, z31.d
+# CHECK-NEXT: 1 2 0.25 pmullt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 pnext p0.b, p15, p0.b
+# CHECK-NEXT: 1 2 0.50 pnext p0.d, p15, p0.d
+# CHECK-NEXT: 1 2 0.50 pnext p0.h, p15, p0.h
+# CHECK-NEXT: 1 2 0.50 pnext p0.s, p15, p0.s
+# CHECK-NEXT: 1 2 0.50 pnext p15.b, p15, p15.b
+# CHECK-NEXT: 1 4 0.25 * * U prfb #14, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb #15, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb #6, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb #7, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb #7, p3, [z13.s, #31]
+# CHECK-NEXT: 1 4 0.25 * * U prfb #7, p3, [z13.s]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl1keep, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl1keep, p0, [x0, z0.d]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl1keep, p0, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl1strm, p0, [x0, #-32, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl1strm, p0, [x0, #31, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl3strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl3strm, p5, [x10, z21.d, sxtw]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl3strm, p5, [x10, z21.s, uxtw]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl3strm, p5, [z10.d, #31]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pldl3strm, p5, [z10.d]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pstl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pstl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pstl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pstl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pstl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfb pstl3strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #14, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #15, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #15, p7, [z31.d, #248]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #15, p7, [z31.d]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #15, p7, [z31.s, #248]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #15, p7, [z31.s]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #6, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd #7, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1keep, p0, [x0, z0.d, lsl #3]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1keep, p0, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1keep, p0, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1keep, p0, [x0, z0.s, sxtw #3]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1keep, p0, [x0, z0.s, uxtw #3]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1strm, p0, [x0, #-32, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1strm, p0, [x0, #31, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pldl3strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pstl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pstl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pstl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pstl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pstl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfd pstl3strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #14, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #15, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #15, p7, [z31.d, #62]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #15, p7, [z31.d]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #15, p7, [z31.s, #62]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #15, p7, [z31.s]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #6, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh #7, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl1keep, p0, [x0, z0.d, lsl #1]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl1strm, p0, [x0, #-32, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl1strm, p0, [x0, #31, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl3strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl3strm, p5, [x10, z21.d, sxtw #1]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl3strm, p5, [x10, z21.d, uxtw #1]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl3strm, p5, [x10, z21.s, sxtw #1]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pldl3strm, p5, [x10, z21.s, uxtw #1]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pstl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pstl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pstl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pstl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pstl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfh pstl3strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #14, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #15, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #15, p7, [z31.d, #124]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #15, p7, [z31.d]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #15, p7, [z31.s, #124]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #15, p7, [z31.s]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #6, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #7, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw #7, p3, [x13, z8.d, uxtw #2]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl1keep, p0, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl1keep, p0, [x0, z0.s, uxtw #2]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl1strm, p0, [x0, #-32, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl1strm, p0, [x0, #31, mul vl]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl3strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl3strm, p5, [x10, z21.d, lsl #2]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pldl3strm, p5, [x10, z21.s, sxtw #2]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pstl1keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pstl1strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pstl2keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pstl2strm, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pstl3keep, p0, [x0]
+# CHECK-NEXT: 1 4 0.25 * * U prfw pstl3strm, p0, [x0]
+# CHECK-NEXT: 1 1 0.50 ptest p15, p0.b
+# CHECK-NEXT: 1 1 0.50 ptest p15, p15.b
+# CHECK-NEXT: 1 2 0.50 ptrue p0.b, pow2
+# CHECK-NEXT: 1 2 0.50 ptrue p0.d, pow2
+# CHECK-NEXT: 1 2 0.50 ptrue p0.h, pow2
+# CHECK-NEXT: 1 2 0.50 ptrue p0.s, pow2
+# CHECK-NEXT: 1 2 0.50 ptrue p15.b
+# CHECK-NEXT: 1 2 0.50 ptrue p15.d
+# CHECK-NEXT: 1 2 0.50 ptrue p15.h
+# CHECK-NEXT: 1 2 0.50 ptrue p15.s
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #14
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #15
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #16
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #17
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #18
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #19
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #20
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #21
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #22
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #23
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #24
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #25
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #26
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #27
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, #28
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, mul3
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, mul4
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl1
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl128
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl16
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl2
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl256
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl3
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl32
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl4
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl5
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl6
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl64
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl7
+# CHECK-NEXT: 1 2 0.50 ptrue p7.s, vl8
+# CHECK-NEXT: 1 2 0.50 ptrues p0.b, pow2
+# CHECK-NEXT: 1 2 0.50 ptrues p0.d, pow2
+# CHECK-NEXT: 1 2 0.50 ptrues p0.h, pow2
+# CHECK-NEXT: 1 2 0.50 ptrues p0.s, pow2
+# CHECK-NEXT: 1 2 0.50 ptrues p15.b
+# CHECK-NEXT: 1 2 0.50 ptrues p15.d
+# CHECK-NEXT: 1 2 0.50 ptrues p15.h
+# CHECK-NEXT: 1 2 0.50 ptrues p15.s
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #14
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #15
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #16
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #17
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #18
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #19
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #20
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #21
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #22
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #23
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #24
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #25
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #26
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #27
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, #28
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, mul3
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, mul4
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl1
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl128
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl16
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl2
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl256
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl3
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl32
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl4
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl5
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl6
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl64
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl7
+# CHECK-NEXT: 1 2 0.50 ptrues p7.s, vl8
+# CHECK-NEXT: 1 2 0.50 punpkhi p0.h, p0.b
+# CHECK-NEXT: 1 2 0.50 punpkhi p15.h, p15.b
+# CHECK-NEXT: 1 2 0.50 punpklo p0.h, p0.b
+# CHECK-NEXT: 1 2 0.50 punpklo p15.h, p15.b
+# CHECK-NEXT: 1 2 0.17 raddhnb z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 raddhnb z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 raddhnb z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 raddhnt z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 raddhnt z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 raddhnt z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 rax1 z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 rbit z0.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 rbit z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 rbit z0.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 rbit z0.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 * U rdffr p0.b
+# CHECK-NEXT: 1 2 1.00 * U rdffr p0.b, p0/z
+# CHECK-NEXT: 1 2 1.00 * U rdffr p15.b
+# CHECK-NEXT: 1 2 1.00 * U rdffr p15.b, p15/z
+# CHECK-NEXT: 1 3 1.00 U rdffrs p0.b, p0/z
+# CHECK-NEXT: 1 3 1.00 U rdffrs p15.b, p15/z
+# CHECK-NEXT: 1 1 0.13 rdvl x0, #0
+# CHECK-NEXT: 1 1 0.13 rdvl x21, #-32
+# CHECK-NEXT: 1 1 0.13 rdvl x23, #31
+# CHECK-NEXT: 1 1 0.13 rdvl xzr, #-1
+# CHECK-NEXT: 1 2 0.50 rev p0.b, p1.b
+# CHECK-NEXT: 1 2 0.50 rev p0.d, p1.d
+# CHECK-NEXT: 1 2 0.50 rev p0.h, p1.h
+# CHECK-NEXT: 1 2 0.50 rev p0.s, p1.s
+# CHECK-NEXT: 1 2 0.17 rev z0.b, z31.b
+# CHECK-NEXT: 1 2 0.17 rev z0.d, z31.d
+# CHECK-NEXT: 1 2 0.17 rev z0.h, z31.h
+# CHECK-NEXT: 1 2 0.17 rev z0.s, z31.s
+# CHECK-NEXT: 1 2 0.17 revb z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 revb z0.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 revb z0.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 revh z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 revh z0.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 revw z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 4 0.17 rshrnb z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 rshrnb z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 rshrnb z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 rshrnb z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 rshrnb z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 rshrnb z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 rshrnt z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 rshrnt z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 rshrnt z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 rshrnt z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 rshrnt z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 rshrnt z31.s, z31.d, #32
+# CHECK-NEXT: 1 2 0.17 rsubhnb z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 rsubhnb z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 rsubhnb z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 rsubhnt z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 rsubhnt z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 rsubhnt z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 saba z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.17 saba z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 saba z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 saba z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 sabalb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 sabalb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.17 sabalb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 sabalt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 sabalt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.17 sabalt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 sabd z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 sabd z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 sabd z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 sabd z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 sabdlb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 sabdlb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 sabdlb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 sabdlt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 sabdlt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 sabdlt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 4 0.17 sadalp z0.h, p0/m, z1.b
+# CHECK-NEXT: 1 4 0.17 sadalp z29.s, p0/m, z30.h
+# CHECK-NEXT: 1 4 0.17 sadalp z30.d, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 saddlb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 saddlb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 saddlb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 saddlbt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 saddlbt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 2 0.17 saddlbt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 saddlt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 saddlt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 saddlt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 8 0.75 saddv d0, p7, z31.b
+# CHECK-NEXT: 1 6 0.50 saddv d0, p7, z31.h
+# CHECK-NEXT: 1 6 0.50 saddv d0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 saddwb z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 saddwb z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 saddwb z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 saddwt z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 saddwt z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 saddwt z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 sbclb z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 sbclb z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 sbclt z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 sbclt z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.25 scvtf z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 scvtf z0.d, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 scvtf z0.h, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 scvtf z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 scvtf z0.h, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 scvtf z0.s, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 scvtf z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 20 7.00 sdiv z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 sdiv z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 20 7.00 sdivr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 sdivr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 3 0.25 sdot z0.d, z1.h, z15.h[1]
+# CHECK-NEXT: 1 3 0.25 sdot z0.d, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.17 sdot z0.s, z1.b, z31.b
+# CHECK-NEXT: 1 3 0.17 sdot z0.s, z1.b, z7.b[3]
+# CHECK-NEXT: 1 2 1.00 sel p0.b, p1, p2.b, p3.b
+# CHECK-NEXT: 1 2 0.17 sel z23.b, p11, z13.b, z8.b
+# CHECK-NEXT: 1 2 0.17 sel z23.d, p11, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.17 sel z23.h, p11, z13.h, z8.h
+# CHECK-NEXT: 1 2 0.17 sel z23.s, p11, z13.s, z8.s
+# CHECK-NEXT: 1 2 1.00 * U setffr
+# CHECK-NEXT: 1 2 0.17 shadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 shadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 shadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 shadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 shrnb z0.b, z0.h, #1
+# CHECK-NEXT: 1 2 0.17 shrnb z0.h, z0.s, #1
+# CHECK-NEXT: 1 2 0.17 shrnb z0.s, z0.d, #1
+# CHECK-NEXT: 1 2 0.17 shrnb z31.b, z31.h, #8
+# CHECK-NEXT: 1 2 0.17 shrnb z31.h, z31.s, #16
+# CHECK-NEXT: 1 2 0.17 shrnb z31.s, z31.d, #32
+# CHECK-NEXT: 1 2 0.17 shrnt z0.b, z0.h, #1
+# CHECK-NEXT: 1 2 0.17 shrnt z0.h, z0.s, #1
+# CHECK-NEXT: 1 2 0.17 shrnt z0.s, z0.d, #1
+# CHECK-NEXT: 1 2 0.17 shrnt z31.b, z31.h, #8
+# CHECK-NEXT: 1 2 0.17 shrnt z31.h, z31.s, #16
+# CHECK-NEXT: 1 2 0.17 shrnt z31.s, z31.d, #32
+# CHECK-NEXT: 1 2 0.17 shsub z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 shsub z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 shsub z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 shsub z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 shsubr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 shsubr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 shsubr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 shsubr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 sli z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 sli z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 sli z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 sli z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 sli z31.b, z31.b, #7
+# CHECK-NEXT: 1 2 0.17 sli z31.d, z31.d, #63
+# CHECK-NEXT: 1 2 0.17 sli z31.h, z31.h, #15
+# CHECK-NEXT: 1 2 0.17 sli z31.s, z31.s, #31
+# CHECK-NEXT: 1 4 1.00 sm4e z0.s, z0.s, z31.s
+# CHECK-NEXT: 1 4 1.00 sm4ekey z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 smax z0.b, z0.b, #-128
+# CHECK-NEXT: 1 2 0.17 smax z0.d, z0.d, #-128
+# CHECK-NEXT: 1 2 0.17 smax z0.h, z0.h, #-128
+# CHECK-NEXT: 1 2 0.17 smax z0.s, z0.s, #-128
+# CHECK-NEXT: 1 2 0.17 smax z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 smax z31.b, z31.b, #127
+# CHECK-NEXT: 1 2 0.17 smax z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 smax z31.d, z31.d, #127
+# CHECK-NEXT: 1 2 0.17 smax z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 smax z31.h, z31.h, #127
+# CHECK-NEXT: 1 2 0.17 smax z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 smax z31.s, z31.s, #127
+# CHECK-NEXT: 1 2 0.17 smaxp z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 smaxp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 smaxp z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 smaxp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 6 0.50 smaxv b0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 smaxv d0, p7, z31.d
+# CHECK-NEXT: 1 6 0.50 smaxv h0, p7, z31.h
+# CHECK-NEXT: 1 4 0.33 smaxv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 smin z0.b, z0.b, #-128
+# CHECK-NEXT: 1 2 0.17 smin z0.d, z0.d, #-128
+# CHECK-NEXT: 1 2 0.17 smin z0.h, z0.h, #-128
+# CHECK-NEXT: 1 2 0.17 smin z0.s, z0.s, #-128
+# CHECK-NEXT: 1 2 0.17 smin z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 smin z31.b, z31.b, #127
+# CHECK-NEXT: 1 2 0.17 smin z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 smin z31.d, z31.d, #127
+# CHECK-NEXT: 1 2 0.17 smin z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 smin z31.h, z31.h, #127
+# CHECK-NEXT: 1 2 0.17 smin z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 smin z31.s, z31.s, #127
+# CHECK-NEXT: 1 2 0.17 sminp z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 sminp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 sminp z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 sminp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 6 0.50 sminv b0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 sminv d0, p7, z31.d
+# CHECK-NEXT: 1 6 0.50 sminv h0, p7, z31.h
+# CHECK-NEXT: 1 4 0.33 sminv s0, p7, z31.s
+# CHECK-NEXT: 1 4 0.25 smlalb z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 smlalb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 smlalb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 smlalb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 smlalb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 smlalt z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 smlalt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 smlalt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 smlalt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 smlalt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 smlslb z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 smlslb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 smlslb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 smlslb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 smlslb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 smlslt z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 smlslt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 smlslt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 smlslt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 smlslt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 3 0.17 smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 smulh z0.b, p7/m, z0.b, z31.b
+# CHECK-NEXT: 1 4 0.25 smulh z0.b, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 smulh z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 4 0.25 smulh z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 4 0.25 smulh z0.h, z1.h, z2.h
+# CHECK-NEXT: 1 4 0.25 smulh z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 4 0.25 smulh z29.s, z30.s, z31.s
+# CHECK-NEXT: 1 4 0.25 smulh z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 4 0.25 smullb z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 smullb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 smullb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 smullb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 4 0.25 smullb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 4 0.25 smullt z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 smullt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 smullt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 smullt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 4 0.25 smullt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 3 1.00 splice z29.b, p7, { z30.b, z31.b }
+# CHECK-NEXT: 1 3 1.00 splice z29.d, p7, { z30.d, z31.d }
+# CHECK-NEXT: 1 3 1.00 splice z29.h, p7, { z30.h, z31.h }
+# CHECK-NEXT: 1 3 1.00 splice z29.s, p7, { z30.s, z31.s }
+# CHECK-NEXT: 1 3 1.00 splice z31.b, p7, z31.b, z31.b
+# CHECK-NEXT: 1 3 1.00 splice z31.d, p7, z31.d, z31.d
+# CHECK-NEXT: 1 3 1.00 splice z31.h, p7, z31.h, z31.h
+# CHECK-NEXT: 1 3 1.00 splice z31.s, p7, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 sqabs z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 sqabs z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 sqabs z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 sqabs z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 sqadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 sqadd z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 sqadd z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 sqadd z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 sqadd z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sqadd z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 sqadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 sqadd z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 sqadd z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sqadd z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 sqadd z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 sqadd z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sqadd z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 sqadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 sqadd z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 sqadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 sqadd z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.17 sqadd z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.17 sqadd z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.17 sqcadd z0.b, z0.b, z0.b, #90
+# CHECK-NEXT: 1 2 0.17 sqcadd z0.d, z0.d, z0.d, #90
+# CHECK-NEXT: 1 2 0.17 sqcadd z0.h, z0.h, z0.h, #90
+# CHECK-NEXT: 1 2 0.17 sqcadd z0.s, z0.s, z0.s, #90
+# CHECK-NEXT: 1 2 0.17 sqcadd z31.b, z31.b, z31.b, #270
+# CHECK-NEXT: 1 2 0.17 sqcadd z31.d, z31.d, z31.d, #270
+# CHECK-NEXT: 1 2 0.17 sqcadd z31.h, z31.h, z31.h, #270
+# CHECK-NEXT: 1 2 0.17 sqcadd z31.s, z31.s, z31.s, #270
+# CHECK-NEXT: 1 2 0.50 sqdecb x0
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, #14
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, w0
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdecb x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecd x0
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, #14
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, w0
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdecd x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.17 sqdecd z0.d
+# CHECK-NEXT: 1 2 0.17 sqdecd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 0.17 sqdecd z0.d, pow2
+# CHECK-NEXT: 1 2 0.17 sqdecd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdech x0
+# CHECK-NEXT: 1 2 0.50 sqdech x0, #14
+# CHECK-NEXT: 1 2 0.50 sqdech x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdech x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdech x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqdech x0, w0
+# CHECK-NEXT: 1 2 0.50 sqdech x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdech x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdech x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.17 sqdech z0.h
+# CHECK-NEXT: 1 2 0.17 sqdech z0.h, all, mul #16
+# CHECK-NEXT: 1 2 0.17 sqdech z0.h, pow2
+# CHECK-NEXT: 1 2 0.17 sqdech z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecp x0, p0.b
+# CHECK-NEXT: 1 2 0.50 sqdecp x0, p0.d
+# CHECK-NEXT: 1 2 0.50 sqdecp x0, p0.h
+# CHECK-NEXT: 1 2 0.50 sqdecp x0, p0.s
+# CHECK-NEXT: 1 2 0.50 sqdecp xzr, p15.b, wzr
+# CHECK-NEXT: 1 2 0.50 sqdecp xzr, p15.d, wzr
+# CHECK-NEXT: 1 2 0.50 sqdecp xzr, p15.h, wzr
+# CHECK-NEXT: 1 2 0.50 sqdecp xzr, p15.s, wzr
+# CHECK-NEXT: 1 7 1.00 sqdecp z0.d, p0.d
+# CHECK-NEXT: 1 7 1.00 sqdecp z0.h, p0.h
+# CHECK-NEXT: 1 7 1.00 sqdecp z0.s, p0.s
+# CHECK-NEXT: 1 2 0.50 sqdecw x0
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, #14
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, w0
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqdecw x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.17 sqdecw z0.s
+# CHECK-NEXT: 1 2 0.17 sqdecw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 0.17 sqdecw z0.s, pow2
+# CHECK-NEXT: 1 2 0.17 sqdecw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 4 0.25 sqdmlalb z0.d, z1.s, z15.s[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlalb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmlalb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqdmlalb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmlalb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqdmlalbt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmlalbt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqdmlalbt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmlalt z0.d, z1.s, z15.s[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlalt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmlalt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqdmlalt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmlalt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqdmlslb z0.d, z1.s, z15.s[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlslb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmlslb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqdmlslb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmlslb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqdmlslbt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmlslbt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqdmlslbt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmlslt z0.d, z1.s, z15.s[3]
+# CHECK-NEXT: 1 4 0.25 sqdmlslt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmlslt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqdmlslt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmlslt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqdmulh z0.b, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 sqdmulh z0.d, z1.d, z15.d[1]
+# CHECK-NEXT: 1 4 0.25 sqdmulh z0.h, z1.h, z2.h
+# CHECK-NEXT: 1 4 0.25 sqdmulh z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqdmulh z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 4 0.25 sqdmulh z29.s, z30.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmulh z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 4 0.25 sqdmullb z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 sqdmullb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 sqdmullb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqdmullb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmullb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqdmullt z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 sqdmullt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 sqdmullt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqdmullt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqdmullt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 sqincb x0
+# CHECK-NEXT: 1 2 0.50 sqincb x0, #14
+# CHECK-NEXT: 1 2 0.50 sqincb x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincb x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqincb x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqincb x0, w0
+# CHECK-NEXT: 1 2 0.50 sqincb x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincb x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqincb x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincd x0
+# CHECK-NEXT: 1 2 0.50 sqincd x0, #14
+# CHECK-NEXT: 1 2 0.50 sqincd x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincd x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqincd x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqincd x0, w0
+# CHECK-NEXT: 1 2 0.50 sqincd x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincd x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqincd x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.17 sqincd z0.d
+# CHECK-NEXT: 1 2 0.17 sqincd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 0.17 sqincd z0.d, pow2
+# CHECK-NEXT: 1 2 0.17 sqincd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 sqinch x0
+# CHECK-NEXT: 1 2 0.50 sqinch x0, #14
+# CHECK-NEXT: 1 2 0.50 sqinch x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqinch x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqinch x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqinch x0, w0
+# CHECK-NEXT: 1 2 0.50 sqinch x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqinch x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqinch x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.17 sqinch z0.h
+# CHECK-NEXT: 1 2 0.17 sqinch z0.h, all, mul #16
+# CHECK-NEXT: 1 2 0.17 sqinch z0.h, pow2
+# CHECK-NEXT: 1 2 0.17 sqinch z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincp x0, p0.b
+# CHECK-NEXT: 1 2 0.50 sqincp x0, p0.d
+# CHECK-NEXT: 1 2 0.50 sqincp x0, p0.h
+# CHECK-NEXT: 1 2 0.50 sqincp x0, p0.s
+# CHECK-NEXT: 1 2 0.50 sqincp xzr, p15.b, wzr
+# CHECK-NEXT: 1 2 0.50 sqincp xzr, p15.d, wzr
+# CHECK-NEXT: 1 2 0.50 sqincp xzr, p15.h, wzr
+# CHECK-NEXT: 1 2 0.50 sqincp xzr, p15.s, wzr
+# CHECK-NEXT: 1 7 1.00 sqincp z0.d, p0.d
+# CHECK-NEXT: 1 7 1.00 sqincp z0.h, p0.h
+# CHECK-NEXT: 1 7 1.00 sqincp z0.s, p0.s
+# CHECK-NEXT: 1 2 0.50 sqincw x0
+# CHECK-NEXT: 1 2 0.50 sqincw x0, #14
+# CHECK-NEXT: 1 2 0.50 sqincw x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincw x0, pow2
+# CHECK-NEXT: 1 2 0.50 sqincw x0, vl1
+# CHECK-NEXT: 1 2 0.50 sqincw x0, w0
+# CHECK-NEXT: 1 2 0.50 sqincw x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 sqincw x0, w0, pow2
+# CHECK-NEXT: 1 2 0.50 sqincw x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.17 sqincw z0.s
+# CHECK-NEXT: 1 2 0.17 sqincw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 0.17 sqincw z0.s, pow2
+# CHECK-NEXT: 1 2 0.17 sqincw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 2 0.17 sqneg z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.17 sqneg z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 sqneg z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 sqneg z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z0.b, z1.b, z2.b, #0
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z0.d, z1.d, z2.d, #0
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z0.h, z1.h, z2.h, #0
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z0.h, z1.h, z2.h[0], #0
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z0.s, z1.s, z2.s, #0
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z0.s, z1.s, z2.s[0], #0
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z15.b, z16.b, z17.b, #270
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z15.d, z16.d, z17.d, #270
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z15.h, z16.h, z17.h, #270
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z15.s, z16.s, z17.s, #270
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z29.b, z30.b, z31.b, #90
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z29.d, z30.d, z31.d, #90
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z29.h, z30.h, z31.h, #90
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z29.s, z30.s, z31.s, #90
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z31.b, z31.b, z31.b, #180
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z31.d, z31.d, z31.d, #180
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z31.h, z30.h, z7.h[0], #180
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z31.h, z31.h, z31.h, #180
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z31.s, z30.s, z7.s[0], #180
+# CHECK-NEXT: 1 4 0.25 sqrdcmlah z31.s, z31.s, z31.s, #180
+# CHECK-NEXT: 1 4 0.25 sqrdmlah z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqrdmlah z0.d, z1.d, z15.d[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.25 sqrdmlah z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqrdmlah z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqrdmlah z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqrdmlah z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh z0.d, z1.d, z15.d[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqrdmlsh z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh z0.b, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 sqrdmulh z0.d, z1.d, z15.d[1]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh z0.h, z1.h, z2.h
+# CHECK-NEXT: 1 4 0.25 sqrdmulh z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 4 0.25 sqrdmulh z29.s, z30.s, z31.s
+# CHECK-NEXT: 1 4 0.25 sqrdmulh z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 4 0.17 sqrshl z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 sqrshl z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 sqrshl z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 sqrshl z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 sqrshlr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 sqrshlr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 sqrshlr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 sqrshlr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 sqrshrnb z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrnb z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrnb z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrnb z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqrshrnb z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqrshrnb z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 sqrshrnt z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrnt z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrnt z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrnt z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqrshrnt z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqrshrnt z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 sqrshrunb z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrunb z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrunb z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrunb z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqrshrunb z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqrshrunb z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 sqrshrunt z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrunt z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrunt z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqrshrunt z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqrshrunt z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqrshrunt z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 sqshl z0.b, p0/m, z0.b, #0
+# CHECK-NEXT: 1 4 0.17 sqshl z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 sqshl z0.d, p0/m, z0.d, #0
+# CHECK-NEXT: 1 4 0.17 sqshl z0.h, p0/m, z0.h, #0
+# CHECK-NEXT: 1 4 0.17 sqshl z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 sqshl z0.s, p0/m, z0.s, #0
+# CHECK-NEXT: 1 4 0.17 sqshl z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 sqshl z31.b, p0/m, z31.b, #7
+# CHECK-NEXT: 1 4 0.17 sqshl z31.d, p0/m, z31.d, #63
+# CHECK-NEXT: 1 4 0.17 sqshl z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 sqshl z31.h, p0/m, z31.h, #15
+# CHECK-NEXT: 1 4 0.17 sqshl z31.s, p0/m, z31.s, #31
+# CHECK-NEXT: 1 4 0.17 sqshlr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 sqshlr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 sqshlr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 sqshlr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 sqshlu z0.b, p0/m, z0.b, #0
+# CHECK-NEXT: 1 4 0.17 sqshlu z0.d, p0/m, z0.d, #0
+# CHECK-NEXT: 1 4 0.17 sqshlu z0.h, p0/m, z0.h, #0
+# CHECK-NEXT: 1 4 0.17 sqshlu z0.s, p0/m, z0.s, #0
+# CHECK-NEXT: 1 4 0.17 sqshlu z31.b, p0/m, z31.b, #7
+# CHECK-NEXT: 1 4 0.17 sqshlu z31.d, p0/m, z31.d, #63
+# CHECK-NEXT: 1 4 0.17 sqshlu z31.h, p0/m, z31.h, #15
+# CHECK-NEXT: 1 4 0.17 sqshlu z31.s, p0/m, z31.s, #31
+# CHECK-NEXT: 1 4 0.17 sqshrnb z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqshrnb z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqshrnb z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqshrnb z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqshrnb z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqshrnb z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 sqshrnt z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqshrnt z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqshrnt z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqshrnt z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqshrnt z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqshrnt z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 sqshrunb z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqshrunb z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqshrunb z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqshrunb z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqshrunb z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqshrunb z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 sqshrunt z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 sqshrunt z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 sqshrunt z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 sqshrunt z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 sqshrunt z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 sqshrunt z31.s, z31.d, #32
+# CHECK-NEXT: 1 2 0.17 sqsub z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 sqsub z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 sqsub z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 sqsub z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 sqsub z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sqsub z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 sqsub z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 sqsub z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 sqsub z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sqsub z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 sqsub z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 sqsub z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sqsub z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 sqsub z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 sqsub z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 sqsub z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 sqsub z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.17 sqsub z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.17 sqsub z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.17 sqsubr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 sqsubr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 sqsubr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 sqsubr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 sqxtnb z0.b, z31.h
+# CHECK-NEXT: 1 4 0.17 sqxtnb z0.h, z31.s
+# CHECK-NEXT: 1 4 0.17 sqxtnb z0.s, z31.d
+# CHECK-NEXT: 1 4 0.17 sqxtnt z0.b, z31.h
+# CHECK-NEXT: 1 4 0.17 sqxtnt z0.h, z31.s
+# CHECK-NEXT: 1 4 0.17 sqxtnt z0.s, z31.d
+# CHECK-NEXT: 1 4 0.17 sqxtunb z0.b, z31.h
+# CHECK-NEXT: 1 4 0.17 sqxtunb z0.h, z31.s
+# CHECK-NEXT: 1 4 0.17 sqxtunb z0.s, z31.d
+# CHECK-NEXT: 1 4 0.17 sqxtunt z0.b, z31.h
+# CHECK-NEXT: 1 4 0.17 sqxtunt z0.h, z31.s
+# CHECK-NEXT: 1 4 0.17 sqxtunt z0.s, z31.d
+# CHECK-NEXT: 1 2 0.17 srhadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 srhadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 srhadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 srhadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 sri z0.b, z0.b, #1
+# CHECK-NEXT: 1 2 0.17 sri z0.d, z0.d, #1
+# CHECK-NEXT: 1 2 0.17 sri z0.h, z0.h, #1
+# CHECK-NEXT: 1 2 0.17 sri z0.s, z0.s, #1
+# CHECK-NEXT: 1 2 0.17 sri z31.b, z31.b, #8
+# CHECK-NEXT: 1 2 0.17 sri z31.d, z31.d, #64
+# CHECK-NEXT: 1 2 0.17 sri z31.h, z31.h, #16
+# CHECK-NEXT: 1 2 0.17 sri z31.s, z31.s, #32
+# CHECK-NEXT: 1 4 0.17 srshl z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 srshl z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 srshl z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 srshl z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 srshlr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 srshlr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 srshlr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 srshlr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 srshr z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 4 0.17 srshr z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 srshr z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 srshr z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 srshr z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 4 0.17 srshr z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 4 0.17 srshr z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 4 0.17 srshr z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 4 0.17 srsra z0.b, z0.b, #1
+# CHECK-NEXT: 1 4 0.17 srsra z0.d, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 srsra z0.h, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 srsra z0.s, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 srsra z31.b, z31.b, #8
+# CHECK-NEXT: 1 4 0.17 srsra z31.d, z31.d, #64
+# CHECK-NEXT: 1 4 0.17 srsra z31.h, z31.h, #16
+# CHECK-NEXT: 1 4 0.17 srsra z31.s, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 sshllb z0.d, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 sshllb z0.h, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 sshllb z0.s, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 sshllb z31.d, z31.s, #31
+# CHECK-NEXT: 1 2 0.17 sshllb z31.h, z31.b, #7
+# CHECK-NEXT: 1 2 0.17 sshllb z31.s, z31.h, #15
+# CHECK-NEXT: 1 2 0.17 sshllt z0.d, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 sshllt z0.h, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 sshllt z0.s, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 sshllt z31.d, z31.s, #31
+# CHECK-NEXT: 1 2 0.17 sshllt z31.h, z31.b, #7
+# CHECK-NEXT: 1 2 0.17 sshllt z31.s, z31.h, #15
+# CHECK-NEXT: 1 4 0.17 ssra z0.b, z0.b, #1
+# CHECK-NEXT: 1 4 0.17 ssra z0.d, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 ssra z0.h, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 ssra z0.s, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 ssra z31.b, z31.b, #8
+# CHECK-NEXT: 1 4 0.17 ssra z31.d, z31.d, #64
+# CHECK-NEXT: 1 4 0.17 ssra z31.h, z31.h, #16
+# CHECK-NEXT: 1 4 0.17 ssra z31.s, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 ssublb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 ssublb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 ssublb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 ssublbt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 ssublbt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 2 0.17 ssublbt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 ssublt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 ssublt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 ssublt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 ssubltb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 ssubltb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 2 0.17 ssubltb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 ssubwb z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 ssubwb z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 ssubwb z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 ssubwt z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 ssubwt z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 ssubwt z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.b }, p0, [x0, x0]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.b }, p0, [x0]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.d }, p0, [x0, x0]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.d }, p0, [x0]
+# CHECK-NEXT: 1 4 1.50 * st1b { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.h }, p0, [x0, x0]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.h }, p0, [x0]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.s }, p0, [x0, x0]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.s }, p0, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.s }, p0, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 2 0.50 * st1b { z0.s }, p0, [x0]
+# CHECK-NEXT: 1 5 2.50 * st1b { z0.s }, p7, [z0.s]
+# CHECK-NEXT: 1 2 0.50 * st1b { z21.b }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1b { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1b { z21.h }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1b { z21.s }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1b { z31.b }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1b { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 4 1.50 * st1b { z31.d }, p7, [z31.d, #31]
+# CHECK-NEXT: 1 2 0.50 * st1b { z31.h }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1b { z31.s }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 5 2.50 * st1b { z31.s }, p7, [z31.s, #31]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0, z0.d, lsl #3]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1d { z0.d }, p0, [x0]
+# CHECK-NEXT: 1 4 1.50 * st1d { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1d { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1d { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 4 1.50 * st1d { z31.d }, p7, [z31.d, #248]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0, z0.d, lsl #1]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.d }, p0, [x0]
+# CHECK-NEXT: 1 4 1.50 * st1h { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.h }, p0, [x0]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.s }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 2 3.00 * st1h { z0.s }, p0, [x0, z0.s, sxtw #1]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.s }, p0, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 2 3.00 * st1h { z0.s }, p0, [x0, z0.s, uxtw #1]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.s }, p0, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 2 0.50 * st1h { z0.s }, p0, [x0]
+# CHECK-NEXT: 1 5 2.50 * st1h { z0.s }, p7, [z0.s]
+# CHECK-NEXT: 1 2 0.50 * st1h { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1h { z21.h }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1h { z21.s }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1h { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 4 1.50 * st1h { z31.d }, p7, [z31.d, #62]
+# CHECK-NEXT: 1 2 0.50 * st1h { z31.h }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1h { z31.s }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 5 2.50 * st1h { z31.s }, p7, [z31.s, #62]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0, z0.d, lsl #2]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.d }, p0, [x0]
+# CHECK-NEXT: 1 4 1.50 * st1w { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 2 3.00 * st1w { z0.s }, p0, [x0, z0.s, sxtw #2]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.s }, p0, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 2 3.00 * st1w { z0.s }, p0, [x0, z0.s, uxtw #2]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.s }, p0, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 2 0.50 * st1w { z0.s }, p0, [x0]
+# CHECK-NEXT: 1 5 2.50 * st1w { z0.s }, p7, [z0.s]
+# CHECK-NEXT: 1 2 0.50 * st1w { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1w { z21.s }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 1 2 0.50 * st1w { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 4 1.50 * st1w { z31.d }, p7, [z31.d, #124]
+# CHECK-NEXT: 1 2 0.50 * st1w { z31.s }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 5 2.50 * st1w { z31.s }, p7, [z31.s, #124]
+# CHECK-NEXT: 1 4 1.00 * st2b { z0.b, z1.b }, p0, [x0, x0]
+# CHECK-NEXT: 1 4 1.00 * st2b { z0.b, z1.b }, p0, [x0]
+# CHECK-NEXT: 1 4 1.00 * st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2b { z5.b, z6.b }, p3, [x17, x16]
+# CHECK-NEXT: 1 4 1.00 * st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 4 1.00 * st2d { z0.d, z1.d }, p0, [x0]
+# CHECK-NEXT: 1 4 1.00 * st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT: 1 4 1.00 * st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 4 1.00 * st2h { z0.h, z1.h }, p0, [x0]
+# CHECK-NEXT: 1 4 1.00 * st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 4 1.00 * st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 4 1.00 * st2w { z0.s, z1.s }, p0, [x0]
+# CHECK-NEXT: 1 4 1.00 * st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 1 4 1.00 * st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT: 1 5 1.50 * st3b { z0.b - z2.b }, p0, [x0, x0]
+# CHECK-NEXT: 1 5 1.50 * st3b { z0.b - z2.b }, p0, [x0]
+# CHECK-NEXT: 1 5 1.50 * st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3b { z5.b - z7.b }, p3, [x17, x16]
+# CHECK-NEXT: 1 5 1.50 * st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 5 1.50 * st3d { z0.d - z2.d }, p0, [x0]
+# CHECK-NEXT: 1 5 1.50 * st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT: 1 5 1.50 * st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 5 1.50 * st3h { z0.h - z2.h }, p0, [x0]
+# CHECK-NEXT: 1 5 1.50 * st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 5 1.50 * st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 5 1.50 * st3w { z0.s - z2.s }, p0, [x0]
+# CHECK-NEXT: 1 5 1.50 * st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 1 5 1.50 * st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT: 1 7 2.00 * st4b { z0.b - z3.b }, p0, [x0, x0]
+# CHECK-NEXT: 1 7 2.00 * st4b { z0.b - z3.b }, p0, [x0]
+# CHECK-NEXT: 1 7 2.00 * st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4b { z5.b - z8.b }, p3, [x17, x16]
+# CHECK-NEXT: 1 7 2.00 * st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 7 2.00 * st4d { z0.d - z3.d }, p0, [x0]
+# CHECK-NEXT: 1 7 2.00 * st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT: 1 7 2.00 * st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 7 2.00 * st4h { z0.h - z3.h }, p0, [x0]
+# CHECK-NEXT: 1 7 2.00 * st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 7 2.00 * st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 7 2.00 * st4w { z0.s - z3.s }, p0, [x0]
+# CHECK-NEXT: 1 7 2.00 * st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 1 7 2.00 * st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT: 1 2 0.50 * stnt1b { z0.b }, p0, [x0, x0]
+# CHECK-NEXT: 1 2 0.50 * stnt1b { z0.b }, p0, [x0]
+# CHECK-NEXT: 1 4 1.50 * stnt1b { z0.d }, p0, [z1.d]
+# CHECK-NEXT: 1 5 3.00 * stnt1b { z0.s }, p0, [z1.s]
+# CHECK-NEXT: 1 2 0.50 * stnt1b { z21.b }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 1 2 0.50 * stnt1b { z23.b }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 4 1.50 * stnt1b { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: 1 4 1.50 * stnt1b { z31.d }, p7, [z31.d]
+# CHECK-NEXT: 1 5 3.00 * stnt1b { z31.s }, p7, [z31.s, x0]
+# CHECK-NEXT: 1 5 3.00 * stnt1b { z31.s }, p7, [z31.s]
+# CHECK-NEXT: 1 2 0.50 * stnt1d { z0.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 2 0.50 * stnt1d { z0.d }, p0, [x0]
+# CHECK-NEXT: 1 4 1.50 * stnt1d { z0.d }, p0, [z1.d]
+# CHECK-NEXT: 1 2 0.50 * stnt1d { z21.d }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 1 2 0.50 * stnt1d { z23.d }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 4 1.50 * stnt1d { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: 1 4 1.50 * stnt1d { z31.d }, p7, [z31.d]
+# CHECK-NEXT: 1 4 1.50 * stnt1h { z0.d }, p0, [z1.d]
+# CHECK-NEXT: 1 2 0.50 * stnt1h { z0.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 2 0.50 * stnt1h { z0.h }, p0, [x0]
+# CHECK-NEXT: 1 5 3.00 * stnt1h { z0.s }, p0, [z1.s]
+# CHECK-NEXT: 1 2 0.50 * stnt1h { z21.h }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 1 2 0.50 * stnt1h { z23.h }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 4 1.50 * stnt1h { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: 1 4 1.50 * stnt1h { z31.d }, p7, [z31.d]
+# CHECK-NEXT: 1 5 3.00 * stnt1h { z31.s }, p7, [z31.s, x0]
+# CHECK-NEXT: 1 5 3.00 * stnt1h { z31.s }, p7, [z31.s]
+# CHECK-NEXT: 1 4 1.50 * stnt1w { z0.d }, p0, [z1.d]
+# CHECK-NEXT: 1 2 0.50 * stnt1w { z0.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 2 0.50 * stnt1w { z0.s }, p0, [x0]
+# CHECK-NEXT: 1 5 3.00 * stnt1w { z0.s }, p0, [z1.s]
+# CHECK-NEXT: 1 2 0.50 * stnt1w { z21.s }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 1 2 0.50 * stnt1w { z23.s }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 4 1.50 * stnt1w { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: 1 4 1.50 * stnt1w { z31.d }, p7, [z31.d]
+# CHECK-NEXT: 1 5 3.00 * stnt1w { z31.s }, p7, [z31.s, x0]
+# CHECK-NEXT: 1 5 3.00 * stnt1w { z31.s }, p7, [z31.s]
+# CHECK-NEXT: 1 1 0.50 * str p0, [x0]
+# CHECK-NEXT: 1 1 0.50 * str p15, [sp, #-256, mul vl]
+# CHECK-NEXT: 1 1 0.50 * str p5, [x10, #255, mul vl]
+# CHECK-NEXT: 1 2 0.50 * str z0, [x0]
+# CHECK-NEXT: 1 2 0.50 * str z21, [x10, #-256, mul vl]
+# CHECK-NEXT: 1 2 0.50 * str z31, [sp, #255, mul vl]
+# CHECK-NEXT: 1 2 0.17 sub z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 sub z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 sub z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 sub z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 sub z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 sub z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sub z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 sub z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 sub z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 sub z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sub z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 sub z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 sub z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 sub z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 sub z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 sub z21.b, p5/m, z21.b, z10.b
+# CHECK-NEXT: 1 2 0.17 sub z21.b, z10.b, z21.b
+# CHECK-NEXT: 1 2 0.17 sub z21.d, p5/m, z21.d, z10.d
+# CHECK-NEXT: 1 2 0.17 sub z21.d, z10.d, z21.d
+# CHECK-NEXT: 1 2 0.17 sub z21.h, p5/m, z21.h, z10.h
+# CHECK-NEXT: 1 2 0.17 sub z21.h, z10.h, z21.h
+# CHECK-NEXT: 1 2 0.17 sub z21.s, p5/m, z21.s, z10.s
+# CHECK-NEXT: 1 2 0.17 sub z21.s, z10.s, z21.s
+# CHECK-NEXT: 1 2 0.17 sub z23.b, p3/m, z23.b, z13.b
+# CHECK-NEXT: 1 2 0.17 sub z23.b, z13.b, z8.b
+# CHECK-NEXT: 1 2 0.17 sub z23.d, p3/m, z23.d, z13.d
+# CHECK-NEXT: 1 2 0.17 sub z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.17 sub z23.h, p3/m, z23.h, z13.h
+# CHECK-NEXT: 1 2 0.17 sub z23.h, z13.h, z8.h
+# CHECK-NEXT: 1 2 0.17 sub z23.s, p3/m, z23.s, z13.s
+# CHECK-NEXT: 1 2 0.17 sub z23.s, z13.s, z8.s
+# CHECK-NEXT: 1 2 0.17 sub z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 sub z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 sub z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 sub z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 sub z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.17 sub z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 sub z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 sub z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.17 sub z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 sub z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 sub z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.17 sub z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 subhnb z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 subhnb z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 subhnb z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 subhnt z0.b, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 subhnt z0.h, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.17 subhnt z0.s, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.17 subr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 subr z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 subr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 subr z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 subr z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 subr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 subr z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 subr z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 subr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 subr z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 subr z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 subr z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 subr z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.17 subr z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.17 subr z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.17 sunpkhi z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 sunpkhi z31.h, z31.b
+# CHECK-NEXT: 1 2 0.17 sunpkhi z31.s, z31.h
+# CHECK-NEXT: 1 2 0.17 sunpklo z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 sunpklo z31.h, z31.b
+# CHECK-NEXT: 1 2 0.17 sunpklo z31.s, z31.h
+# CHECK-NEXT: 1 2 0.17 suqadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 suqadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 suqadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 suqadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 sxtb z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 sxtb z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 0.17 sxtb z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.17 sxtb z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 sxtb z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 sxtb z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 sxth z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 sxth z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.17 sxth z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 sxth z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 sxtw z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 sxtw z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 tbl z28.b, { z29.b, z30.b }, z31.b
+# CHECK-NEXT: 1 2 0.17 tbl z28.d, { z29.d, z30.d }, z31.d
+# CHECK-NEXT: 1 2 0.17 tbl z28.h, { z29.h, z30.h }, z31.h
+# CHECK-NEXT: 1 2 0.17 tbl z28.s, { z29.s, z30.s }, z31.s
+# CHECK-NEXT: 1 2 0.17 tbl z31.b, { z31.b }, z31.b
+# CHECK-NEXT: 1 2 0.17 tbl z31.d, { z31.d }, z31.d
+# CHECK-NEXT: 1 2 0.17 tbl z31.h, { z31.h }, z31.h
+# CHECK-NEXT: 1 2 0.17 tbl z31.s, { z31.s }, z31.s
+# CHECK-NEXT: 1 2 0.17 tbx z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 tbx z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 tbx z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 tbx z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 trn1 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 trn1 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 0.50 trn1 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 0.50 trn1 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.17 trn1 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 trn1 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 trn1 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 trn1 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 trn2 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 trn2 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 0.50 trn2 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 0.50 trn2 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.17 trn2 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 trn2 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 trn2 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 trn2 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 4 0.17 uaba z0.b, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.17 uaba z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.17 uaba z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 uaba z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 uabalb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 uabalb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.17 uabalb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.17 uabalt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.17 uabalt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.17 uabalt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uabd z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 uabd z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 uabd z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uabd z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 uabdlb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 uabdlb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uabdlb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 uabdlt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 uabdlt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uabdlt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 4 0.17 uadalp z0.h, p0/m, z1.b
+# CHECK-NEXT: 1 4 0.17 uadalp z29.s, p0/m, z30.h
+# CHECK-NEXT: 1 4 0.17 uadalp z30.d, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 uaddlb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 uaddlb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uaddlb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 uaddlt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 uaddlt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uaddlt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 8 0.75 uaddv d0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 uaddv d0, p7, z31.d
+# CHECK-NEXT: 1 6 0.50 uaddv d0, p7, z31.h
+# CHECK-NEXT: 1 6 0.50 uaddv d0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 uaddwb z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 uaddwb z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 uaddwb z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 uaddwt z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 uaddwt z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 uaddwt z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 3 0.25 ucvtf z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 ucvtf z0.d, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 ucvtf z0.h, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 ucvtf z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 3 0.25 ucvtf z0.h, p0/m, z0.s
+# CHECK-NEXT: 1 3 0.25 ucvtf z0.s, p0/m, z0.d
+# CHECK-NEXT: 1 3 0.25 ucvtf z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 20 7.00 udiv z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 udiv z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 20 7.00 udivr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 udivr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 3 0.25 udot z0.d, z1.h, z15.h[1]
+# CHECK-NEXT: 1 3 0.25 udot z0.d, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.17 udot z0.s, z1.b, z31.b
+# CHECK-NEXT: 1 3 0.17 udot z0.s, z1.b, z7.b[3]
+# CHECK-NEXT: 1 2 0.17 uhadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 uhadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 uhadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 uhadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 uhsub z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 uhsub z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 uhsub z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 uhsub z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 uhsubr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 uhsubr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 uhsubr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 uhsubr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 umax z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 umax z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 umax z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 umax z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 umax z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 umax z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 umaxp z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 umaxp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 umaxp z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 umaxp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 6 0.50 umaxv b0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 umaxv d0, p7, z31.d
+# CHECK-NEXT: 1 6 0.50 umaxv h0, p7, z31.h
+# CHECK-NEXT: 1 4 0.33 umaxv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.17 umin z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 umin z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 umin z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 umin z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 umin z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 umin z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 uminp z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 uminp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 uminp z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 uminp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 6 0.50 uminv b0, p7, z31.b
+# CHECK-NEXT: 1 4 0.33 uminv d0, p7, z31.d
+# CHECK-NEXT: 1 6 0.50 uminv h0, p7, z31.h
+# CHECK-NEXT: 1 4 0.33 uminv s0, p7, z31.s
+# CHECK-NEXT: 1 4 0.25 umlalb z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 umlalb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 umlalb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 umlalb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 umlalb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 umlalt z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 umlalt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 umlalt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 umlalt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 umlalt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 umlslb z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 umlslb z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 umlslb z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 umlslb z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 umlslb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 umlslt z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 umlslt z0.d, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.25 umlslt z0.h, z1.b, z31.b
+# CHECK-NEXT: 1 4 0.25 umlslt z0.s, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.25 umlslt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 3 0.17 ummla z0.s, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 umulh z0.b, p7/m, z0.b, z31.b
+# CHECK-NEXT: 1 4 0.25 umulh z0.b, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 umulh z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 4 0.25 umulh z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 4 0.25 umulh z0.h, z1.h, z2.h
+# CHECK-NEXT: 1 4 0.25 umulh z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 4 0.25 umulh z29.s, z30.s, z31.s
+# CHECK-NEXT: 1 4 0.25 umulh z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 4 0.25 umullb z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 umullb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 umullb z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 umullb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 4 0.25 umullb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 4 0.25 umullt z0.d, z1.s, z15.s[1]
+# CHECK-NEXT: 1 4 0.25 umullt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 4 0.25 umullt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.25 umullt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 4 0.25 umullt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 uqadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 uqadd z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 uqadd z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 uqadd z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 uqadd z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 uqadd z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 uqadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 uqadd z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 uqadd z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 uqadd z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 uqadd z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 uqadd z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 uqadd z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 uqadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 uqadd z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 uqadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 uqadd z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.17 uqadd z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.17 uqadd z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.50 uqdecb w0
+# CHECK-NEXT: 1 2 0.50 uqdecb w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecb w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdecb w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecb x0
+# CHECK-NEXT: 1 2 0.50 uqdecb x0, #14
+# CHECK-NEXT: 1 2 0.50 uqdecb x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecb x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdecb x0, vl1
+# CHECK-NEXT: 1 2 0.50 uqdecd w0
+# CHECK-NEXT: 1 2 0.50 uqdecd w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecd w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdecd w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecd x0
+# CHECK-NEXT: 1 2 0.50 uqdecd x0, #14
+# CHECK-NEXT: 1 2 0.50 uqdecd x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecd x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdecd x0, vl1
+# CHECK-NEXT: 1 2 0.17 uqdecd z0.d
+# CHECK-NEXT: 1 2 0.17 uqdecd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 0.17 uqdecd z0.d, pow2
+# CHECK-NEXT: 1 2 0.17 uqdecd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdech w0
+# CHECK-NEXT: 1 2 0.50 uqdech w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdech w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdech w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdech x0
+# CHECK-NEXT: 1 2 0.50 uqdech x0, #14
+# CHECK-NEXT: 1 2 0.50 uqdech x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdech x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdech x0, vl1
+# CHECK-NEXT: 1 2 0.17 uqdech z0.h
+# CHECK-NEXT: 1 2 0.17 uqdech z0.h, all, mul #16
+# CHECK-NEXT: 1 2 0.17 uqdech z0.h, pow2
+# CHECK-NEXT: 1 2 0.17 uqdech z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecp wzr, p15.b
+# CHECK-NEXT: 1 2 0.50 uqdecp wzr, p15.d
+# CHECK-NEXT: 1 2 0.50 uqdecp wzr, p15.h
+# CHECK-NEXT: 1 2 0.50 uqdecp wzr, p15.s
+# CHECK-NEXT: 1 2 0.50 uqdecp x0, p0.b
+# CHECK-NEXT: 1 2 0.50 uqdecp x0, p0.d
+# CHECK-NEXT: 1 2 0.50 uqdecp x0, p0.h
+# CHECK-NEXT: 1 2 0.50 uqdecp x0, p0.s
+# CHECK-NEXT: 1 7 1.00 uqdecp z0.d, p0.d
+# CHECK-NEXT: 1 7 1.00 uqdecp z0.h, p0.h
+# CHECK-NEXT: 1 7 1.00 uqdecp z0.s, p0.s
+# CHECK-NEXT: 1 2 0.50 uqdecw w0
+# CHECK-NEXT: 1 2 0.50 uqdecw w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecw w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdecw w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecw x0
+# CHECK-NEXT: 1 2 0.50 uqdecw x0, #14
+# CHECK-NEXT: 1 2 0.50 uqdecw x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqdecw x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqdecw x0, vl1
+# CHECK-NEXT: 1 2 0.17 uqdecw z0.s
+# CHECK-NEXT: 1 2 0.17 uqdecw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 0.17 uqdecw z0.s, pow2
+# CHECK-NEXT: 1 2 0.17 uqdecw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincb w0
+# CHECK-NEXT: 1 2 0.50 uqincb w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincb w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqincb w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincb x0
+# CHECK-NEXT: 1 2 0.50 uqincb x0, #14
+# CHECK-NEXT: 1 2 0.50 uqincb x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincb x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqincb x0, vl1
+# CHECK-NEXT: 1 2 0.50 uqincd w0
+# CHECK-NEXT: 1 2 0.50 uqincd w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincd w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqincd w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincd x0
+# CHECK-NEXT: 1 2 0.50 uqincd x0, #14
+# CHECK-NEXT: 1 2 0.50 uqincd x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincd x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqincd x0, vl1
+# CHECK-NEXT: 1 2 0.17 uqincd z0.d
+# CHECK-NEXT: 1 2 0.17 uqincd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 0.17 uqincd z0.d, pow2
+# CHECK-NEXT: 1 2 0.17 uqincd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqinch w0
+# CHECK-NEXT: 1 2 0.50 uqinch w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqinch w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqinch w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqinch x0
+# CHECK-NEXT: 1 2 0.50 uqinch x0, #14
+# CHECK-NEXT: 1 2 0.50 uqinch x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqinch x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqinch x0, vl1
+# CHECK-NEXT: 1 2 0.17 uqinch z0.h
+# CHECK-NEXT: 1 2 0.17 uqinch z0.h, all, mul #16
+# CHECK-NEXT: 1 2 0.17 uqinch z0.h, pow2
+# CHECK-NEXT: 1 2 0.17 uqinch z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincp wzr, p15.b
+# CHECK-NEXT: 1 2 0.50 uqincp wzr, p15.d
+# CHECK-NEXT: 1 2 0.50 uqincp wzr, p15.h
+# CHECK-NEXT: 1 2 0.50 uqincp wzr, p15.s
+# CHECK-NEXT: 1 2 0.50 uqincp x0, p0.b
+# CHECK-NEXT: 1 2 0.50 uqincp x0, p0.d
+# CHECK-NEXT: 1 2 0.50 uqincp x0, p0.h
+# CHECK-NEXT: 1 2 0.50 uqincp x0, p0.s
+# CHECK-NEXT: 1 7 1.00 uqincp z0.d, p0.d
+# CHECK-NEXT: 1 7 1.00 uqincp z0.h, p0.h
+# CHECK-NEXT: 1 7 1.00 uqincp z0.s, p0.s
+# CHECK-NEXT: 1 2 0.50 uqincw w0
+# CHECK-NEXT: 1 2 0.50 uqincw w0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincw w0, pow2
+# CHECK-NEXT: 1 2 0.50 uqincw w0, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincw x0
+# CHECK-NEXT: 1 2 0.50 uqincw x0, #14
+# CHECK-NEXT: 1 2 0.50 uqincw x0, all, mul #16
+# CHECK-NEXT: 1 2 0.50 uqincw x0, pow2
+# CHECK-NEXT: 1 2 0.50 uqincw x0, vl1
+# CHECK-NEXT: 1 2 0.17 uqincw z0.s
+# CHECK-NEXT: 1 2 0.17 uqincw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 0.17 uqincw z0.s, pow2
+# CHECK-NEXT: 1 2 0.17 uqincw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 4 0.17 uqrshl z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 uqrshl z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 uqrshl z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 uqrshl z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 uqrshlr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 uqrshlr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 uqrshlr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 uqrshlr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 uqrshrnb z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 uqrshrnb z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 uqrshrnb z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 uqrshrnb z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 uqrshrnb z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 uqrshrnb z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 uqrshrnt z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 uqrshrnt z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 uqrshrnt z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 uqrshrnt z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 uqrshrnt z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 uqrshrnt z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 uqshl z0.b, p0/m, z0.b, #0
+# CHECK-NEXT: 1 4 0.17 uqshl z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 uqshl z0.d, p0/m, z0.d, #0
+# CHECK-NEXT: 1 4 0.17 uqshl z0.h, p0/m, z0.h, #0
+# CHECK-NEXT: 1 4 0.17 uqshl z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 uqshl z0.s, p0/m, z0.s, #0
+# CHECK-NEXT: 1 4 0.17 uqshl z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 uqshl z31.b, p0/m, z31.b, #7
+# CHECK-NEXT: 1 4 0.17 uqshl z31.d, p0/m, z31.d, #63
+# CHECK-NEXT: 1 4 0.17 uqshl z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 uqshl z31.h, p0/m, z31.h, #15
+# CHECK-NEXT: 1 4 0.17 uqshl z31.s, p0/m, z31.s, #31
+# CHECK-NEXT: 1 4 0.17 uqshlr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 uqshlr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 uqshlr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 uqshlr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 uqshrnb z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 uqshrnb z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 uqshrnb z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 uqshrnb z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 uqshrnb z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 uqshrnb z31.s, z31.d, #32
+# CHECK-NEXT: 1 4 0.17 uqshrnt z0.b, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 uqshrnt z0.h, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 uqshrnt z0.s, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 uqshrnt z31.b, z31.h, #8
+# CHECK-NEXT: 1 4 0.17 uqshrnt z31.h, z31.s, #16
+# CHECK-NEXT: 1 4 0.17 uqshrnt z31.s, z31.d, #32
+# CHECK-NEXT: 1 2 0.17 uqsub z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 uqsub z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 uqsub z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 uqsub z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.17 uqsub z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 uqsub z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 uqsub z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 uqsub z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 uqsub z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 uqsub z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 uqsub z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 uqsub z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.17 uqsub z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 uqsub z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 uqsub z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.17 uqsub z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 2 0.17 uqsub z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.17 uqsub z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.17 uqsub z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.17 uqsubr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 uqsubr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 uqsubr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 uqsubr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 uqxtnb z0.b, z31.h
+# CHECK-NEXT: 1 4 0.17 uqxtnb z0.h, z31.s
+# CHECK-NEXT: 1 4 0.17 uqxtnb z0.s, z31.d
+# CHECK-NEXT: 1 4 0.17 uqxtnt z0.b, z31.h
+# CHECK-NEXT: 1 4 0.17 uqxtnt z0.h, z31.s
+# CHECK-NEXT: 1 4 0.17 uqxtnt z0.s, z31.d
+# CHECK-NEXT: 1 4 0.25 urecpe z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 urhadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 urhadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 urhadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 urhadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 urshl z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 urshl z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 urshl z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 urshl z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 urshlr z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 4 0.17 urshlr z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 4 0.17 urshlr z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 4 0.17 urshlr z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 urshr z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 4 0.17 urshr z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 urshr z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 urshr z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 urshr z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 4 0.17 urshr z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 4 0.17 urshr z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 4 0.17 urshr z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 4 0.25 ursqrte z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 4 0.17 ursra z0.b, z0.b, #1
+# CHECK-NEXT: 1 4 0.17 ursra z0.d, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 ursra z0.h, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 ursra z0.s, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 ursra z31.b, z31.b, #8
+# CHECK-NEXT: 1 4 0.17 ursra z31.d, z31.d, #64
+# CHECK-NEXT: 1 4 0.17 ursra z31.h, z31.h, #16
+# CHECK-NEXT: 1 4 0.17 ursra z31.s, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 ushllb z0.d, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 ushllb z0.h, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 ushllb z0.s, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 ushllb z31.d, z31.s, #31
+# CHECK-NEXT: 1 2 0.17 ushllb z31.h, z31.b, #7
+# CHECK-NEXT: 1 2 0.17 ushllb z31.s, z31.h, #15
+# CHECK-NEXT: 1 2 0.17 ushllt z0.d, z0.s, #0
+# CHECK-NEXT: 1 2 0.17 ushllt z0.h, z0.b, #0
+# CHECK-NEXT: 1 2 0.17 ushllt z0.s, z0.h, #0
+# CHECK-NEXT: 1 2 0.17 ushllt z31.d, z31.s, #31
+# CHECK-NEXT: 1 2 0.17 ushllt z31.h, z31.b, #7
+# CHECK-NEXT: 1 2 0.17 ushllt z31.s, z31.h, #15
+# CHECK-NEXT: 1 3 0.17 usmmla z0.s, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 usqadd z0.b, p0/m, z0.b, z1.b
+# CHECK-NEXT: 1 2 0.17 usqadd z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: 1 2 0.17 usqadd z29.s, p7/m, z29.s, z30.s
+# CHECK-NEXT: 1 2 0.17 usqadd z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: 1 4 0.17 usra z0.b, z0.b, #1
+# CHECK-NEXT: 1 4 0.17 usra z0.d, z0.d, #1
+# CHECK-NEXT: 1 4 0.17 usra z0.h, z0.h, #1
+# CHECK-NEXT: 1 4 0.17 usra z0.s, z0.s, #1
+# CHECK-NEXT: 1 4 0.17 usra z31.b, z31.b, #8
+# CHECK-NEXT: 1 4 0.17 usra z31.d, z31.d, #64
+# CHECK-NEXT: 1 4 0.17 usra z31.h, z31.h, #16
+# CHECK-NEXT: 1 4 0.17 usra z31.s, z31.s, #32
+# CHECK-NEXT: 1 2 0.17 usublb z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 usublb z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 usublb z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 usublt z0.h, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.17 usublt z29.s, z30.h, z31.h
+# CHECK-NEXT: 1 2 0.17 usublt z31.d, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.17 usubwb z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 usubwb z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 usubwb z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 usubwt z0.h, z1.h, z2.b
+# CHECK-NEXT: 1 2 0.17 usubwt z29.s, z30.s, z31.h
+# CHECK-NEXT: 1 2 0.17 usubwt z31.d, z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 uunpkhi z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 uunpkhi z31.h, z31.b
+# CHECK-NEXT: 1 2 0.17 uunpkhi z31.s, z31.h
+# CHECK-NEXT: 1 2 0.17 uunpklo z31.d, z31.s
+# CHECK-NEXT: 1 2 0.17 uunpklo z31.h, z31.b
+# CHECK-NEXT: 1 2 0.17 uunpklo z31.s, z31.h
+# CHECK-NEXT: 1 2 0.17 uxtb z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 uxtb z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 0.17 uxtb z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.17 uxtb z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 uxtb z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.17 uxtb z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 uxth z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 uxth z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.17 uxth z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.17 uxth z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.17 uxtw z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.17 uxtw z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 uzp1 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 uzp1 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 0.50 uzp1 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 0.50 uzp1 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.17 uzp1 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 uzp1 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 uzp1 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uzp1 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 uzp2 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 uzp2 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 0.50 uzp2 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 0.50 uzp2 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.17 uzp2 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 uzp2 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 uzp2 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 uzp2 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 1 0.50 whilege p15.b, w0, wzr
+# CHECK-NEXT: 1 1 0.50 whilege p15.b, wzr, w0
+# CHECK-NEXT: 1 1 0.50 whilege p15.b, x0, xzr
+# CHECK-NEXT: 1 1 0.50 whilege p15.b, xzr, x0
+# CHECK-NEXT: 1 1 0.50 whilege p15.d, w0, wzr
+# CHECK-NEXT: 1 1 0.50 whilege p15.d, x0, xzr
+# CHECK-NEXT: 1 1 0.50 whilege p15.h, w0, wzr
+# CHECK-NEXT: 1 1 0.50 whilege p15.h, x0, xzr
+# CHECK-NEXT: 1 1 0.50 whilege p15.s, w0, wzr
+# CHECK-NEXT: 1 1 0.50 whilege p15.s, x0, xzr
+# CHECK-NEXT: 1 2 0.50 whilerw p15.b, x30, x30
+# CHECK-NEXT: 1 2 0.50 whilerw p15.d, x30, x30
+# CHECK-NEXT: 1 2 0.50 whilerw p15.h, x30, x30
+# CHECK-NEXT: 1 2 0.50 whilerw p15.s, x30, x30
+# CHECK-NEXT: 1 2 0.50 whilewr p15.b, x30, x30
+# CHECK-NEXT: 1 2 0.50 whilewr p15.d, x30, x30
+# CHECK-NEXT: 1 2 0.50 whilewr p15.h, x30, x30
+# CHECK-NEXT: 1 2 0.50 whilewr p15.s, x30, x30
+# CHECK-NEXT: 1 2 1.00 * U wrffr p0.b
+# CHECK-NEXT: 1 2 1.00 * U wrffr p15.b
+# CHECK-NEXT: 1 2 0.17 xar z0.b, z0.b, z1.b, #1
+# CHECK-NEXT: 1 2 0.17 xar z0.d, z0.d, z1.d, #1
+# CHECK-NEXT: 1 2 0.17 xar z0.h, z0.h, z1.h, #1
+# CHECK-NEXT: 1 2 0.17 xar z0.s, z0.s, z1.s, #1
+# CHECK-NEXT: 1 2 0.17 xar z31.b, z31.b, z30.b, #8
+# CHECK-NEXT: 1 2 0.17 xar z31.d, z31.d, z30.d, #64
+# CHECK-NEXT: 1 2 0.17 xar z31.h, z31.h, z30.h, #16
+# CHECK-NEXT: 1 2 0.17 xar z31.s, z31.s, z30.s, #32
+# CHECK-NEXT: 1 2 0.50 zip1 p0.b, p0.b, p0.b
+# CHECK-NEXT: 1 2 0.50 zip1 p0.d, p0.d, p0.d
+# CHECK-NEXT: 1 2 0.50 zip1 p0.h, p0.h, p0.h
+# CHECK-NEXT: 1 2 0.50 zip1 p0.s, p0.s, p0.s
+# CHECK-NEXT: 1 2 0.50 zip1 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 zip1 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 0.50 zip1 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 0.50 zip1 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.17 zip1 z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 zip1 z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 zip1 z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 zip1 z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 zip1 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 zip1 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 zip1 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 zip1 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 zip2 p0.b, p0.b, p0.b
+# CHECK-NEXT: 1 2 0.50 zip2 p0.d, p0.d, p0.d
+# CHECK-NEXT: 1 2 0.50 zip2 p0.h, p0.h, p0.h
+# CHECK-NEXT: 1 2 0.50 zip2 p0.s, p0.s, p0.s
+# CHECK-NEXT: 1 2 0.50 zip2 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 zip2 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 0.50 zip2 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 0.50 zip2 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.17 zip2 z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.17 zip2 z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.17 zip2 z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.17 zip2 z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.17 zip2 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.17 zip2 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.17 zip2 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.17 zip2 z31.s, z31.s, z31.s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - C1UUnitB
+# CHECK-NEXT: [0.1] - C1UUnitB
+# CHECK-NEXT: [0.2] - C1UUnitB
+# CHECK-NEXT: [1] - C1UUnitCME
+# CHECK-NEXT: [2.0] - C1UUnitD
+# CHECK-NEXT: [2.1] - C1UUnitD
+# CHECK-NEXT: [3.0] - C1UUnitFlg
+# CHECK-NEXT: [3.1] - C1UUnitFlg
+# CHECK-NEXT: [3.2] - C1UUnitFlg
+# CHECK-NEXT: [3.3] - C1UUnitFlg
+# CHECK-NEXT: [4.0] - C1UUnitL23
+# CHECK-NEXT: [4.1] - C1UUnitL23
+# CHECK-NEXT: [5] - C1UUnitLS0
+# CHECK-NEXT: [6] - C1UUnitLS1
+# CHECK-NEXT: [7] - C1UUnitM0
+# CHECK-NEXT: [8] - C1UUnitM1
+# CHECK-NEXT: [9] - C1UUnitS0
+# CHECK-NEXT: [10] - C1UUnitS1
+# CHECK-NEXT: [11] - C1UUnitS2
+# CHECK-NEXT: [12] - C1UUnitS3
+# CHECK-NEXT: [13] - C1UUnitS4
+# CHECK-NEXT: [14] - C1UUnitS5
+# CHECK-NEXT: [15] - C1UUnitV0
+# CHECK-NEXT: [16] - C1UUnitV1
+# CHECK-NEXT: [17] - C1UUnitV2
+# CHECK-NEXT: [18] - C1UUnitV3
+# CHECK-NEXT: [19] - C1UUnitV4
+# CHECK-NEXT: [20] - C1UUnitV5
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
+# CHECK-NEXT: - - - - - - - - - - 174.75 174.75 373.75 373.75 347.00 256.00 14.50 14.50 14.50 14.50 14.50 14.50 1043.83 823.83 300.83 400.33 400.33 300.83
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [0.2] [1] [2.0] [2.1] [3.0] [3.1] [3.2] [3.3] [4.0] [4.1] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z0.b, p0/m, z0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z0.d, p0/m, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z0.h, p0/m, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z0.s, p0/m, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z31.b, p7/m, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z31.d, p7/m, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z31.h, p7/m, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 abs z31.s, p7/m, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 adclb z0.d, z1.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 adclb z0.s, z1.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 adclt z0.d, z1.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 adclt z0.s, z1.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.b, z0.b, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.b, z0.b, z0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.d, z0.d, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.d, z0.d, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.h, z0.h, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.h, z0.h, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.s, z0.s, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.s, z0.s, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z0.s, z1.s, z2.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.b, p5/m, z21.b, z10.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.b, z10.b, z21.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.d, p5/m, z21.d, z10.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.d, z10.d, z21.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.h, p5/m, z21.h, z10.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.h, z10.h, z21.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.s, p5/m, z21.s, z10.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z21.s, z10.s, z21.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z23.b, p3/m, z23.b, z13.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z23.b, z13.b, z8.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z23.d, p3/m, z23.d, z13.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z23.d, z13.d, z8.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z23.h, p3/m, z23.h, z13.h
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 add z23.s, p3/m, z23.s, z13.s
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmax z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmax z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnm z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxnmp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fmaxnmv d0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 fmaxnmv h0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fmaxnmv s0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmaxp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fmaxv d0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 fmaxv h0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fmaxv s0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmin z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnm z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminnmp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fminnmv d0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 fminnmv h0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fminnmv s0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp z0.h, p0/m, z0.h, z1.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp z29.s, p3/m, z29.s, z30.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fminp z31.d, p7/m, z31.d, z30.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 fminv d0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.67 0.67 0.67 0.67 0.67 0.67 fminv h0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 fminv s0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmla z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlalb z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlalb z29.s, z30.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlalb z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlalt z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlalt z29.s, z30.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlalt z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmls z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlslb z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlslb z29.s, z30.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlslb z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlslt z0.s, z1.h, z7.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlslt z29.s, z30.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmlslt z30.s, z31.h, z7.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.d, #-10.00000000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.d, #0.12500000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.d, p0/m, #-10.00000000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.d, p0/m, #0.12500000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.h, #-0.12500000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.h, p0/m, #-0.12500000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.s, #-0.12500000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmov z0.s, p0/m, #-0.12500000
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmsb z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmsb z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmsb z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.d, z0.d, z0.d[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.d, z1.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.h, z0.h, z0.h[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.h, z1.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.s, z0.s, z0.s[0]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z0.s, z1.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z31.d, p7/m, z31.d, #2.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z31.d, z31.d, z15.d[1]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z31.h, p7/m, z31.h, #2.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z31.h, z31.h, z7.h[7]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z31.s, p7/m, z31.s, #2.0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmul z31.s, z31.s, z7.s[3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fmulx z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg z31.d, p7/m, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg z31.h, p7/m, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fneg z31.s, p7/m, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fnmad z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fnmad z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fnmad z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 fnmla z0.d, p7/m, z1.d, z31.d
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+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z23.d, x13, #8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z23.h, #13, w8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z23.h, w13, #8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z23.s, #13, w8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z23.s, w13, #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.b, #-1, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.b, #-1, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.b, wzr, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.b, wzr, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.d, #-1, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.d, #-1, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.d, xzr, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.d, xzr, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.h, #-1, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.h, #-1, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.h, wzr, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.h, wzr, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.s, #-1, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.s, #-1, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.s, wzr, #-1
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.25 0.25 - 0.25 0.25 - index z31.s, wzr, wzr
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+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z0.d, x0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z0.h, w0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z0.s, w0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.b, b31
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.b, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.d, d31
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.d, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.h, h31
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.h, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.s, s31
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 insr z31.s, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lasta b0, p7, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lasta d0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lasta h0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lasta s0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lasta w0, p7, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lasta w0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lasta w0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lasta x0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lastb b0, p7, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lastb d0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lastb h0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - 1.00 - - - - lastb s0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lastb w0, p7, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lastb w0, p7, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lastb w0, p7, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.50 1.50 - - - - lastb x0, p7, z31.d
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z0.b }, p0/z, [sp, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z0.b }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z21.b }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z21.s }, p5/z, [x10, x21]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z23.d }, p3/z, [x13, x8]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z31.b }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1b { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1b { z5.h }, p3/z, [x17, x16]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1d { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1d { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1d { z23.d }, p3/z, [sp, x8, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1d { z23.d }, p3/z, [x13, x8, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1d { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1d { z31.d }, p7/z, [z31.d, #248]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z21.s }, p5/z, [x10, x21, lsl #1]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1h { z31.s }, p7/z, [sp, #-1, mul vl]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1h { z31.s }, p7/z, [z31.s, #62]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rb { z31.b }, p7/z, [sp, #63]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rb { z31.d }, p7/z, [sp, #63]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rb { z31.h }, p7/z, [sp, #63]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rb { z31.s }, p7/z, [sp, #63]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rd { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rd { z31.d }, p7/z, [sp, #504]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rh { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rh { z31.d }, p7/z, [sp, #126]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rh { z31.h }, p7/z, [sp, #126]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rh { z31.s }, p7/z, [sp, #126]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqb { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqb { z0.b }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqb { z21.b }, p5/z, [x10, #112]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqb { z23.b }, p3/z, [x13, #-128]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqd { z23.d }, p3/z, [x13, #-128]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqd { z23.d }, p3/z, [x13, #112]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqh { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqh { z23.h }, p3/z, [x13, #-128]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqh { z23.h }, p3/z, [x13, #112]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqh { z31.h }, p7/z, [sp, #-16]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqw { z23.s }, p3/z, [x13, #-128]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqw { z23.s }, p3/z, [x13, #112]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rqw { z31.s }, p7/z, [sp, #-16]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsb { z31.d }, p7/z, [sp, #63]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsb { z31.h }, p7/z, [sp, #63]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsb { z31.s }, p7/z, [sp, #63]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsh { z31.d }, p7/z, [sp, #126]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsh { z31.s }, p7/z, [sp, #126]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rsw { z31.d }, p7/z, [sp, #252]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rw { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rw { z31.d }, p7/z, [sp, #252]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1rw { z31.s }, p7/z, [sp, #252]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sb { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z0.h }, p0/z, [sp, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sb { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z21.s }, p5/z, [x10, x21]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sb { z23.d }, p3/z, [x13, x8]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sb { z31.d }, p7/z, [sp, z31.d]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sb { z31.s }, p7/z, [z31.s, #31]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sh { z0.d }, p0/z, [z0.d]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sh { z0.s }, p0/z, [z0.s]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sh { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sh { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sh { z31.s }, p7/z, [z31.s, #62]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sw { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sw { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sw { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1sw { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z21.s }, p5/z, [sp, x21, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z21.s }, p5/z, [x10, x21, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z23.d }, p3/z, [x13, x8, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ld1w { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ld1w { z31.s }, p7/z, [z31.s, #124]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2b { z0.b, z1.b }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2b { z0.b, z1.b }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2b { z5.b, z6.b }, p3/z, [x17, x16]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2d { z0.d, z1.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2h { z0.h, z1.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2w { z0.s, z1.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 0.50 0.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.33 0.33 0.33 0.33 0.33 0.33 ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3b { z0.b - z2.b }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3b { z0.b - z2.b }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3b { z5.b - z7.b }, p3/z, [x17, x16]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3d { z0.d - z2.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3h { z0.h - z2.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3w { z0.s - z2.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.75 0.75 0.75 0.75 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.50 0.50 0.50 0.50 0.50 0.50 ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4b { z0.b - z3.b }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4b { z0.b - z3.b }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4b { z5.b - z8.b }, p3/z, [x17, x16]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4d { z0.d - z3.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4h { z0.h - z3.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4w { z0.s - z3.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - 1.33 1.33 1.33 1.33 1.33 1.33 ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 1.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.33 1.33 1.33 1.33 1.33 1.33 ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z0.d }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z0.s }, p0/z, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z31.b }, p7/z, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z31.d }, p7/z, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z31.h }, p7/z, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z31.s }, p7/z, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1b { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z31.d }, p7/z, [sp]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1d { z31.d }, p7/z, [z31.d, #248]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1h { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - 0.50 0.50 - - - - ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1b { z0.s }, p0/z, [x0]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1d { z0.d }, p0/z, [x0]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1h { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]
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+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - ldnf1sh { z0.d }, p0/z, [x0]
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+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 1.50 1.50 - - - - st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]
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+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4b { z0.b - z3.b }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.00 2.00 - - - - st4b { z5.b - z8.b }, p3, [x17, x16]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.00 2.00 - - - - st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4d { z0.d - z3.d }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.00 2.00 - - - - st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.00 2.00 - - - - st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4h { z0.h - z3.h }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.00 2.00 - - - - st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.00 2.00 - - - - st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4w { z0.s - z3.s }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 - - - - - - - - 2.00 2.00 - - - - st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 2.00 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 2.00 2.00 - - - - st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1b { z0.b }, p0, [x0, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1b { z0.b }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1b { z0.d }, p0, [z1.d]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1b { z0.s }, p0, [z1.s]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1b { z21.b }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1b { z23.b }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1b { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1b { z31.d }, p7, [z31.d]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1b { z31.s }, p7, [z31.s, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1b { z31.s }, p7, [z31.s]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1d { z0.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1d { z0.d }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1d { z0.d }, p0, [z1.d]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1d { z21.d }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1d { z23.d }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1d { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1d { z31.d }, p7, [z31.d]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1h { z0.d }, p0, [z1.d]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1h { z0.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1h { z0.h }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1h { z0.s }, p0, [z1.s]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1h { z21.h }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1h { z23.h }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1h { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1h { z31.d }, p7, [z31.d]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1h { z31.s }, p7, [z31.s, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1h { z31.s }, p7, [z31.s]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1w { z0.d }, p0, [z1.d]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1w { z0.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1w { z0.s }, p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1w { z0.s }, p0, [z1.s]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - stnt1w { z21.s }, p5, [x10, #7, mul vl]
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+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1w { z31.d }, p7, [z31.d, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 1.50 1.50 - - - - stnt1w { z31.d }, p7, [z31.d]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1w { z31.s }, p7, [z31.s, x0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.50 1.50 - - - - - - - - 3.00 3.00 - - - - stnt1w { z31.s }, p7, [z31.s]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - - str p0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - - str p15, [sp, #-256, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - - str p5, [x10, #255, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str z0, [x0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str z21, [x10, #-256, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - 0.50 0.50 - - - - str z31, [sp, #255, mul vl]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.b, z0.b, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.b, z0.b, z0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.d, z0.d, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.d, z0.d, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.h, z0.h, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.h, z0.h, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.s, z0.s, #0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z0.s, z0.s, #0, lsl #8
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 sub z21.b, p5/m, z21.b, z10.b
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uunpkhi z31.h, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uunpkhi z31.s, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uunpklo z31.d, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uunpklo z31.h, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uunpklo z31.s, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtb z0.d, p0/m, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtb z0.h, p0/m, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtb z0.s, p0/m, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtb z31.d, p7/m, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtb z31.h, p7/m, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtb z31.s, p7/m, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxth z0.d, p0/m, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxth z0.s, p0/m, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxth z31.d, p7/m, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxth z31.s, p7/m, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtw z0.d, p0/m, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uxtw z31.d, p7/m, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp1 p15.b, p15.b, p15.b
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp1 p15.d, p15.d, p15.d
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp1 p15.h, p15.h, p15.h
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp1 p15.s, p15.s, p15.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp1 z31.b, z31.b, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp1 z31.d, z31.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp1 z31.h, z31.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp1 z31.s, z31.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp2 p15.b, p15.b, p15.b
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp2 p15.d, p15.d, p15.d
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp2 p15.h, p15.h, p15.h
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - uzp2 p15.s, p15.s, p15.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp2 z31.b, z31.b, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp2 z31.d, z31.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp2 z31.h, z31.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 uzp2 z31.s, z31.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.b, w0, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.b, wzr, w0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.b, x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.b, xzr, x0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.d, w0, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.d, x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.h, w0, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.h, x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.s, w0, wzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilege p15.s, x0, xzr
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilerw p15.b, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilerw p15.d, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilerw p15.h, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilerw p15.s, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilewr p15.b, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilewr p15.d, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilewr p15.h, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - whilewr p15.s, x30, x30
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - - - - - - - wrffr p0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - - - - - - - - - wrffr p15.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z0.b, z0.b, z1.b, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z0.d, z0.d, z1.d, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z0.h, z0.h, z1.h, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z0.s, z0.s, z1.s, #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z31.b, z31.b, z30.b, #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z31.d, z31.d, z30.d, #64
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z31.h, z31.h, z30.h, #16
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 xar z31.s, z31.s, z30.s, #32
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p0.b, p0.b, p0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p0.d, p0.d, p0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p0.h, p0.h, p0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p0.s, p0.s, p0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p15.b, p15.b, p15.b
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p15.d, p15.d, p15.d
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p15.h, p15.h, p15.h
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip1 p15.s, p15.s, p15.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z0.b, z0.b, z0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z0.d, z0.d, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z0.h, z0.h, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z0.s, z0.s, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z31.b, z31.b, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z31.d, z31.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z31.h, z31.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip1 z31.s, z31.s, z31.s
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p0.b, p0.b, p0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p0.d, p0.d, p0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p0.h, p0.h, p0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p0.s, p0.s, p0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p15.b, p15.b, p15.b
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p15.d, p15.d, p15.d
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p15.h, p15.h, p15.h
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - - - - zip2 p15.s, p15.s, p15.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z0.b, z0.b, z0.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z0.d, z0.d, z0.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z0.h, z0.h, z0.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z0.s, z0.s, z0.s
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z31.b, z31.b, z31.b
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z31.d, z31.d, z31.d
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z31.h, z31.h, z31.h
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - 0.17 0.17 0.17 0.17 0.17 0.17 zip2 z31.s, z31.s, z31.s
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
new file mode 100644
index 0000000..cb831f9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
@@ -0,0 +1,5336 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra --instruction-info=0 --resource-pressure=0 --timeline --timeline-max-iterations=1 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN G01
+ld1 { v1.1d }, [x27], #8
+add x0, x27, 1
+ld1 { v1.2d }, [x27], #16
+add x0, x27, 1
+ld1 { v1.2s }, [x27], #8
+add x0, x27, 1
+ld1 { v1.4h }, [x27], #8
+add x0, x27, 1
+ld1 { v1.4s }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G02
+ld1 { v1.8b }, [x27], #8
+add x0, x27, 1
+ld1 { v1.8h }, [x27], #16
+add x0, x27, 1
+ld1 { v1.16b }, [x27], #16
+add x0, x27, 1
+ld1 { v1.1d }, [x27], x28
+add x0, x27, 1
+ld1 { v1.2d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G03
+ld1 { v1.2s }, [x27], x28
+add x0, x27, 1
+ld1 { v1.4h }, [x27], x28
+add x0, x27, 1
+ld1 { v1.4s }, [x27], x28
+add x0, x27, 1
+ld1 { v1.8b }, [x27], x28
+add x0, x27, 1
+ld1 { v1.8h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G04
+ld1 { v1.16b }, [x27], x28
+add x0, x27, 1
+ld1 { v1.1d, v2.1d }, [x27], #16
+add x0, x27, 1
+ld1 { v1.2d, v2.2d }, [x27], #32
+add x0, x27, 1
+ld1 { v1.2s, v2.2s }, [x27], #16
+add x0, x27, 1
+ld1 { v1.4h, v2.4h }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G05
+ld1 { v1.4s, v2.4s }, [x27], #32
+add x0, x27, 1
+ld1 { v1.8b, v2.8b }, [x27], #16
+add x0, x27, 1
+ld1 { v1.8h, v2.8h }, [x27], #32
+add x0, x27, 1
+ld1 { v1.16b, v2.16b }, [x27], #32
+add x0, x27, 1
+ld1 { v1.1d, v2.1d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G06
+ld1 { v1.2d, v2.2d }, [x27], x28
+add x0, x27, 1
+ld1 { v1.2s, v2.2s }, [x27], x28
+add x0, x27, 1
+ld1 { v1.4h, v2.4h }, [x27], x28
+add x0, x27, 1
+ld1 { v1.4s, v2.4s }, [x27], x28
+add x0, x27, 1
+ld1 { v1.8b, v2.8b }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G07
+ld1 { v1.8h, v2.8h }, [x27], x28
+add x0, x27, 1
+ld1 { v1.16b, v2.16b }, [x27], x28
+add x0, x27, 1
+ld1 { v1.1d, v2.1d, v3.1d }, [x27], #24
+add x0, x27, 1
+ld1 { v1.2d, v2.2d, v3.2d }, [x27], #48
+add x0, x27, 1
+ld1 { v1.2s, v2.2s, v3.2s }, [x27], #24
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G08
+ld1 { v1.4h, v2.4h, v3.4h }, [x27], #24
+add x0, x27, 1
+ld1 { v1.4s, v2.4s, v3.4s }, [x27], #48
+add x0, x27, 1
+ld1 { v1.8b, v2.8b, v3.8b }, [x27], #24
+add x0, x27, 1
+ld1 { v1.8h, v2.8h, v3.8h }, [x27], #48
+add x0, x27, 1
+ld1 { v1.16b, v2.16b, v3.16b }, [x27], #48
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G09
+ld1 { v1.1d, v2.1d, v3.1d }, [x27], x28
+add x0, x27, 1
+ld1 { v1.2d, v2.2d, v3.2d }, [x27], x28
+add x0, x27, 1
+ld1 { v1.2s, v2.2s, v3.2s }, [x27], x28
+add x0, x27, 1
+ld1 { v1.4h, v2.4h, v3.4h }, [x27], x28
+add x0, x27, 1
+ld1 { v1.4s, v2.4s, v3.4s }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G10
+ld1 { v1.8b, v2.8b, v3.8b }, [x27], x28
+add x0, x27, 1
+ld1 { v1.8h, v2.8h, v3.8h }, [x27], x28
+add x0, x27, 1
+ld1 { v1.16b, v2.16b, v3.16b }, [x27], x28
+add x0, x27, 1
+ld1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+add x0, x27, 1
+ld1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G11
+ld1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+add x0, x27, 1
+ld1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+add x0, x27, 1
+ld1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+add x0, x27, 1
+ld1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+add x0, x27, 1
+ld1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G12
+ld1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+add x0, x27, 1
+ld1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+add x0, x27, 1
+ld1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+add x0, x27, 1
+ld1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+add x0, x27, 1
+ld1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G13
+ld1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+add x0, x27, 1
+ld1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+add x0, x27, 1
+ld1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+add x0, x27, 1
+ld1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+add x0, x27, 1
+ld1 { v1.b }[0], [x27], #1
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G14
+ld1 { v1.b }[8], [x27], #1
+add x0, x27, 1
+ld1 { v1.b }[0], [x27], x28
+add x0, x27, 1
+ld1 { v1.b }[8], [x27], x28
+add x0, x27, 1
+ld1 { v1.h }[0], [x27], #2
+add x0, x27, 1
+ld1 { v1.h }[4], [x27], #2
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G15
+ld1 { v1.h }[0], [x27], x28
+add x0, x27, 1
+ld1 { v1.h }[4], [x27], x28
+add x0, x27, 1
+ld1 { v1.s }[0], [x27], #4
+add x0, x27, 1
+ld1 { v1.s }[0], [x27], x28
+add x0, x27, 1
+ld1 { v1.d }[0], [x27], #8
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G16
+ld1 { v1.d }[0], [x27], x28
+add x0, x27, 1
+ld1r { v1.1d }, [x27], #8
+add x0, x27, 1
+ld1r { v1.2d }, [x27], #8
+add x0, x27, 1
+ld1r { v1.2s }, [x27], #4
+add x0, x27, 1
+ld1r { v1.4h }, [x27], #2
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G17
+ld1r { v1.4s }, [x27], #4
+add x0, x27, 1
+ld1r { v1.8b }, [x27], #1
+add x0, x27, 1
+ld1r { v1.8h }, [x27], #2
+add x0, x27, 1
+ld1r { v1.16b }, [x27], #1
+add x0, x27, 1
+ld1r { v1.1d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G18
+ld1r { v1.2d }, [x27], x28
+add x0, x27, 1
+ld1r { v1.2s }, [x27], x28
+add x0, x27, 1
+ld1r { v1.4h }, [x27], x28
+add x0, x27, 1
+ld1r { v1.4s }, [x27], x28
+add x0, x27, 1
+ld1r { v1.8b }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G19
+ld1r { v1.8h }, [x27], x28
+add x0, x27, 1
+ld1r { v1.16b }, [x27], x28
+add x0, x27, 1
+ld2 { v1.2d, v2.2d }, [x27], #32
+add x0, x27, 1
+ld2 { v1.2s, v2.2s }, [x27], #16
+add x0, x27, 1
+ld2 { v1.4h, v2.4h }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G20
+ld2 { v1.4s, v2.4s }, [x27], #32
+add x0, x27, 1
+ld2 { v1.8b, v2.8b }, [x27], #16
+add x0, x27, 1
+ld2 { v1.8h, v2.8h }, [x27], #32
+add x0, x27, 1
+ld2 { v1.16b, v2.16b }, [x27], #32
+add x0, x27, 1
+ld2 { v1.2d, v2.2d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G21
+ld2 { v1.2s, v2.2s }, [x27], x28
+add x0, x27, 1
+ld2 { v1.4h, v2.4h }, [x27], x28
+add x0, x27, 1
+ld2 { v1.4s, v2.4s }, [x27], x28
+add x0, x27, 1
+ld2 { v1.8b, v2.8b }, [x27], x28
+add x0, x27, 1
+ld2 { v1.8h, v2.8h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G22
+ld2 { v1.16b, v2.16b }, [x27], x28
+add x0, x27, 1
+ld2 { v1.b, v2.b }[0], [x27], #2
+add x0, x27, 1
+ld2 { v1.b, v2.b }[8], [x27], #2
+add x0, x27, 1
+ld2 { v1.b, v2.b }[0], [x27], x28
+add x0, x27, 1
+ld2 { v1.b, v2.b }[8], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G23
+ld2 { v1.h, v2.h }[0], [x27], #4
+add x0, x27, 1
+ld2 { v1.h, v2.h }[4], [x27], #4
+add x0, x27, 1
+ld2 { v1.h, v2.h }[0], [x27], x28
+add x0, x27, 1
+ld2 { v1.h, v2.h }[4], [x27], x28
+add x0, x27, 1
+ld2 { v1.s, v2.s }[0], [x27], #8
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G24
+ld2 { v1.s, v2.s }[0], [x27], x28
+add x0, x27, 1
+ld2 { v1.d, v2.d }[0], [x27], #16
+add x0, x27, 1
+ld2 { v1.d, v2.d }[0], [x27], x28
+add x0, x27, 1
+ld2r { v1.1d, v2.1d }, [x27], #16
+add x0, x27, 1
+ld2r { v1.2d, v2.2d }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G25
+ld2r { v1.2s, v2.2s }, [x27], #8
+add x0, x27, 1
+ld2r { v1.4h, v2.4h }, [x27], #4
+add x0, x27, 1
+ld2r { v1.4s, v2.4s }, [x27], #8
+add x0, x27, 1
+ld2r { v1.8b, v2.8b }, [x27], #2
+add x0, x27, 1
+ld2r { v1.8h, v2.8h }, [x27], #4
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G26
+ld2r { v1.16b, v2.16b }, [x27], #2
+add x0, x27, 1
+ld2r { v1.1d, v2.1d }, [x27], x28
+add x0, x27, 1
+ld2r { v1.2d, v2.2d }, [x27], x28
+add x0, x27, 1
+ld2r { v1.2s, v2.2s }, [x27], x28
+add x0, x27, 1
+ld2r { v1.4h, v2.4h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G27
+ld2r { v1.4s, v2.4s }, [x27], x28
+add x0, x27, 1
+ld2r { v1.8b, v2.8b }, [x27], x28
+add x0, x27, 1
+ld2r { v1.8h, v2.8h }, [x27], x28
+add x0, x27, 1
+ld2r { v1.16b, v2.16b }, [x27], x28
+add x0, x27, 1
+ld3 { v1.2d, v2.2d, v3.2d }, [x27], #48
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G28
+ld3 { v1.2s, v2.2s, v3.2s }, [x27], #24
+add x0, x27, 1
+ld3 { v1.4h, v2.4h, v3.4h }, [x27], #24
+add x0, x27, 1
+ld3 { v1.4s, v2.4s, v3.4s }, [x27], #48
+add x0, x27, 1
+ld3 { v1.8b, v2.8b, v3.8b }, [x27], #24
+add x0, x27, 1
+ld3 { v1.8h, v2.8h, v3.8h }, [x27], #48
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G29
+ld3 { v1.16b, v2.16b, v3.16b }, [x27], #48
+add x0, x27, 1
+ld3 { v1.2d, v2.2d, v3.2d }, [x27], x28
+add x0, x27, 1
+ld3 { v1.2s, v2.2s, v3.2s }, [x27], x28
+add x0, x27, 1
+ld3 { v1.4h, v2.4h, v3.4h }, [x27], x28
+add x0, x27, 1
+ld3 { v1.4s, v2.4s, v3.4s }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G30
+ld3 { v1.8b, v2.8b, v3.8b }, [x27], x28
+add x0, x27, 1
+ld3 { v1.8h, v2.8h, v3.8h }, [x27], x28
+add x0, x27, 1
+ld3 { v1.16b, v2.16b, v3.16b }, [x27], x28
+add x0, x27, 1
+ld3 { v1.b, v2.b, v3.b }[0], [x27], #3
+add x0, x27, 1
+ld3 { v1.b, v2.b, v3.b }[8], [x27], #3
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G31
+ld3 { v1.b, v2.b, v3.b }[0], [x27], x28
+add x0, x27, 1
+ld3 { v1.b, v2.b, v3.b }[8], [x27], x28
+add x0, x27, 1
+ld3 { v1.h, v2.h, v3.h }[0], [x27], #6
+add x0, x27, 1
+ld3 { v1.h, v2.h, v3.h }[4], [x27], #6
+add x0, x27, 1
+ld3 { v1.h, v2.h, v3.h }[0], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G32
+ld3 { v1.h, v2.h, v3.h }[4], [x27], x28
+add x0, x27, 1
+ld3 { v1.s, v2.s, v3.s }[0], [x27], #12
+add x0, x27, 1
+ld3 { v1.s, v2.s, v3.s }[0], [x27], x28
+add x0, x27, 1
+ld3 { v1.d, v2.d, v3.d }[0], [x27], #24
+add x0, x27, 1
+ld3 { v1.d, v2.d, v3.d }[0], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G33
+ld3r { v1.1d, v2.1d, v3.1d }, [x27], #24
+add x0, x27, 1
+ld3r { v1.2d, v2.2d, v3.2d }, [x27], #24
+add x0, x27, 1
+ld3r { v1.2s, v2.2s, v3.2s }, [x27], #12
+add x0, x27, 1
+ld3r { v1.4h, v2.4h, v3.4h }, [x27], #6
+add x0, x27, 1
+ld3r { v1.4s, v2.4s, v3.4s }, [x27], #12
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G34
+ld3r { v1.8b, v2.8b, v3.8b }, [x27], #3
+add x0, x27, 1
+ld3r { v1.8h, v2.8h, v3.8h }, [x27], #6
+add x0, x27, 1
+ld3r { v1.16b, v2.16b, v3.16b }, [x27], #3
+add x0, x27, 1
+ld3r { v1.1d, v2.1d, v3.1d }, [x27], x28
+add x0, x27, 1
+ld3r { v1.2d, v2.2d, v3.2d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G35
+ld3r { v1.2s, v2.2s, v3.2s }, [x27], x28
+add x0, x27, 1
+ld3r { v1.4h, v2.4h, v3.4h }, [x27], x28
+add x0, x27, 1
+ld3r { v1.4s, v2.4s, v3.4s }, [x27], x28
+add x0, x27, 1
+ld3r { v1.8b, v2.8b, v3.8b }, [x27], x28
+add x0, x27, 1
+ld3r { v1.8h, v2.8h, v3.8h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G36
+ld3r { v1.16b, v2.16b, v3.16b }, [x27], x28
+add x0, x27, 1
+ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+add x0, x27, 1
+ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+add x0, x27, 1
+ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+add x0, x27, 1
+ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G37
+ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+add x0, x27, 1
+ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+add x0, x27, 1
+ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+add x0, x27, 1
+ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+add x0, x27, 1
+ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G38
+ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+add x0, x27, 1
+ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+add x0, x27, 1
+ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+add x0, x27, 1
+ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+add x0, x27, 1
+ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G39
+ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
+add x0, x27, 1
+ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
+add x0, x27, 1
+ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
+add x0, x27, 1
+ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
+add x0, x27, 1
+ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G40
+ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
+add x0, x27, 1
+ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
+add x0, x27, 1
+ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
+add x0, x27, 1
+ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
+add x0, x27, 1
+ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G41
+ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
+add x0, x27, 1
+ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
+add x0, x27, 1
+ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+add x0, x27, 1
+ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #32
+add x0, x27, 1
+ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G42
+ld4r { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #8
+add x0, x27, 1
+ld4r { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #16
+add x0, x27, 1
+ld4r { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #4
+add x0, x27, 1
+ld4r { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #8
+add x0, x27, 1
+ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #4
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G43
+ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+add x0, x27, 1
+ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+add x0, x27, 1
+ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+add x0, x27, 1
+ld4r { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+add x0, x27, 1
+ld4r { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G44
+ld4r { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+add x0, x27, 1
+ld4r { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+add x0, x27, 1
+ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+add x0, x27, 1
+ldp s1, s2, [x27], #248
+add x0, x27, 1
+ldp d1, d2, [x27], #496
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G45
+ldp q1, q2, [x27], #992
+add x0, x27, 1
+ldp s1, s2, [x27, #248]!
+add x0, x27, 1
+ldp d1, d2, [x27, #496]!
+add x0, x27, 1
+ldp q1, q2, [x27, #992]!
+add x0, x27, 1
+ldp w1, w2, [x27], #248
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G46
+ldp x1, x2, [x27], #496
+add x0, x27, 1
+ldp w1, w2, [x27, #248]!
+add x0, x27, 1
+ldp x1, x2, [x27, #496]!
+add x0, x27, 1
+ldpsw x1, x2, [x27], #248
+add x0, x27, 1
+ldpsw x1, x2, [x27, #248]!
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G47
+ldr b1, [x27], #254
+add x0, x27, 1
+ldr h1, [x27], #254
+add x0, x27, 1
+ldr s1, [x27], #254
+add x0, x27, 1
+ldr d1, [x27], #254
+add x0, x27, 1
+ldr q1, [x27], #254
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G48
+ldr b1, [x27, #254]!
+add x0, x27, 1
+ldr h1, [x27, #254]!
+add x0, x27, 1
+ldr s1, [x27, #254]!
+add x0, x27, 1
+ldr d1, [x27, #254]!
+add x0, x27, 1
+ldr q1, [x27, #254]!
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G49
+ldr w1, [x27], #254
+add x0, x27, 1
+ldr x1, [x27], #254
+add x0, x27, 1
+ldr w1, [x27, #254]!
+add x0, x27, 1
+ldr x1, [x27, #254]!
+add x0, x27, 1
+ldrb w1, [x27], #254
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G50
+ldrb w1, [x27, #254]!
+add x0, x27, 1
+ldrh w1, [x27], #254
+add x0, x27, 1
+ldrh w1, [x27, #254]!
+add x0, x27, 1
+ldrsb w1, [x27], #254
+add x0, x27, 1
+ldrsb x1, [x27], #254
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G51
+ldrsb w1, [x27, #254]!
+add x0, x27, 1
+ldrsb x1, [x27, #254]!
+add x0, x27, 1
+ldrsh w1, [x27], #254
+add x0, x27, 1
+ldrsh x1, [x27], #254
+add x0, x27, 1
+ldrsh w1, [x27, #254]!
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G52
+ldrsh x1, [x27, #254]!
+add x0, x27, 1
+ldrsw x1, [x27], #254
+add x0, x27, 1
+ldrsw x1, [x27, #254]!
+add x0, x27, 1
+st1 { v1.1d }, [x27], #8
+add x0, x27, 1
+st1 { v1.2d }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G53
+st1 { v1.2s }, [x27], #8
+add x0, x27, 1
+st1 { v1.4h }, [x27], #8
+add x0, x27, 1
+st1 { v1.4s }, [x27], #16
+add x0, x27, 1
+st1 { v1.8b }, [x27], #8
+add x0, x27, 1
+st1 { v1.8h }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G54
+st1 { v1.16b }, [x27], #16
+add x0, x27, 1
+st1 { v1.1d }, [x27], x28
+add x0, x27, 1
+st1 { v1.2d }, [x27], x28
+add x0, x27, 1
+st1 { v1.2s }, [x27], x28
+add x0, x27, 1
+st1 { v1.4h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G55
+st1 { v1.4s }, [x27], x28
+add x0, x27, 1
+st1 { v1.8b }, [x27], x28
+add x0, x27, 1
+st1 { v1.8h }, [x27], x28
+add x0, x27, 1
+st1 { v1.16b }, [x27], x28
+add x0, x27, 1
+st1 { v1.1d, v2.1d }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G56
+st1 { v1.2d, v2.2d }, [x27], #32
+add x0, x27, 1
+st1 { v1.2s, v2.2s }, [x27], #16
+add x0, x27, 1
+st1 { v1.4h, v2.4h }, [x27], #16
+add x0, x27, 1
+st1 { v1.4s, v2.4s }, [x27], #32
+add x0, x27, 1
+st1 { v1.8b, v2.8b }, [x27], #16
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G57
+st1 { v1.8h, v2.8h }, [x27], #32
+add x0, x27, 1
+st1 { v1.16b, v2.16b }, [x27], #32
+add x0, x27, 1
+st1 { v1.1d, v2.1d }, [x27], x28
+add x0, x27, 1
+st1 { v1.2d, v2.2d }, [x27], x28
+add x0, x27, 1
+st1 { v1.2s, v2.2s }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G58
+st1 { v1.4h, v2.4h }, [x27], x28
+add x0, x27, 1
+st1 { v1.4s, v2.4s }, [x27], x28
+add x0, x27, 1
+st1 { v1.8b, v2.8b }, [x27], x28
+add x0, x27, 1
+st1 { v1.8h, v2.8h }, [x27], x28
+add x0, x27, 1
+st1 { v1.16b, v2.16b }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G59
+st1 { v1.1d, v2.1d, v3.1d }, [x27], #24
+add x0, x27, 1
+st1 { v1.2d, v2.2d, v3.2d }, [x27], #48
+add x0, x27, 1
+st1 { v1.2s, v2.2s, v3.2s }, [x27], #24
+add x0, x27, 1
+st1 { v1.4h, v2.4h, v3.4h }, [x27], #24
+add x0, x27, 1
+st1 { v1.4s, v2.4s, v3.4s }, [x27], #48
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G60
+st1 { v1.8b, v2.8b, v3.8b }, [x27], #24
+add x0, x27, 1
+st1 { v1.8h, v2.8h, v3.8h }, [x27], #48
+add x0, x27, 1
+st1 { v1.16b, v2.16b, v3.16b }, [x27], #48
+add x0, x27, 1
+st1 { v1.1d, v2.1d, v3.1d }, [x27], x28
+add x0, x27, 1
+st1 { v1.2d, v2.2d, v3.2d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G61
+st1 { v1.2s, v2.2s, v3.2s }, [x27], x28
+add x0, x27, 1
+st1 { v1.4h, v2.4h, v3.4h }, [x27], x28
+add x0, x27, 1
+st1 { v1.4s, v2.4s, v3.4s }, [x27], x28
+add x0, x27, 1
+st1 { v1.8b, v2.8b, v3.8b }, [x27], x28
+add x0, x27, 1
+st1 { v1.8h, v2.8h, v3.8h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G62
+st1 { v1.16b, v2.16b, v3.16b }, [x27], x28
+add x0, x27, 1
+st1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+add x0, x27, 1
+st1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+add x0, x27, 1
+st1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+add x0, x27, 1
+st1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G63
+st1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+add x0, x27, 1
+st1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+add x0, x27, 1
+st1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+add x0, x27, 1
+st1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+add x0, x27, 1
+st1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G64
+st1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+add x0, x27, 1
+st1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+add x0, x27, 1
+st1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+add x0, x27, 1
+st1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+add x0, x27, 1
+st1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G65
+st1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+add x0, x27, 1
+st1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+add x0, x27, 1
+st1 { v1.b }[0], [x27], #1
+add x0, x27, 1
+st1 { v1.b }[8], [x27], #1
+add x0, x27, 1
+st1 { v1.b }[0], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G66
+st1 { v1.b }[8], [x27], x28
+add x0, x27, 1
+st1 { v1.h }[0], [x27], #2
+add x0, x27, 1
+st1 { v1.h }[4], [x27], #2
+add x0, x27, 1
+st1 { v1.h }[0], [x27], x28
+add x0, x27, 1
+st1 { v1.h }[4], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G67
+st1 { v1.s }[0], [x27], #4
+add x0, x27, 1
+st1 { v1.s }[0], [x27], x28
+add x0, x27, 1
+st1 { v1.d }[0], [x27], #8
+add x0, x27, 1
+st1 { v1.d }[0], [x27], x28
+add x0, x27, 1
+st2 { v1.2d, v2.2d }, [x27], #32
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G68
+st2 { v1.2s, v2.2s }, [x27], #16
+add x0, x27, 1
+st2 { v1.4h, v2.4h }, [x27], #16
+add x0, x27, 1
+st2 { v1.4s, v2.4s }, [x27], #32
+add x0, x27, 1
+st2 { v1.8b, v2.8b }, [x27], #16
+add x0, x27, 1
+st2 { v1.8h, v2.8h }, [x27], #32
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G69
+st2 { v1.16b, v2.16b }, [x27], #32
+add x0, x27, 1
+st2 { v1.2d, v2.2d }, [x27], x28
+add x0, x27, 1
+st2 { v1.2s, v2.2s }, [x27], x28
+add x0, x27, 1
+st2 { v1.4h, v2.4h }, [x27], x28
+add x0, x27, 1
+st2 { v1.4s, v2.4s }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G70
+st2 { v1.8b, v2.8b }, [x27], x28
+add x0, x27, 1
+st2 { v1.8h, v2.8h }, [x27], x28
+add x0, x27, 1
+st2 { v1.16b, v2.16b }, [x27], x28
+add x0, x27, 1
+st2 { v1.b, v2.b }[0], [x27], #2
+add x0, x27, 1
+st2 { v1.b, v2.b }[8], [x27], #2
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G71
+st2 { v1.b, v2.b }[0], [x27], x28
+add x0, x27, 1
+st2 { v1.b, v2.b }[8], [x27], x28
+add x0, x27, 1
+st2 { v1.h, v2.h }[0], [x27], #4
+add x0, x27, 1
+st2 { v1.h, v2.h }[4], [x27], #4
+add x0, x27, 1
+st2 { v1.h, v2.h }[0], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G72
+st2 { v1.h, v2.h }[4], [x27], x28
+add x0, x27, 1
+st2 { v1.s, v2.s }[0], [x27], #8
+add x0, x27, 1
+st2 { v1.s, v2.s }[0], [x27], x28
+add x0, x27, 1
+st2 { v1.d, v2.d }[0], [x27], #16
+add x0, x27, 1
+st2 { v1.d, v2.d }[0], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G73
+st2g x26, [x27], #4064
+add x0, x27, 1
+st2g x26, [x27, #4064]!
+add x0, x27, 1
+st3 { v1.2d, v2.2d, v3.2d }, [x27], #48
+add x0, x27, 1
+st3 { v1.2s, v2.2s, v3.2s }, [x27], #24
+add x0, x27, 1
+st3 { v1.4h, v2.4h, v3.4h }, [x27], #24
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G74
+st3 { v1.4s, v2.4s, v3.4s }, [x27], #48
+add x0, x27, 1
+st3 { v1.8b, v2.8b, v3.8b }, [x27], #24
+add x0, x27, 1
+st3 { v1.8h, v2.8h, v3.8h }, [x27], #48
+add x0, x27, 1
+st3 { v1.16b, v2.16b, v3.16b }, [x27], #48
+add x0, x27, 1
+st3 { v1.2d, v2.2d, v3.2d }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G75
+st3 { v1.2s, v2.2s, v3.2s }, [x27], x28
+add x0, x27, 1
+st3 { v1.4h, v2.4h, v3.4h }, [x27], x28
+add x0, x27, 1
+st3 { v1.4s, v2.4s, v3.4s }, [x27], x28
+add x0, x27, 1
+st3 { v1.8b, v2.8b, v3.8b }, [x27], x28
+add x0, x27, 1
+st3 { v1.8h, v2.8h, v3.8h }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G76
+st3 { v1.16b, v2.16b, v3.16b }, [x27], x28
+add x0, x27, 1
+st3 { v1.b, v2.b, v3.b }[0], [x27], #3
+add x0, x27, 1
+st3 { v1.b, v2.b, v3.b }[8], [x27], #3
+add x0, x27, 1
+st3 { v1.b, v2.b, v3.b }[0], [x27], x28
+add x0, x27, 1
+st3 { v1.b, v2.b, v3.b }[8], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G77
+st3 { v1.h, v2.h, v3.h }[0], [x27], #6
+add x0, x27, 1
+st3 { v1.h, v2.h, v3.h }[4], [x27], #6
+add x0, x27, 1
+st3 { v1.h, v2.h, v3.h }[0], [x27], x28
+add x0, x27, 1
+st3 { v1.h, v2.h, v3.h }[4], [x27], x28
+add x0, x27, 1
+st3 { v1.s, v2.s, v3.s }[0], [x27], #12
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G78
+st3 { v1.s, v2.s, v3.s }[0], [x27], x28
+add x0, x27, 1
+st3 { v1.d, v2.d, v3.d }[0], [x27], #24
+add x0, x27, 1
+st3 { v1.d, v2.d, v3.d }[0], [x27], x28
+add x0, x27, 1
+st4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+add x0, x27, 1
+st4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G79
+st4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+add x0, x27, 1
+st4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+add x0, x27, 1
+st4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+add x0, x27, 1
+st4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+add x0, x27, 1
+st4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G80
+st4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+add x0, x27, 1
+st4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+add x0, x27, 1
+st4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+add x0, x27, 1
+st4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+add x0, x27, 1
+st4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G81
+st4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+add x0, x27, 1
+st4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+add x0, x27, 1
+st4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
+add x0, x27, 1
+st4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
+add x0, x27, 1
+st4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G82
+st4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
+add x0, x27, 1
+st4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
+add x0, x27, 1
+st4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
+add x0, x27, 1
+st4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
+add x0, x27, 1
+st4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G83
+st4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
+add x0, x27, 1
+st4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
+add x0, x27, 1
+st4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
+add x0, x27, 1
+st4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
+add x0, x27, 1
+stg x26, [x27], #4064
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G84
+stg x26, [x27, #4064]!
+add x0, x27, 1
+stgp x1, x2, [x27], #992
+add x0, x27, 1
+stgp x1, x2, [x27, #992]!
+add x0, x27, 1
+stp s1, s2, [x27], #248
+add x0, x27, 1
+stp d1, d2, [x27], #496
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G85
+stp q1, q2, [x27], #992
+add x0, x27, 1
+stp s1, s2, [x27, #248]!
+add x0, x27, 1
+stp d1, d2, [x27, #496]!
+add x0, x27, 1
+stp q1, q2, [x27, #992]!
+add x0, x27, 1
+stp w1, w2, [x27], #248
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G86
+stp x1, x2, [x27], #496
+add x0, x27, 1
+stp w1, w2, [x27, #248]!
+add x0, x27, 1
+stp x1, x2, [x27, #496]!
+add x0, x27, 1
+str b1, [x27], #254
+add x0, x27, 1
+str h1, [x27], #254
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G87
+str s1, [x27], #254
+add x0, x27, 1
+str d1, [x27], #254
+add x0, x27, 1
+str q1, [x27], #254
+add x0, x27, 1
+str b1, [x27, #254]!
+add x0, x27, 1
+str h1, [x27, #254]!
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G88
+str s1, [x27, #254]!
+add x0, x27, 1
+str d1, [x27, #254]!
+add x0, x27, 1
+str q1, [x27, #254]!
+add x0, x27, 1
+str w1, [x27], #254
+add x0, x27, 1
+str x1, [x27], #254
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G89
+str w1, [x27, #254]!
+add x0, x27, 1
+str x1, [x27, #254]!
+add x0, x27, 1
+strb w1, [x27], #254
+add x0, x27, 1
+strb w1, [x27, #254]!
+add x0, x27, 1
+strh w1, [x27], #254
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G90
+strh w1, [x27, #254]!
+add x0, x27, 1
+stz2g x26, [x27], #4064
+add x0, x27, 1
+stz2g x26, [x27, #4064]!
+add x0, x27, 1
+stzg x26, [x27], #4064
+add x0, x27, 1
+stzg x26, [x27, #4064]!
+add x0, x27, 1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN G91
+ldr x1, [x27], #254
+add x0, x27, 1
+ldr x2, [x1], #254
+add x0, x27, 1
+# LLVM-MCA-END
+
+# CHECK: [0] Code Region - G01
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.1d }, [x27], #8
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.2d }, [x27], #16
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.2s }, [x27], #8
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.4h }, [x27], #8
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.4s }, [x27], #16
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.1d }, [x27], #8
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.2d }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.2s }, [x27], #8
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.4h }, [x27], #8
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.4s }, [x27], #16
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [1] Code Region - G02
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.8b }, [x27], #8
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.8h }, [x27], #16
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.16b }, [x27], #16
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.1d }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.2d }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.8b }, [x27], #8
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.8h }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.16b }, [x27], #16
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.1d }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.2d }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [2] Code Region - G03
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.2s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.4h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.4s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.8b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.8h }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.2s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.4h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.4s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.8b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.8h }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [3] Code Region - G04
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 2.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.16b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.16b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [4] Code Region - G05
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [5] Code Region - G06
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [6] Code Region - G07
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 3.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.1d, v2.1d, v3.1d }, [x27], #24
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.1d, v2.1d, v3.1d }, [x27], #24
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [7] Code Region - G08
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 3.8
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [8] Code Region - G09
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 3.8
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.1d, v2.1d, v3.1d }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.1d, v2.1d, v3.1d }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [9] Code Region - G10
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 509
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 4.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeER. ld1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+# CHECK-NEXT: [0,7] .D===eE-----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeER ld1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: [0,9] .D====eE-----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+# CHECK-NEXT: 7. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: 9. 1 5.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.2 <total>
+
+# CHECK: [10] Code Region - G11
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 509
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeER. . ld1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: [0,1] D=eE-----R. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeER . ld1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: [0,3] D==eE-----R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeER . ld1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: [0,5] D===eE-----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeER. ld1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: [0,7] .D===eE-----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeER ld1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: [0,9] .D====eE-----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: 3. 1 3.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: 5. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: 7. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: 9. 1 5.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.5 <total>
+
+# CHECK: [11] Code Region - G12
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 509
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeER. . ld1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: [0,1] D=eE-----R. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeER . ld1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE-----R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeER . ld1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE-----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeER. ld1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE-----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeER ld1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE-----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: 1. 1 2.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.5 <total>
+
+# CHECK: [12] Code Region - G13
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 1108
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 1.35
+# CHECK-NEXT: IPC: 0.90
+# CHECK-NEXT: Block RThroughput: 4.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345678
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeER. . . ld1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE-----R. . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeER . . ld1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE-----R . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeER . . ld1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE-----R . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeER . . ld1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE-----R . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=========eeeeeeER ld1 { v1.b }[0], [x27], #1
+# CHECK-NEXT: [0,9] .D==========eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 10.0 0.0 0.0 ld1 { v1.b }[0], [x27], #1
+# CHECK-NEXT: 9. 1 11.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 4.3 0.1 2.4 <total>
+
+# CHECK: [13] Code Region - G14
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 3003
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.50
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 012
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . . . . . ld1 { v1.b }[8], [x27], #1
+# CHECK-NEXT: [0,1] D=eE----R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D======eeeeeeER. . . . . ld1 { v1.b }[0], [x27], x28
+# CHECK-NEXT: [0,3] D=======eE----R. . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D============eeeeeeER . . . ld1 { v1.b }[8], [x27], x28
+# CHECK-NEXT: [0,5] D=============eE----R . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=================eeeeeeER . . ld1 { v1.h }[0], [x27], #2
+# CHECK-NEXT: [0,7] .D==================eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=======================eeeeeeER ld1 { v1.h }[4], [x27], #2
+# CHECK-NEXT: [0,9] .D========================eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.b }[8], [x27], #1
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 7.0 0.0 0.0 ld1 { v1.b }[0], [x27], x28
+# CHECK-NEXT: 3. 1 8.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 13.0 0.0 0.0 ld1 { v1.b }[8], [x27], x28
+# CHECK-NEXT: 5. 1 14.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 18.0 0.0 0.0 ld1 { v1.h }[0], [x27], #2
+# CHECK-NEXT: 7. 1 19.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 24.0 0.0 0.0 ld1 { v1.h }[4], [x27], #2
+# CHECK-NEXT: 9. 1 25.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 13.1 0.1 2.0 <total>
+
+# CHECK: [14] Code Region - G15
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 3003
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.50
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 012
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . . . . . ld1 { v1.h }[0], [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D======eeeeeeER. . . . . ld1 { v1.h }[4], [x27], x28
+# CHECK-NEXT: [0,3] D=======eE----R. . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D============eeeeeeER . . . ld1 { v1.s }[0], [x27], #4
+# CHECK-NEXT: [0,5] D=============eE----R . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=================eeeeeeER . . ld1 { v1.s }[0], [x27], x28
+# CHECK-NEXT: [0,7] .D==================eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=======================eeeeeeER ld1 { v1.d }[0], [x27], #8
+# CHECK-NEXT: [0,9] .D========================eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.h }[0], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 7.0 0.0 0.0 ld1 { v1.h }[4], [x27], x28
+# CHECK-NEXT: 3. 1 8.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 13.0 0.0 0.0 ld1 { v1.s }[0], [x27], #4
+# CHECK-NEXT: 5. 1 14.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 18.0 0.0 0.0 ld1 { v1.s }[0], [x27], x28
+# CHECK-NEXT: 7. 1 19.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 24.0 0.0 0.0 ld1 { v1.d }[0], [x27], #8
+# CHECK-NEXT: 9. 1 25.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 13.1 0.1 2.0 <total>
+
+# CHECK: [15] Code Region - G16
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 1.50
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1 { v1.d }[0], [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1r { v1.1d }, [x27], #8
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1r { v1.2d }, [x27], #8
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1r { v1.2s }, [x27], #4
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1r { v1.4h }, [x27], #2
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1 { v1.d }[0], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1r { v1.1d }, [x27], #8
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1r { v1.2d }, [x27], #8
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1r { v1.2s }, [x27], #4
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1r { v1.4h }, [x27], #2
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [16] Code Region - G17
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1r { v1.4s }, [x27], #4
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1r { v1.8b }, [x27], #1
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1r { v1.8h }, [x27], #2
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1r { v1.16b }, [x27], #1
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1r { v1.1d }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1r { v1.4s }, [x27], #4
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1r { v1.8b }, [x27], #1
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1r { v1.8h }, [x27], #2
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1r { v1.16b }, [x27], #1
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1r { v1.1d }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [17] Code Region - G18
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1r { v1.2d }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1r { v1.2s }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ld1r { v1.4h }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ld1r { v1.4s }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ld1r { v1.8b }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1r { v1.2d }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1r { v1.2s }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld1r { v1.4h }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld1r { v1.4s }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld1r { v1.8b }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [18] Code Region - G19
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ld1r { v1.8h }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ld1r { v1.16b }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld2 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld2 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld2 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld1r { v1.8h }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld1r { v1.16b }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld2 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld2 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld2 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.6 <total>
+
+# CHECK: [19] Code Region - G20
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 2.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld2 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld2 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld2 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld2 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld2 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld2 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld2 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld2 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld2 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [20] Code Region - G21
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 1.8
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld2 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld2 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld2 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld2 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld2 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld2 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld2 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld2 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld2 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [21] Code Region - G22
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 3310
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.45
+# CHECK-NEXT: IPC: 0.30
+# CHECK-NEXT: Block RThroughput: 1.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 012
+
+# CHECK: [0,0] DeeeeeeeeER . . . . . . . ld2 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D========eeeeeeeeER . . . . . . ld2 { v1.b, v2.b }[0], [x27], #2
+# CHECK-NEXT: [0,3] D=========eE------R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D================eeeeeeeeER . . . . ld2 { v1.b, v2.b }[8], [x27], #2
+# CHECK-NEXT: [0,5] D=================eE------R . . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=======================eeeeeeeeER. . . ld2 { v1.b, v2.b }[0], [x27], x28
+# CHECK-NEXT: [0,7] .D========================eE------R. . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===============================eeeeeeeeER ld2 { v1.b, v2.b }[8], [x27], x28
+# CHECK-NEXT: [0,9] .D================================eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 9.0 0.0 0.0 ld2 { v1.b, v2.b }[0], [x27], #2
+# CHECK-NEXT: 3. 1 10.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 17.0 0.0 0.0 ld2 { v1.b, v2.b }[8], [x27], #2
+# CHECK-NEXT: 5. 1 18.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 24.0 0.0 0.0 ld2 { v1.b, v2.b }[0], [x27], x28
+# CHECK-NEXT: 7. 1 25.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 32.0 0.0 0.0 ld2 { v1.b, v2.b }[8], [x27], x28
+# CHECK-NEXT: 9. 1 33.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 17.1 0.1 3.0 <total>
+
+# CHECK: [22] Code Region - G23
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 4003
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.37
+# CHECK-NEXT: IPC: 0.25
+# CHECK-NEXT: Block RThroughput: 1.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 012
+
+# CHECK: [0,0] DeeeeeeeeER . . . . . . . ld2 { v1.h, v2.h }[0], [x27], #4
+# CHECK-NEXT: [0,1] D=eE------R . . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D========eeeeeeeeER . . . . . . ld2 { v1.h, v2.h }[4], [x27], #4
+# CHECK-NEXT: [0,3] D=========eE------R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D================eeeeeeeeER . . . . ld2 { v1.h, v2.h }[0], [x27], x28
+# CHECK-NEXT: [0,5] D=================eE------R . . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=======================eeeeeeeeER. . . ld2 { v1.h, v2.h }[4], [x27], x28
+# CHECK-NEXT: [0,7] .D========================eE------R. . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===============================eeeeeeeeER ld2 { v1.s, v2.s }[0], [x27], #8
+# CHECK-NEXT: [0,9] .D================================eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2 { v1.h, v2.h }[0], [x27], #4
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 9.0 0.0 0.0 ld2 { v1.h, v2.h }[4], [x27], #4
+# CHECK-NEXT: 3. 1 10.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 17.0 0.0 0.0 ld2 { v1.h, v2.h }[0], [x27], x28
+# CHECK-NEXT: 5. 1 18.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 24.0 0.0 0.0 ld2 { v1.h, v2.h }[4], [x27], x28
+# CHECK-NEXT: 7. 1 25.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 32.0 0.0 0.0 ld2 { v1.s, v2.s }[0], [x27], #8
+# CHECK-NEXT: 9. 1 33.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 17.1 0.1 3.0 <total>
+
+# CHECK: [23] Code Region - G24
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 2603
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.58
+# CHECK-NEXT: IPC: 0.38
+# CHECK-NEXT: Block RThroughput: 1.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012345678
+
+# CHECK: [0,0] DeeeeeeeeER . . . . ld2 { v1.s, v2.s }[0], [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D========eeeeeeeeER . . . ld2 { v1.d, v2.d }[0], [x27], #16
+# CHECK-NEXT: [0,3] D=========eE------R . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D================eeeeeeeeER . ld2 { v1.d, v2.d }[0], [x27], x28
+# CHECK-NEXT: [0,5] D=================eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D================eeeeeeeeER. ld2r { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: [0,7] .D=================eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=================eeeeeeeeER ld2r { v1.2d, v2.2d }, [x27], #16
+# CHECK-NEXT: [0,9] .D==================eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2 { v1.s, v2.s }[0], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 9.0 0.0 0.0 ld2 { v1.d, v2.d }[0], [x27], #16
+# CHECK-NEXT: 3. 1 10.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 17.0 0.0 0.0 ld2 { v1.d, v2.d }[0], [x27], x28
+# CHECK-NEXT: 5. 1 18.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 17.0 0.0 0.0 ld2r { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: 7. 1 18.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 18.0 0.0 0.0 ld2r { v1.2d, v2.2d }, [x27], #16
+# CHECK-NEXT: 9. 1 19.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 12.9 0.1 3.0 <total>
+
+# CHECK: [24] Code Region - G25
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 1.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld2r { v1.2s, v2.2s }, [x27], #8
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld2r { v1.4h, v2.4h }, [x27], #4
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld2r { v1.4s, v2.4s }, [x27], #8
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld2r { v1.8b, v2.8b }, [x27], #2
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld2r { v1.8h, v2.8h }, [x27], #4
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2r { v1.2s, v2.2s }, [x27], #8
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld2r { v1.4h, v2.4h }, [x27], #4
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld2r { v1.4s, v2.4s }, [x27], #8
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld2r { v1.8b, v2.8b }, [x27], #2
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld2r { v1.8h, v2.8h }, [x27], #4
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [25] Code Region - G26
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 1.7
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld2r { v1.16b, v2.16b }, [x27], #2
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld2r { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld2r { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld2r { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld2r { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2r { v1.16b, v2.16b }, [x27], #2
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld2r { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld2r { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld2r { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld2r { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [26] Code Region - G27
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 511
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 1.8
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld2r { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld2r { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld2r { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER . ld2r { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeeER ld3 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: [0,9] .D====eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld2r { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld2r { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld2r { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld2r { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld3 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: 9. 1 5.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.1 <total>
+
+# CHECK: [27] Code Region - G28
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 511
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeeER . ld3 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: [0,1] D=eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeeER . ld3 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: [0,3] D==eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeeER . ld3 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: [0,5] D===eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeeER. ld3 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: [0,7] .D===eE-------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeeER ld3 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: [0,9] .D====eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: 1. 1 2.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld3 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: 3. 1 3.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld3 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: 5. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld3 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: 7. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld3 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: 9. 1 5.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.5 <total>
+
+# CHECK: [28] Code Region - G29
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 511
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 3.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeeER . ld3 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: [0,1] D=eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeeER . ld3 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeeER . ld3 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeeER. ld3 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE-------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeeER ld3 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: 1. 1 2.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld3 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld3 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld3 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld3 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.5 <total>
+
+# CHECK: [29] Code Region - G30
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 2111
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.71
+# CHECK-NEXT: IPC: 0.47
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 01
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeeeeeeeeeER . . . .. ld3 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE-------R . . . .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeeER . . . .. ld3 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE-------R . . . .. add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeeER . . . .. ld3 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE-------R . . . .. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==========eeeeeeeeeER . .. ld3 { v1.b, v2.b, v3.b }[0], [x27], #3
+# CHECK-NEXT: [0,7] .D===========eE-------R . .. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===================eeeeeeeeeER ld3 { v1.b, v2.b, v3.b }[8], [x27], #3
+# CHECK-NEXT: [0,9] .D====================eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld3 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld3 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 11.0 0.0 0.0 ld3 { v1.b, v2.b, v3.b }[0], [x27], #3
+# CHECK-NEXT: 7. 1 12.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 20.0 0.0 0.0 ld3 { v1.b, v2.b, v3.b }[8], [x27], #3
+# CHECK-NEXT: 9. 1 21.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 7.9 0.1 3.5 <total>
+
+# CHECK: [30] Code Region - G31
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 4503
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.22
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 01234567
+
+# CHECK: [0,0] DeeeeeeeeeER . . . . . . . . ld3 { v1.b, v2.b, v3.b }[0], [x27], x28
+# CHECK-NEXT: [0,1] D=eE-------R . . . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=========eeeeeeeeeER . . . . . . ld3 { v1.b, v2.b, v3.b }[8], [x27], x28
+# CHECK-NEXT: [0,3] D==========eE-------R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==================eeeeeeeeeER. . . . . ld3 { v1.h, v2.h, v3.h }[0], [x27], #6
+# CHECK-NEXT: [0,5] D===================eE-------R. . . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==========================eeeeeeeeeER . . . ld3 { v1.h, v2.h, v3.h }[4], [x27], #6
+# CHECK-NEXT: [0,7] .D===========================eE-------R . . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===================================eeeeeeeeeER ld3 { v1.h, v2.h, v3.h }[0], [x27], x28
+# CHECK-NEXT: [0,9] .D====================================eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3 { v1.b, v2.b, v3.b }[0], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 10.0 0.0 0.0 ld3 { v1.b, v2.b, v3.b }[8], [x27], x28
+# CHECK-NEXT: 3. 1 11.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 19.0 0.0 0.0 ld3 { v1.h, v2.h, v3.h }[0], [x27], #6
+# CHECK-NEXT: 5. 1 20.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 27.0 0.0 0.0 ld3 { v1.h, v2.h, v3.h }[4], [x27], #6
+# CHECK-NEXT: 7. 1 28.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 36.0 0.0 0.0 ld3 { v1.h, v2.h, v3.h }[0], [x27], x28
+# CHECK-NEXT: 9. 1 37.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 19.1 0.1 3.5 <total>
+
+# CHECK: [31] Code Region - G32
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 4503
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.22
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 01234567
+
+# CHECK: [0,0] DeeeeeeeeeER . . . . . . . . ld3 { v1.h, v2.h, v3.h }[4], [x27], x28
+# CHECK-NEXT: [0,1] D=eE-------R . . . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=========eeeeeeeeeER . . . . . . ld3 { v1.s, v2.s, v3.s }[0], [x27], #12
+# CHECK-NEXT: [0,3] D==========eE-------R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==================eeeeeeeeeER. . . . . ld3 { v1.s, v2.s, v3.s }[0], [x27], x28
+# CHECK-NEXT: [0,5] D===================eE-------R. . . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==========================eeeeeeeeeER . . . ld3 { v1.d, v2.d, v3.d }[0], [x27], #24
+# CHECK-NEXT: [0,7] .D===========================eE-------R . . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===================================eeeeeeeeeER ld3 { v1.d, v2.d, v3.d }[0], [x27], x28
+# CHECK-NEXT: [0,9] .D====================================eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3 { v1.h, v2.h, v3.h }[4], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 10.0 0.0 0.0 ld3 { v1.s, v2.s, v3.s }[0], [x27], #12
+# CHECK-NEXT: 3. 1 11.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 19.0 0.0 0.0 ld3 { v1.s, v2.s, v3.s }[0], [x27], x28
+# CHECK-NEXT: 5. 1 20.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 27.0 0.0 0.0 ld3 { v1.d, v2.d, v3.d }[0], [x27], #24
+# CHECK-NEXT: 7. 1 28.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 36.0 0.0 0.0 ld3 { v1.d, v2.d, v3.d }[0], [x27], x28
+# CHECK-NEXT: 9. 1 37.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 19.1 0.1 3.5 <total>
+
+# CHECK: [32] Code Region - G33
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld3r { v1.1d, v2.1d, v3.1d }, [x27], #24
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld3r { v1.2d, v2.2d, v3.2d }, [x27], #24
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld3r { v1.2s, v2.2s, v3.2s }, [x27], #12
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld3r { v1.4h, v2.4h, v3.4h }, [x27], #6
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld3r { v1.4s, v2.4s, v3.4s }, [x27], #12
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3r { v1.1d, v2.1d, v3.1d }, [x27], #24
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld3r { v1.2d, v2.2d, v3.2d }, [x27], #24
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld3r { v1.2s, v2.2s, v3.2s }, [x27], #12
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld3r { v1.4h, v2.4h, v3.4h }, [x27], #6
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld3r { v1.4s, v2.4s, v3.4s }, [x27], #12
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [33] Code Region - G34
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld3r { v1.8b, v2.8b, v3.8b }, [x27], #3
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld3r { v1.8h, v2.8h, v3.8h }, [x27], #6
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld3r { v1.16b, v2.16b, v3.16b }, [x27], #3
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld3r { v1.1d, v2.1d, v3.1d }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld3r { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3r { v1.8b, v2.8b, v3.8b }, [x27], #3
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld3r { v1.8h, v2.8h, v3.8h }, [x27], #6
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld3r { v1.16b, v2.16b, v3.16b }, [x27], #3
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld3r { v1.1d, v2.1d, v3.1d }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld3r { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [34] Code Region - G35
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld3r { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld3r { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld3r { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld3r { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld3r { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3r { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld3r { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld3r { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld3r { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld3r { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [35] Code Region - G36
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 511
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 4.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld3r { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeeER . ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: [0,3] D==eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER . ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: [0,7] .D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeeER ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: [0,9] .D====eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld3r { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: 3. 1 3.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: 9. 1 5.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.2 <total>
+
+# CHECK: [36] Code Region - G37
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 609
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.46
+# CHECK-NEXT: IPC: 1.64
+# CHECK-NEXT: Block RThroughput: 5.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeeER . ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: [0,3] D==eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeeER. ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: [0,5] D===eE-------R. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeeER ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE-------R add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: 3. 1 3.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: 5. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.3 <total>
+
+# CHECK: [37] Code Region - G38
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 577
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.60
+# CHECK-NEXT: IPC: 1.73
+# CHECK-NEXT: Block RThroughput: 5.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeeER . ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE-------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeeER. ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE-------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeeER ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE-------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 7.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.3 <total>
+
+# CHECK: [38] Code Region - G39
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 4003
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.37
+# CHECK-NEXT: IPC: 0.25
+# CHECK-NEXT: Block RThroughput: 3.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 012
+
+# CHECK: [0,0] DeeeeeeeeER . . . . . . . ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
+# CHECK-NEXT: [0,1] D=eE------R . . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D========eeeeeeeeER . . . . . . ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
+# CHECK-NEXT: [0,3] D=========eE------R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D================eeeeeeeeER . . . . ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
+# CHECK-NEXT: [0,5] D=================eE------R . . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=======================eeeeeeeeER. . . ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
+# CHECK-NEXT: [0,7] .D========================eE------R. . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===============================eeeeeeeeER ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
+# CHECK-NEXT: [0,9] .D================================eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 9.0 0.0 0.0 ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
+# CHECK-NEXT: 3. 1 10.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 17.0 0.0 0.0 ld4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
+# CHECK-NEXT: 5. 1 18.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 24.0 0.0 0.0 ld4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
+# CHECK-NEXT: 7. 1 25.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 32.0 0.0 0.0 ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
+# CHECK-NEXT: 9. 1 33.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 17.1 0.1 3.0 <total>
+
+# CHECK: [39] Code Region - G40
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 4003
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.37
+# CHECK-NEXT: IPC: 0.25
+# CHECK-NEXT: Block RThroughput: 3.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 012
+
+# CHECK: [0,0] DeeeeeeeeER . . . . . . . ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
+# CHECK-NEXT: [0,1] D=eE------R . . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D========eeeeeeeeER . . . . . . ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
+# CHECK-NEXT: [0,3] D=========eE------R . . . . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D================eeeeeeeeER . . . . ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
+# CHECK-NEXT: [0,5] D=================eE------R . . . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=======================eeeeeeeeER. . . ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
+# CHECK-NEXT: [0,7] .D========================eE------R. . . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===============================eeeeeeeeER ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
+# CHECK-NEXT: [0,9] .D================================eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 9.0 0.0 0.0 ld4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
+# CHECK-NEXT: 3. 1 10.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 17.0 0.0 0.0 ld4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
+# CHECK-NEXT: 5. 1 18.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 24.0 0.0 0.0 ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
+# CHECK-NEXT: 7. 1 25.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 32.0 0.0 0.0 ld4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
+# CHECK-NEXT: 9. 1 33.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 17.1 0.1 3.0 <total>
+
+# CHECK: [40] Code Region - G41
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 1903
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.79
+# CHECK-NEXT: IPC: 0.53
+# CHECK-NEXT: Block RThroughput: 3.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01
+
+# CHECK: [0,0] DeeeeeeeeER . .. ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
+# CHECK-NEXT: [0,1] D=eE------R . .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D========eeeeeeeeER .. ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
+# CHECK-NEXT: [0,3] D=========eE------R .. add x0, x27, #1
+# CHECK-NEXT: [0,4] D=========eeeeeeeeER.. ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+# CHECK-NEXT: [0,5] D==========eE------R.. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=========eeeeeeeeER. ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #32
+# CHECK-NEXT: [0,7] .D==========eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D==========eeeeeeeeER ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #16
+# CHECK-NEXT: [0,9] .D===========eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 9.0 0.0 0.0 ld4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
+# CHECK-NEXT: 3. 1 10.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 10.0 0.0 0.0 ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+# CHECK-NEXT: 5. 1 11.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 10.0 0.0 0.0 ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #32
+# CHECK-NEXT: 7. 1 11.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 11.0 0.0 0.0 ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #16
+# CHECK-NEXT: 9. 1 12.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 8.7 0.1 3.0 <total>
+
+# CHECK: [41] Code Region - G42
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 3.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld4r { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #8
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld4r { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #16
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld4r { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #4
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld4r { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #8
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #4
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4r { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #8
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld4r { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld4r { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #4
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld4r { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #8
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #4
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [42] Code Region - G43
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 510
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.94
+# CHECK-NEXT: IPC: 1.96
+# CHECK-NEXT: Block RThroughput: 3.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER . ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER . ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeeeER. ld4r { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeeeER ld4r { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4r { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld4r { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld4r { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ld4r { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ld4r { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 3.0 <total>
+
+# CHECK: [43] Code Region - G44
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1700
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 3.35
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 2.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeeER . ld4r { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE------R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeeER. ld4r { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE------R. add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeeeER ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE------R add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeE-R ldp s1, s2, [x27], #248
+# CHECK-NEXT: [0,7] .D===eE-----R add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ldp d1, d2, [x27], #496
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld4r { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ld4r { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 1.0 ldp s1, s2, [x27], #248
+# CHECK-NEXT: 7. 1 4.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ldp d1, d2, [x27], #496
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.8 <total>
+
+# CHECK: [44] Code Region - G45
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 507
+# CHECK-NEXT: Total uOps: 2000
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 3.94
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 2.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER .. ldp q1, q2, [x27], #992
+# CHECK-NEXT: [0,1] D=eE----R .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER.. ldp s1, s2, [x27, #248]!
+# CHECK-NEXT: [0,3] D==eE----R.. add x0, x27, #1
+# CHECK-NEXT: [0,4] .D=eeeeeeER. ldp d1, d2, [x27, #496]!
+# CHECK-NEXT: [0,5] .D==eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER ldp q1, q2, [x27, #992]!
+# CHECK-NEXT: [0,7] .D===eE----R add x0, x27, #1
+# CHECK-NEXT: [0,8] . D==eeeeE-R ldp w1, w2, [x27], #248
+# CHECK-NEXT: [0,9] . D===eE---R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldp q1, q2, [x27], #992
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldp s1, s2, [x27, #248]!
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 2.0 0.0 0.0 ldp d1, d2, [x27, #496]!
+# CHECK-NEXT: 5. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ldp q1, q2, [x27, #992]!
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 3.0 0.0 1.0 ldp w1, w2, [x27], #248
+# CHECK-NEXT: 9. 1 4.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 1 2.7 0.1 2.0 <total>
+
+# CHECK: [45] Code Region - G46
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 1107
+# CHECK-NEXT: Total uOps: 1600
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 1.45
+# CHECK-NEXT: IPC: 0.90
+# CHECK-NEXT: Block RThroughput: 2.3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234567
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . . . ldp x1, x2, [x27], #496
+# CHECK-NEXT: [0,1] D====eER . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D====eeeeER . . ldp w1, w2, [x27, #248]!
+# CHECK-NEXT: [0,3] D=====eE--R . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D=====eeeeER . . ldp x1, x2, [x27, #496]!
+# CHECK-NEXT: [0,5] D=========eER . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D========eeeeeER. ldpsw x1, x2, [x27], #248
+# CHECK-NEXT: [0,7] .D=========eE---R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=========eeeeeER ldpsw x1, x2, [x27, #248]!
+# CHECK-NEXT: [0,9] .D==========eE---R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldp x1, x2, [x27], #496
+# CHECK-NEXT: 1. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 5.0 0.0 0.0 ldp w1, w2, [x27, #248]!
+# CHECK-NEXT: 3. 1 6.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 6.0 0.0 0.0 ldp x1, x2, [x27, #496]!
+# CHECK-NEXT: 5. 1 10.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 9.0 0.0 0.0 ldpsw x1, x2, [x27], #248
+# CHECK-NEXT: 7. 1 10.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 10.0 0.0 0.0 ldpsw x1, x2, [x27, #248]!
+# CHECK-NEXT: 9. 1 11.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 1 7.3 0.1 0.8 <total>
+
+# CHECK: [46] Code Region - G47
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 1.9
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ldr b1, [x27], #254
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ldr h1, [x27], #254
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ldr s1, [x27], #254
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ldr d1, [x27], #254
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ldr q1, [x27], #254
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldr b1, [x27], #254
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldr h1, [x27], #254
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ldr s1, [x27], #254
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ldr d1, [x27], #254
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ldr q1, [x27], #254
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [47] Code Region - G48
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 1.9
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . ldr b1, [x27, #254]!
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . ldr h1, [x27, #254]!
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . ldr s1, [x27, #254]!
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. ldr d1, [x27, #254]!
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER ldr q1, [x27, #254]!
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldr b1, [x27, #254]!
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldr h1, [x27, #254]!
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ldr s1, [x27, #254]!
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ldr d1, [x27, #254]!
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ldr q1, [x27, #254]!
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [48] Code Region - G49
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . ldr w1, [x27], #254
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . ldr x1, [x27], #254
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . ldr w1, [x27, #254]!
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. ldr x1, [x27, #254]!
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER ldrb w1, [x27], #254
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldr w1, [x27], #254
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldr x1, [x27], #254
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ldr w1, [x27, #254]!
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ldr x1, [x27, #254]!
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ldrb w1, [x27], #254
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [49] Code Region - G50
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . ldrb w1, [x27, #254]!
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . ldrh w1, [x27], #254
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . ldrh w1, [x27, #254]!
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. ldrsb w1, [x27], #254
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER ldrsb x1, [x27], #254
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldrb w1, [x27, #254]!
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldrh w1, [x27], #254
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ldrh w1, [x27, #254]!
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ldrsb w1, [x27], #254
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ldrsb x1, [x27], #254
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [50] Code Region - G51
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . ldrsb w1, [x27, #254]!
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . ldrsb x1, [x27, #254]!
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . ldrsh w1, [x27], #254
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. ldrsh x1, [x27], #254
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER ldrsh w1, [x27, #254]!
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldrsb w1, [x27, #254]!
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldrsb x1, [x27, #254]!
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ldrsh w1, [x27], #254
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 ldrsh x1, [x27], #254
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 ldrsh w1, [x27, #254]!
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [51] Code Region - G52
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeeeER . ldrsh x1, [x27, #254]!
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER. ldrsw x1, [x27], #254
+# CHECK-NEXT: [0,3] D==eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER ldrsw x1, [x27, #254]!
+# CHECK-NEXT: [0,5] D===eE--R add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeE-R st1 { v1.1d }, [x27], #8
+# CHECK-NEXT: [0,7] .D===eE-R add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER st1 { v1.2d }, [x27], #16
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldrsh x1, [x27, #254]!
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 ldrsw x1, [x27], #254
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 ldrsw x1, [x27, #254]!
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 1.0 st1 { v1.1d }, [x27], #8
+# CHECK-NEXT: 7. 1 4.0 0.0 1.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.2d }, [x27], #16
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.8 <total>
+
+# CHECK: [52] Code Region - G53
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . st1 { v1.2s }, [x27], #8
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.4h }, [x27], #8
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.4s }, [x27], #16
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. st1 { v1.8b }, [x27], #8
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER st1 { v1.8h }, [x27], #16
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.2s }, [x27], #8
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.4h }, [x27], #8
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.4s }, [x27], #16
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.8b }, [x27], #8
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.8h }, [x27], #16
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [53] Code Region - G54
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . st1 { v1.16b }, [x27], #16
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.1d }, [x27], x28
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.2d }, [x27], x28
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. st1 { v1.2s }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER st1 { v1.4h }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.16b }, [x27], #16
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.1d }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.2d }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.2s }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.4h }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [54] Code Region - G55
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . st1 { v1.4s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.8b }, [x27], x28
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.8h }, [x27], x28
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. st1 { v1.16b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER st1 { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.4s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.8b }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.8h }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.16b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.1d, v2.1d }, [x27], #16
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [55] Code Region - G56
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 3.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . st1 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. st1 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER st1 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [56] Code Region - G57
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 4.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . st1 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. st1 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER st1 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.1d, v2.1d }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [57] Code Region - G58
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 4.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . st1 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. st1 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER st1 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [58] Code Region - G59
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 703
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.13
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 6.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . st1 { v1.1d, v2.1d, v3.1d }, [x27], #24
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===eeER. st1 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: [0,7] .D====eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D====eeER st1 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: [0,9] .D=====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.1d, v2.1d, v3.1d }, [x27], #24
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 1.0 0.0 st1 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: 7. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 0.0 0.0 st1 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: 9. 1 6.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.5 0.2 0.0 <total>
+
+# CHECK: [59] Code Region - G60
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 703
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.13
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 6.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . st1 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===eeER. st1 { v1.1d, v2.1d, v3.1d }, [x27], x28
+# CHECK-NEXT: [0,7] .D====eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D====eeER st1 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: [0,9] .D=====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 1.0 0.0 st1 { v1.1d, v2.1d, v3.1d }, [x27], x28
+# CHECK-NEXT: 7. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 0.0 0.0 st1 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: 9. 1 6.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.5 0.2 0.0 <total>
+
+# CHECK: [60] Code Region - G61
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 703
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.13
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 6.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . st1 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . st1 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER . st1 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D====eeER st1 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: [0,9] .D=====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 1.0 0.0 st1 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: 9. 1 6.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.3 0.2 0.0 <total>
+
+# CHECK: [61] Code Region - G62
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 704
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.13
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 6.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . st1 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D===eeER . st1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: [0,5] D====eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===eeER . st1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: [0,7] .D====eER . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=====eeER st1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: [0,9] .D======eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], #32
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 4.0 1.0 0.0 st1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: 5. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 st1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: 7. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 6.0 1.0 0.0 st1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: 9. 1 7.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.9 0.3 0.0 <total>
+
+# CHECK: [62] Code Region - G63
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 804
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 1.87
+# CHECK-NEXT: IPC: 1.24
+# CHECK-NEXT: Block RThroughput: 8.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. .. st1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: [0,1] D=eER. .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER .. st1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: [0,3] D==eER .. add x0, x27, #1
+# CHECK-NEXT: [0,4] D===eeER .. st1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: [0,5] D====eER .. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===eeER .. st1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: [0,7] .D====eER .. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D======eeER st1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+# CHECK-NEXT: [0,9] .D=======eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 4.0 1.0 0.0 st1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: 5. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 st1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: 7. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 7.0 2.0 0.0 st1 { v1.1d, v2.1d, v3.1d, v4.1d }, [x27], x28
+# CHECK-NEXT: 9. 1 8.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 4.1 0.4 0.0 <total>
+
+# CHECK: [63] Code Region - G64
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 703
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.13
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 7.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . st1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . st1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D===eeER . st1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: [0,5] D====eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===eeER. st1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: [0,7] .D====eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D====eeER st1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: [0,9] .D=====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 4.0 1.0 0.0 st1 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: 5. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 st1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: 7. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 0.0 0.0 st1 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: 9. 1 6.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.7 0.2 0.0 <total>
+
+# CHECK: [64] Code Region - G65
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 706
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.12
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 5.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . . st1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: [0,1] D=eER. . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . . st1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: [0,3] D==eER . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D====eeeeER . st1 { v1.b }[0], [x27], #1
+# CHECK-NEXT: [0,5] D=====eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D====eeeeER. st1 { v1.b }[8], [x27], #1
+# CHECK-NEXT: [0,7] .D=====eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=====eeeeER st1 { v1.b }[0], [x27], x28
+# CHECK-NEXT: [0,9] .D======eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 5.0 2.0 0.0 st1 { v1.b }[0], [x27], #1
+# CHECK-NEXT: 5. 1 6.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 5.0 0.0 0.0 st1 { v1.b }[8], [x27], #1
+# CHECK-NEXT: 7. 1 6.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 6.0 0.0 0.0 st1 { v1.b }[0], [x27], x28
+# CHECK-NEXT: 9. 1 7.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 4.3 0.3 0.6 <total>
+
+# CHECK: [65] Code Region - G66
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st1 { v1.b }[8], [x27], x28
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st1 { v1.h }[0], [x27], #2
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st1 { v1.h }[4], [x27], #2
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st1 { v1.h }[0], [x27], x28
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st1 { v1.h }[4], [x27], x28
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.b }[8], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.h }[0], [x27], #2
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.h }[4], [x27], #2
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.h }[0], [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st1 { v1.h }[4], [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [66] Code Region - G67
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st1 { v1.s }[0], [x27], #4
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st1 { v1.s }[0], [x27], x28
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st1 { v1.d }[0], [x27], #8
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st1 { v1.d }[0], [x27], x28
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st2 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st1 { v1.s }[0], [x27], #4
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st1 { v1.s }[0], [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st1 { v1.d }[0], [x27], #8
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st1 { v1.d }[0], [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st2 { v1.2d, v2.2d }, [x27], #32
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [67] Code Region - G68
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st2 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st2 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st2 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st2 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st2 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st2 { v1.2s, v2.2s }, [x27], #16
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st2 { v1.4h, v2.4h }, [x27], #16
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st2 { v1.4s, v2.4s }, [x27], #32
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st2 { v1.8b, v2.8b }, [x27], #16
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st2 { v1.8h, v2.8h }, [x27], #32
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [68] Code Region - G69
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st2 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st2 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st2 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st2 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st2 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st2 { v1.16b, v2.16b }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st2 { v1.2d, v2.2d }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st2 { v1.2s, v2.2s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st2 { v1.4h, v2.4h }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st2 { v1.4s, v2.4s }, [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [69] Code Region - G70
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 4.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st2 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st2 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st2 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st2 { v1.b, v2.b }[0], [x27], #2
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st2 { v1.b, v2.b }[8], [x27], #2
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st2 { v1.8b, v2.8b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st2 { v1.8h, v2.8h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st2 { v1.16b, v2.16b }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st2 { v1.b, v2.b }[0], [x27], #2
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st2 { v1.b, v2.b }[8], [x27], #2
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [70] Code Region - G71
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st2 { v1.b, v2.b }[0], [x27], x28
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st2 { v1.b, v2.b }[8], [x27], x28
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st2 { v1.h, v2.h }[0], [x27], #4
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st2 { v1.h, v2.h }[4], [x27], #4
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st2 { v1.h, v2.h }[0], [x27], x28
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st2 { v1.b, v2.b }[0], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st2 { v1.b, v2.b }[8], [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st2 { v1.h, v2.h }[0], [x27], #4
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st2 { v1.h, v2.h }[4], [x27], #4
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st2 { v1.h, v2.h }[0], [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [71] Code Region - G72
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st2 { v1.h, v2.h }[4], [x27], x28
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st2 { v1.s, v2.s }[0], [x27], #8
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st2 { v1.s, v2.s }[0], [x27], x28
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st2 { v1.d, v2.d }[0], [x27], #16
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st2 { v1.d, v2.d }[0], [x27], x28
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st2 { v1.h, v2.h }[4], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st2 { v1.s, v2.s }[0], [x27], #8
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st2 { v1.s, v2.s }[0], [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st2 { v1.d, v2.d }[0], [x27], #16
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st2 { v1.d, v2.d }[0], [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [72] Code Region - G73
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 606
+# CHECK-NEXT: Total uOps: 1300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.15
+# CHECK-NEXT: IPC: 1.65
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeER . .. st2g x26, [x27], #4064
+# CHECK-NEXT: [0,1] D=eER. .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eER. .. st2g x26, [x27, #4064]!
+# CHECK-NEXT: [0,3] D==eER .. add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeER.. st3 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: [0,5] D===eE---R.. add x0, x27, #1
+# CHECK-NEXT: [0,6] D===eeeeER.. st3 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: [0,7] D====eE--R.. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D====eeeeER st3 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: [0,9] .D=====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st2g x26, [x27], #4064
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st2g x26, [x27, #4064]!
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st3 { v1.2d, v2.2d, v3.2d }, [x27], #48
+# CHECK-NEXT: 5. 1 4.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 st3 { v1.2s, v2.2s, v3.2s }, [x27], #24
+# CHECK-NEXT: 7. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 1.0 0.0 st3 { v1.4h, v2.4h, v3.4h }, [x27], #24
+# CHECK-NEXT: 9. 1 6.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.5 0.2 0.7 <total>
+
+# CHECK: [73] Code Region - G74
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 906
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 1.66
+# CHECK-NEXT: IPC: 1.10
+# CHECK-NEXT: Block RThroughput: 9.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01234
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeER . . st3 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: [0,1] D=eE---R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . . st3 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: [0,3] D==eE--R . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D===eeeeeER . st3 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: [0,5] D====eE---R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===eeeeeER . st3 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: [0,7] .D====eE---R . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D======eeeeeER st3 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: [0,9] .D=======eE---R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st3 { v1.4s, v2.4s, v3.4s }, [x27], #48
+# CHECK-NEXT: 1. 1 2.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st3 { v1.8b, v2.8b, v3.8b }, [x27], #24
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 4.0 1.0 0.0 st3 { v1.8h, v2.8h, v3.8h }, [x27], #48
+# CHECK-NEXT: 5. 1 5.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 st3 { v1.16b, v2.16b, v3.16b }, [x27], #48
+# CHECK-NEXT: 7. 1 5.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 7.0 2.0 0.0 st3 { v1.2d, v2.2d, v3.2d }, [x27], x28
+# CHECK-NEXT: 9. 1 8.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 1 4.1 0.4 1.4 <total>
+
+# CHECK: [74] Code Region - G75
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 706
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.12
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 7.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . . st3 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE--R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . . st3 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE--R . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeER. . st3 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: [0,5] D===eE---R. . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. . st3 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: [0,7] .D===eE--R. . add x0, x27, #1
+# CHECK-NEXT: [0,8] .D====eeeeeER st3 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: [0,9] .D=====eE---R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st3 { v1.2s, v2.2s, v3.2s }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st3 { v1.4h, v2.4h, v3.4h }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st3 { v1.4s, v2.4s, v3.4s }, [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st3 { v1.8b, v2.8b, v3.8b }, [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 1.0 0.0 st3 { v1.8h, v2.8h, v3.8h }, [x27], x28
+# CHECK-NEXT: 9. 1 6.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.3 0.2 1.2 <total>
+
+# CHECK: [75] Code Region - G76
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 606
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.48
+# CHECK-NEXT: IPC: 1.65
+# CHECK-NEXT: Block RThroughput: 6.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeER .. st3 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE---R .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER .. st3 { v1.b, v2.b, v3.b }[0], [x27], #3
+# CHECK-NEXT: [0,3] D==eE--R .. add x0, x27, #1
+# CHECK-NEXT: [0,4] D===eeeeER.. st3 { v1.b, v2.b, v3.b }[8], [x27], #3
+# CHECK-NEXT: [0,5] D====eE--R.. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===eeeeER. st3 { v1.b, v2.b, v3.b }[0], [x27], x28
+# CHECK-NEXT: [0,7] .D====eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D====eeeeER st3 { v1.b, v2.b, v3.b }[8], [x27], x28
+# CHECK-NEXT: [0,9] .D=====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st3 { v1.16b, v2.16b, v3.16b }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st3 { v1.b, v2.b, v3.b }[0], [x27], #3
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 4.0 1.0 0.0 st3 { v1.b, v2.b, v3.b }[8], [x27], #3
+# CHECK-NEXT: 5. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 st3 { v1.b, v2.b, v3.b }[0], [x27], x28
+# CHECK-NEXT: 7. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 0.0 0.0 st3 { v1.b, v2.b, v3.b }[8], [x27], x28
+# CHECK-NEXT: 9. 1 6.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.7 0.2 1.1 <total>
+
+# CHECK: [76] Code Region - G77
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 506
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.96
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . st3 { v1.h, v2.h, v3.h }[0], [x27], #6
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . st3 { v1.h, v2.h, v3.h }[4], [x27], #6
+# CHECK-NEXT: [0,3] D==eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . st3 { v1.h, v2.h, v3.h }[0], [x27], x28
+# CHECK-NEXT: [0,5] D===eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeER. st3 { v1.h, v2.h, v3.h }[4], [x27], x28
+# CHECK-NEXT: [0,7] .D===eE--R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeER st3 { v1.s, v2.s, v3.s }[0], [x27], #12
+# CHECK-NEXT: [0,9] .D====eE--R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st3 { v1.h, v2.h, v3.h }[0], [x27], #6
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st3 { v1.h, v2.h, v3.h }[4], [x27], #6
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st3 { v1.h, v2.h, v3.h }[0], [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st3 { v1.h, v2.h, v3.h }[4], [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st3 { v1.s, v2.s, v3.s }[0], [x27], #12
+# CHECK-NEXT: 9. 1 5.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.0 <total>
+
+# CHECK: [77] Code Region - G78
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 1003
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 1.50
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 10.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . . st3 { v1.s, v2.s, v3.s }[0], [x27], x28
+# CHECK-NEXT: [0,1] D=eE--R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeER . . st3 { v1.d, v2.d, v3.d }[0], [x27], #24
+# CHECK-NEXT: [0,3] D==eE--R . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeER . . st3 { v1.d, v2.d, v3.d }[0], [x27], x28
+# CHECK-NEXT: [0,5] D===eE--R . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. st4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER st4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st3 { v1.s, v2.s, v3.s }[0], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st3 { v1.d, v2.d, v3.d }[0], [x27], #24
+# CHECK-NEXT: 3. 1 3.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st3 { v1.d, v2.d, v3.d }[0], [x27], x28
+# CHECK-NEXT: 5. 1 4.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], #64
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 1.4 <total>
+
+# CHECK: [78] Code Region - G79
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 2399
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.63
+# CHECK-NEXT: IPC: 0.42
+# CHECK-NEXT: Block RThroughput: 24.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeeeER . . . . st4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: [0,1] D=eE----R . . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeER . . . st4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: [0,3] D==eE-----R . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D======eeeeeeER. . . st4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: [0,5] D=======eE----R. . . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D===========eeeeeeeER. st4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: [0,7] .D============eE-----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D============eeeeeeeER st4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: [0,9] .D=============eE-----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], #32
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], #64
+# CHECK-NEXT: 3. 1 3.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 7.0 4.0 0.0 st4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], #32
+# CHECK-NEXT: 5. 1 8.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 12.0 5.0 0.0 st4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], #64
+# CHECK-NEXT: 7. 1 13.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 13.0 0.0 0.0 st4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
+# CHECK-NEXT: 9. 1 14.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 1 7.5 1.0 2.3 <total>
+
+# CHECK: [79] Code Region - G80
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 1903
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.79
+# CHECK-NEXT: IPC: 0.53
+# CHECK-NEXT: Block RThroughput: 19.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 01
+
+# CHECK: [0,0] DeeeeeeER . . .. st4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . .. st4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R. . .. add x0, x27, #1
+# CHECK-NEXT: [0,4] D=======eeeeeeER .. st4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: [0,5] D========eE----R .. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D=======eeeeeeeER .. st4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: [0,7] .D========eE-----R .. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D============eeeeeeER st4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: [0,9] .D=============eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st4 { v1.2d, v2.2d, v3.2d, v4.2d }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st4 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 8.0 5.0 0.0 st4 { v1.4h, v2.4h, v3.4h, v4.4h }, [x27], x28
+# CHECK-NEXT: 5. 1 9.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 8.0 0.0 0.0 st4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
+# CHECK-NEXT: 7. 1 9.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 13.0 4.0 0.0 st4 { v1.8b, v2.8b, v3.8b, v4.8b }, [x27], x28
+# CHECK-NEXT: 9. 1 14.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 6.9 1.0 2.1 <total>
+
+# CHECK: [80] Code Region - G81
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 1508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.66
+# CHECK-NEXT: Block RThroughput: 13.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DeeeeeeeER. . . . st4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: [0,1] D=eE-----R. . . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeeER . . . st4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: [0,3] D==eE-----R . . . add x0, x27, #1
+# CHECK-NEXT: [0,4] D============eeeeeeER . st4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
+# CHECK-NEXT: [0,5] D=============eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D============eeeeeeER. st4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
+# CHECK-NEXT: [0,7] .D=============eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=============eeeeeeER st4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
+# CHECK-NEXT: [0,9] .D==============eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st4 { v1.8h, v2.8h, v3.8h, v4.8h }, [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st4 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 5.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 13.0 10.0 0.0 st4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], #4
+# CHECK-NEXT: 5. 1 14.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 13.0 0.0 0.0 st4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], #4
+# CHECK-NEXT: 7. 1 14.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 14.0 0.0 0.0 st4 { v1.b, v2.b, v3.b, v4.b }[0], [x27], x28
+# CHECK-NEXT: 9. 1 15.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 9.1 1.1 2.2 <total>
+
+# CHECK: [81] Code Region - G82
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 508
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.95
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER . . st4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
+# CHECK-NEXT: [0,1] D=eE----R . . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER. . st4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
+# CHECK-NEXT: [0,3] D==eE----R. . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER . st4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
+# CHECK-NEXT: [0,5] D===eE----R . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER. st4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
+# CHECK-NEXT: [0,7] .D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeeeeeER st4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
+# CHECK-NEXT: [0,9] .D====eE----R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st4 { v1.b, v2.b, v3.b, v4.b }[8], [x27], x28
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], #8
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], #8
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st4 { v1.h, v2.h, v3.h, v4.h }[0], [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 st4 { v1.h, v2.h, v3.h, v4.h }[4], [x27], x28
+# CHECK-NEXT: 9. 1 5.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.0 <total>
+
+# CHECK: [82] Code Region - G83
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 507
+# CHECK-NEXT: Total uOps: 1400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.76
+# CHECK-NEXT: IPC: 1.97
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 01
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER .. st4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
+# CHECK-NEXT: [0,1] D=eE----R .. add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeeeeeER.. st4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
+# CHECK-NEXT: [0,3] D==eE----R.. add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeeeeeER. st4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
+# CHECK-NEXT: [0,5] D===eE----R. add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeeeeeER st4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
+# CHECK-NEXT: [0,7] .D===eE----R add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eE----R stg x26, [x27], #4064
+# CHECK-NEXT: [0,9] .D====eE---R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 st4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], #16
+# CHECK-NEXT: 1. 1 2.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 st4 { v1.s, v2.s, v3.s, v4.s }[0], [x27], x28
+# CHECK-NEXT: 3. 1 3.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 st4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], #32
+# CHECK-NEXT: 5. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 st4 { v1.d, v2.d, v3.d, v4.d }[0], [x27], x28
+# CHECK-NEXT: 7. 1 4.0 0.0 4.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 4.0 stg x26, [x27], #4064
+# CHECK-NEXT: 9. 1 5.0 0.0 3.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 2.3 <total>
+
+# CHECK: [83] Code Region - G84
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1200
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.38
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeER . . stg x26, [x27, #4064]!
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eER. . stgp x1, x2, [x27], #992
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eER . stgp x1, x2, [x27, #992]!
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] D===eeER. stp s1, s2, [x27], #248
+# CHECK-NEXT: [0,7] D====eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER stp d1, d2, [x27], #496
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 stg x26, [x27, #4064]!
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 stgp x1, x2, [x27], #992
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 stgp x1, x2, [x27, #992]!
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 stp s1, s2, [x27], #248
+# CHECK-NEXT: 7. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 stp d1, d2, [x27], #496
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.3 0.1 0.0 <total>
+
+# CHECK: [84] Code Region - G85
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 704
+# CHECK-NEXT: Total uOps: 1300
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 1.85
+# CHECK-NEXT: IPC: 1.42
+# CHECK-NEXT: Block RThroughput: 3.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeER. . stp q1, q2, [x27], #992
+# CHECK-NEXT: [0,1] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,2] D==eeER . stp s1, s2, [x27, #248]!
+# CHECK-NEXT: [0,3] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D===eeER . stp d1, d2, [x27, #496]!
+# CHECK-NEXT: [0,5] D====eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] D====eeER . stp q1, q2, [x27, #992]!
+# CHECK-NEXT: [0,7] D======eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D=====eER. stp w1, w2, [x27], #248
+# CHECK-NEXT: [0,9] .D======eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 stp q1, q2, [x27], #992
+# CHECK-NEXT: 1. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 3.0 0.0 0.0 stp s1, s2, [x27, #248]!
+# CHECK-NEXT: 3. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 4.0 0.0 0.0 stp d1, d2, [x27, #496]!
+# CHECK-NEXT: 5. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 5.0 0.0 0.0 stp q1, q2, [x27, #992]!
+# CHECK-NEXT: 7. 1 7.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 6.0 0.0 0.0 stp w1, w2, [x27], #248
+# CHECK-NEXT: 9. 1 7.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 4.5 0.1 0.0 <total>
+
+# CHECK: [85] Code Region - G86
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeER . . stp x1, x2, [x27], #496
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eER. . stp w1, w2, [x27, #248]!
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eER . stp x1, x2, [x27, #496]!
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. str b1, [x27], #254
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER str h1, [x27], #254
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 stp x1, x2, [x27], #496
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 stp w1, w2, [x27, #248]!
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 stp x1, x2, [x27, #496]!
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 str b1, [x27], #254
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 str h1, [x27], #254
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [86] Code Region - G87
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . str s1, [x27], #254
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . str d1, [x27], #254
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . str q1, [x27], #254
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eeER. str b1, [x27, #254]!
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eeER str h1, [x27, #254]!
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 str s1, [x27], #254
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 str d1, [x27], #254
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 str q1, [x27], #254
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 str b1, [x27, #254]!
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 str h1, [x27, #254]!
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [87] Code Region - G88
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeER. . str s1, [x27, #254]!
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eeER . str d1, [x27, #254]!
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eeER . str q1, [x27, #254]!
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eER . str w1, [x27], #254
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eER. str x1, [x27], #254
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 str s1, [x27, #254]!
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 str d1, [x27, #254]!
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 str q1, [x27, #254]!
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 str w1, [x27], #254
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 str x1, [x27], #254
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [88] Code Region - G89
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1500
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.98
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeER . . str w1, [x27, #254]!
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eER. . str x1, [x27, #254]!
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eER . strb w1, [x27], #254
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] .D==eER . strb w1, [x27, #254]!
+# CHECK-NEXT: [0,7] .D===eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] .D===eER. strh w1, [x27], #254
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 str w1, [x27, #254]!
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 str x1, [x27, #254]!
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 strb w1, [x27], #254
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 strb w1, [x27, #254]!
+# CHECK-NEXT: 7. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 4.0 0.0 0.0 strh w1, [x27], #254
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.1 0.1 0.0 <total>
+
+# CHECK: [89] Code Region - G90
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1000
+# CHECK-NEXT: Total Cycles: 504
+# CHECK-NEXT: Total uOps: 1100
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 2.18
+# CHECK-NEXT: IPC: 1.98
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeER . . strh w1, [x27, #254]!
+# CHECK-NEXT: [0,1] D=eER. . add x0, x27, #1
+# CHECK-NEXT: [0,2] D=eER. . stz2g x26, [x27], #4064
+# CHECK-NEXT: [0,3] D==eER . add x0, x27, #1
+# CHECK-NEXT: [0,4] D==eER . stz2g x26, [x27, #4064]!
+# CHECK-NEXT: [0,5] D===eER . add x0, x27, #1
+# CHECK-NEXT: [0,6] D===eER . stzg x26, [x27], #4064
+# CHECK-NEXT: [0,7] D====eER. add x0, x27, #1
+# CHECK-NEXT: [0,8] D====eER. stzg x26, [x27, #4064]!
+# CHECK-NEXT: [0,9] .D====eER add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 strh w1, [x27, #254]!
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 stz2g x26, [x27], #4064
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 4. 1 3.0 0.0 0.0 stz2g x26, [x27, #4064]!
+# CHECK-NEXT: 5. 1 4.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 6. 1 4.0 0.0 0.0 stzg x26, [x27], #4064
+# CHECK-NEXT: 7. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 8. 1 5.0 0.0 0.0 stzg x26, [x27, #4064]!
+# CHECK-NEXT: 9. 1 5.0 0.0 0.0 add x0, x27, #1
+# CHECK-NEXT: 1 3.4 0.1 0.0 <total>
+
+# CHECK: [90] Code Region - G91
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 110
+# CHECK-NEXT: Total uOps: 600
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 5.45
+# CHECK-NEXT: IPC: 3.64
+# CHECK-NEXT: Block RThroughput: 0.6
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . ldr x1, [x27], #254
+# CHECK-NEXT: [0,1] D=eE--R . add x0, x27, #1
+# CHECK-NEXT: [0,2] D====eeeeER ldr x2, [x1], #254
+# CHECK-NEXT: [0,3] D=eE------R add x0, x27, #1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ldr x1, [x27], #254
+# CHECK-NEXT: 1. 1 2.0 0.0 2.0 add x0, x27, #1
+# CHECK-NEXT: 2. 1 5.0 0.0 0.0 ldr x2, [x1], #254
+# CHECK-NEXT: 3. 1 2.0 0.0 6.0 add x0, x27, #1
+# CHECK-NEXT: 1 2.5 0.3 2.0 <total>
diff --git a/llvm/test/tools/llvm-mca/AArch64/Inputs/flag-manipulation-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/flag-manipulation-instructions.s
new file mode 100644
index 0000000..bfeb780f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Inputs/flag-manipulation-instructions.s
@@ -0,0 +1,6 @@
+setf8 w1
+setf16 w1
+rmif x0, #0, #0
+cfinv
+axflag
+xaflag
