| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ |
| ; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR9 %s |
| ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ |
| ; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR8 %s |
| ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown \ |
| ; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR7 %s |
| |
| define <1 x i64> @setcc_v1i128(<1 x i128> %a) { |
| ; CHECK-PWR9-LABEL: setcc_v1i128: |
| ; CHECK-PWR9: # %bb.0: # %entry |
| ; CHECK-PWR9-NEXT: mfvsrld r3, vs34 |
| ; CHECK-PWR9-NEXT: cmpldi r3, 35708 |
| ; CHECK-PWR9-NEXT: mfvsrd r3, vs34 |
| ; CHECK-PWR9-NEXT: cmpdi cr1, r3, 0 |
| ; CHECK-PWR9-NEXT: li r3, 1 |
| ; CHECK-PWR9-NEXT: crnand 4*cr5+lt, 4*cr1+eq, lt |
| ; CHECK-PWR9-NEXT: isel r3, 0, r3, 4*cr5+lt |
| ; CHECK-PWR9-NEXT: blr |
| ; |
| ; CHECK-PWR8-LABEL: setcc_v1i128: |
| ; CHECK-PWR8: # %bb.0: # %entry |
| ; CHECK-PWR8-NEXT: mfvsrd r3, vs34 |
| ; CHECK-PWR8-NEXT: xxswapd vs0, vs34 |
| ; CHECK-PWR8-NEXT: cmpdi r3, 0 |
| ; CHECK-PWR8-NEXT: mffprd r3, f0 |
| ; CHECK-PWR8-NEXT: cmpldi cr1, r3, 35708 |
| ; CHECK-PWR8-NEXT: li r3, 1 |
| ; CHECK-PWR8-NEXT: crnand 4*cr5+lt, eq, 4*cr1+lt |
| ; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt |
| ; CHECK-PWR8-NEXT: blr |
| ; |
| ; CHECK-PWR7-LABEL: setcc_v1i128: |
| ; CHECK-PWR7: # %bb.0: # %entry |
| ; CHECK-PWR7-NEXT: li r5, 0 |
| ; CHECK-PWR7-NEXT: cntlzd r3, r3 |
| ; CHECK-PWR7-NEXT: ori r5, r5, 35708 |
| ; CHECK-PWR7-NEXT: rldicl r3, r3, 58, 63 |
| ; CHECK-PWR7-NEXT: subc r5, r4, r5 |
| ; CHECK-PWR7-NEXT: subfe r4, r4, r4 |
| ; CHECK-PWR7-NEXT: neg r4, r4 |
| ; CHECK-PWR7-NEXT: and r3, r3, r4 |
| ; CHECK-PWR7-NEXT: blr |
| entry: |
| %0 = icmp ult <1 x i128> %a, <i128 35708> |
| %1 = zext <1 x i1> %0 to <1 x i64> |
| ret <1 x i64> %1 |
| } |
| |
