llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV32ZBC

declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)

define i32 @clmul32(i32 %a, i32 %b) nounwind {
; RV32ZBC-LABEL: clmul32:
; RV32ZBC:       # %bb.0:
; RV32ZBC-NEXT:    clmul a0, a0, a1
; RV32ZBC-NEXT:    ret
  %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
 ret i32 %tmp
}

declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)

define i32 @clmul32h(i32 %a, i32 %b) nounwind {
; RV32ZBC-LABEL: clmul32h:
; RV32ZBC:       # %bb.0:
; RV32ZBC-NEXT:    clmulh a0, a0, a1
; RV32ZBC-NEXT:    ret
  %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
 ret i32 %tmp
}

declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)

define i32 @clmul32r(i32 %a, i32 %b) nounwind {
; RV32ZBC-LABEL: clmul32r:
; RV32ZBC:       # %bb.0:
; RV32ZBC-NEXT:    clmulr a0, a0, a1
; RV32ZBC-NEXT:    ret
  %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
 ret i32 %tmp
}