llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

  define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
  define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
  define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
  define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
  define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
  define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}

...
---
name:            load1_s8_to_zextLoad1_s32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
    ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
    ; MIPS32: RetRA implicit $v0
    %0:_(p0) = COPY $a0
    %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            load2_s16_to_zextLoad2_s32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
    ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
    ; MIPS32: RetRA implicit $v0
    %0:_(p0) = COPY $a0
    %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            load4_s32_to_zextLoad4_s64
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
    ; MIPS32: $v0 = COPY [[LOAD]](s32)
    ; MIPS32: $v1 = COPY [[C]](s32)
    ; MIPS32: RetRA implicit $v0, implicit $v1
    %0:_(p0) = COPY $a0
    %5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
    %6:_(s32) = G_CONSTANT i32 0
    %2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $v0 = COPY %3(s32)
    $v1 = COPY %4(s32)
    RetRA implicit $v0, implicit $v1

...
---
name:            load1_s8_to_sextLoad1_s32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
    ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
    ; MIPS32: RetRA implicit $v0
    %0:_(p0) = COPY $a0
    %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            load2_s16_to_sextLoad2_s32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
    ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
    ; MIPS32: RetRA implicit $v0
    %0:_(p0) = COPY $a0
    %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
    $v0 = COPY %2(s32)
    RetRA implicit $v0

...
---
name:            load4_s32_to_sextLoad4_s64
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
    ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
    ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
    ; MIPS32: $v0 = COPY [[LOAD]](s32)
    ; MIPS32: $v1 = COPY [[ASHR]](s32)
    ; MIPS32: RetRA implicit $v0, implicit $v1
    %0:_(p0) = COPY $a0
    %5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)
    %9:_(s32) = G_CONSTANT i32 31
    %10:_(s32) = G_CONSTANT i32 0
    %8:_(s32) = COPY %9(s32)
    %7:_(s32) = G_ASHR %5, %8(s32)
    %2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
    $v0 = COPY %3(s32)
    $v1 = COPY %4(s32)
    RetRA implicit $v0, implicit $v1

...