| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // Test host codegen. |
| // RUN: %clang_cc1 -DHAS_INT128 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -DHAS_INT128 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DHAS_INT128 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 |
| |
| // Test target codegen - host bc file has to be created first. |
| // RUN: %clang_cc1 -DHAS_INT128 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -DHAS_INT128 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK5 |
| // RUN: %clang_cc1 -DHAS_INT128 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -DHAS_INT128 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK7 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 |
| |
| // expected-no-diagnostics |
| #ifndef HEADER |
| #define HEADER |
| |
| |
| void mapWithPrivate() { |
| int x, y; |
| #pragma omp target teams private(x) map(x,y) private(y) |
| ; |
| } |
| |
| void mapWithFirstprivate() { |
| int x, y; |
| #pragma omp target teams firstprivate(x) map(x,y) firstprivate(y) |
| ; |
| } |
| |
| void mapWithReduction() { |
| int x, y; |
| #pragma omp target teams reduction(+:x) map(x,y) reduction(+:y) |
| ; |
| } |
| |
| void mapFrom() { |
| int x; |
| #pragma omp target teams firstprivate(x) map(from:x) |
| ; |
| } |
| |
| void mapTo() { |
| int x; |
| #pragma omp target teams firstprivate(x) map(to:x) |
| ; |
| } |
| |
| void mapAlloc() { |
| int x; |
| #pragma omp target teams firstprivate(x) map(alloc:x) |
| ; |
| } |
| |
| void mapArray() { |
| int x[77], y[88], z[99]; |
| #pragma omp target teams private(x) firstprivate(y) reduction(+:z) map(x,y,z) |
| ; |
| #pragma omp target teams private(x) firstprivate(y) reduction(+:z) map(to:x,y,z) |
| ; |
| } |
| |
| # if HAS_INT128 |
| void mapInt128() { |
| __int128 x, y, z; |
| #pragma omp target teams private(x) firstprivate(y) reduction(+:z) map(x,y,z) |
| ; |
| #pragma omp target teams private(x) firstprivate(y) reduction(+:z) map(from:x,y,z) |
| ; |
| } |
| # endif |
| #endif |
| // CHECK1-LABEL: define {{[^@]+}}@_Z14mapWithPrivatev |
| // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP8]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 2, ptr [[TMP9]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP17]], align 8 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP20]], align 4 |
| // CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27() #[[ATTR2:[0-9]+]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 |
| // CHECK1-SAME: () #[[ATTR1:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z19mapWithFirstprivatev |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP8]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 2, ptr [[TMP9]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP17]], align 8 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP20]], align 4 |
| // CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33(ptr [[X]], ptr [[Y]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 |
| // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[Y_CASTED]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP3]], i64 [[TMP5]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z16mapWithReductionv |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP8]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 2, ptr [[TMP9]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP17]], align 8 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP20]], align 4 |
| // CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39(ptr [[X]], ptr [[Y]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 |
| // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[Y2:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 0, ptr [[X1]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[Y2]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr [[X1]], ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr [[Y2]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 2, i64 16, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK1-NEXT: ] |
| // CHECK1: .omp.reduction.case1: |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP1]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.case2: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK1-NEXT: [[TMP14:%.*]] = atomicrmw add ptr [[TMP1]], i32 [[TMP13]] monotonic, align 4 |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.default: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func |
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 1 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i64 0, i64 1 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP11]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP9]], align 4 |
| // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] |
| // CHECK1-NEXT: store i32 [[ADD2]], ptr [[TMP11]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z7mapFromv |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 |
| // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 |
| // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45(ptr [[X]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 |
| // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP2]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z5mapTov |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 |
| // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 |
| // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51(ptr [[X]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 |
| // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP2]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z8mapAllocv |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 |
| // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 |
| // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57(ptr [[X]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 |
| // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP2]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z8mapArrayv |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK1-NEXT: [[Y:%.*]] = alloca [88 x i32], align 4 |
| // CHECK1-NEXT: [[Z:%.*]] = alloca [99 x i32], align 4 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP11]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP12]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.11, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP19]], align 8 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP20]], align 8 |
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 |
| // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP22]], align 4 |
| // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP23]], align 4 |
| // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63(ptr [[Y]], ptr [[Z]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP26]], align 8 |
| // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP27]], align 8 |
| // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 |
| // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP29]], align 8 |
| // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP30]], align 8 |
| // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8 |
| // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP32]], align 8 |
| // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP33]], align 8 |
| // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 2 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8 |
| // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP37]], align 4 |
| // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP38]], align 4 |
| // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP35]], ptr [[TMP39]], align 8 |
| // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 8 |
| // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.13, ptr [[TMP41]], align 8 |
| // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.14, ptr [[TMP42]], align 8 |
| // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP43]], align 8 |
| // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP44]], align 8 |
| // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP45]], align 8 |
| // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP46]], align 8 |
| // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4 |
| // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4 |
| // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP49]], align 4 |
| // CHECK1-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.region_id, ptr [[KERNEL_ARGS4]]) |
| // CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 |
| // CHECK1-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] |
| // CHECK1: omp_offload.failed5: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65(ptr [[Y]], ptr [[Z]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT6]] |
| // CHECK1: omp_offload.cont6: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 |
| // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK1-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK1-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i64 352, i1 false) |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK1: omp.arrayinit.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK1-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK1: omp.arrayinit.done: |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK1-NEXT: ] |
| // CHECK1: .omp.reduction.case1: |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done6: |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.case2: |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK1: omp.arraycpy.body8: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK1: omp.arraycpy.done14: |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.default: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func |
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done2: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 |
| // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK1-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK1-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i64 352, i1 false) |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK1: omp.arrayinit.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK1-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK1: omp.arrayinit.done: |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK1-NEXT: ] |
| // CHECK1: .omp.reduction.case1: |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done6: |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.case2: |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK1: omp.arraycpy.body8: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK1: omp.arraycpy.done14: |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.default: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func |
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 99 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done2: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z9mapInt128v |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[X:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[Y:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[Z:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [3 x ptr], align 8 |
| // CHECK1-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP11]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP12]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.15, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.16, ptr [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP19]], align 8 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP20]], align 8 |
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 |
| // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP22]], align 4 |
| // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP23]], align 4 |
| // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72(ptr [[Y]], ptr [[Z]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP26]], align 8 |
| // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[TMP27]], align 8 |
| // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 |
| // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP29]], align 8 |
| // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[TMP30]], align 8 |
| // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8 |
| // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP32]], align 8 |
| // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[X]], ptr [[TMP33]], align 8 |
| // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 2 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8 |
| // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP37]], align 4 |
| // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP38]], align 4 |
| // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP35]], ptr [[TMP39]], align 8 |
| // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 8 |
| // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.17, ptr [[TMP41]], align 8 |
| // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP42]], align 8 |
| // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP43]], align 8 |
| // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP44]], align 8 |
| // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP45]], align 8 |
| // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP46]], align 8 |
| // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4 |
| // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4 |
| // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP49]], align 4 |
| // CHECK1-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.region_id, ptr [[KERNEL_ARGS4]]) |
| // CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 |
| // CHECK1-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] |
| // CHECK1: omp_offload.failed5: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74(ptr [[Y]], ptr [[Z]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT6]] |
| // CHECK1: omp_offload.cont6: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 |
| // CHECK1-SAME: (ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y1:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[X:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[Z2:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 16 |
| // CHECK1-NEXT: store i128 [[TMP2]], ptr [[Y1]], align 16 |
| // CHECK1-NEXT: store i128 0, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK1-NEXT: ] |
| // CHECK1: .omp.reduction.case1: |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i128, ptr [[TMP1]], align 16 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: store i128 [[ADD]], ptr [[TMP1]], align 16 |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.case2: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: call void @__atomic_load(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], i32 noundef signext 0) |
| // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] |
| // CHECK1: atomic_cont: |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16 |
| // CHECK1-NEXT: store i128 [[TMP10]], ptr [[TMP]], align 16 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i128, ptr [[TMP]], align 16 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i128 [[TMP11]], [[TMP12]] |
| // CHECK1-NEXT: store i128 [[ADD4]], ptr [[ATOMIC_TEMP3]], align 16 |
| // CHECK1-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], ptr noundef [[ATOMIC_TEMP3]], i32 noundef signext 0, i32 noundef signext 0) |
| // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] |
| // CHECK1: atomic_exit: |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.default: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined.omp.reduction.reduction_func |
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP7]], align 16 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i128, ptr [[TMP5]], align 16 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP8]], [[TMP9]] |
| // CHECK1-NEXT: store i128 [[ADD]], ptr [[TMP7]], align 16 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 |
| // CHECK1-SAME: (ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[Y1:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[X:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[Z2:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i128, align 16 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 16 |
| // CHECK1-NEXT: store i128 [[TMP2]], ptr [[Y1]], align 16 |
| // CHECK1-NEXT: store i128 0, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK1-NEXT: ] |
| // CHECK1: .omp.reduction.case1: |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i128, ptr [[TMP1]], align 16 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: store i128 [[ADD]], ptr [[TMP1]], align 16 |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.case2: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: call void @__atomic_load(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], i32 noundef signext 0) |
| // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] |
| // CHECK1: atomic_cont: |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16 |
| // CHECK1-NEXT: store i128 [[TMP10]], ptr [[TMP]], align 16 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i128, ptr [[TMP]], align 16 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i128 [[TMP11]], [[TMP12]] |
| // CHECK1-NEXT: store i128 [[ADD4]], ptr [[ATOMIC_TEMP3]], align 16 |
| // CHECK1-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], ptr noundef [[ATOMIC_TEMP3]], i32 noundef signext 0, i32 noundef signext 0) |
| // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] |
| // CHECK1: atomic_exit: |
| // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK1: .omp.reduction.default: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined.omp.reduction.reduction_func |
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP7]], align 16 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i128, ptr [[TMP5]], align 16 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP8]], [[TMP9]] |
| // CHECK1-NEXT: store i128 [[ADD]], ptr [[TMP7]], align 16 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z14mapWithPrivatev |
| // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 2, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP17]], align 8 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP20]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27() #[[ATTR2:[0-9]+]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 |
| // CHECK3-SAME: () #[[ATTR1:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z19mapWithFirstprivatev |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 2, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP17]], align 8 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP20]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33(ptr [[X]], ptr [[Y]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[Y_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y_CASTED]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP3]], i32 [[TMP5]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z16mapWithReductionv |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 2, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP17]], align 8 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP20]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK3-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39(ptr [[X]], ptr [[Y]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[Y2:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[X1]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[Y2]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X1]], ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Y2]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 2, i32 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK3-NEXT: ] |
| // CHECK3: .omp.reduction.case1: |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK3: .omp.reduction.case2: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = atomicrmw add ptr [[TMP1]], i32 [[TMP13]] monotonic, align 4 |
| // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK3: .omp.reduction.default: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func |
| // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] |
| // CHECK3-NEXT: store i32 [[ADD2]], ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z7mapFromv |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.5, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP13]], align 8 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 |
| // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45(ptr [[X]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP2]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z5mapTov |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP13]], align 8 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 |
| // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51(ptr [[X]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP2]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z8mapAllocv |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP13]], align 8 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 |
| // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57(ptr [[X]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP2]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z8mapArrayv |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK3-NEXT: [[Y:%.*]] = alloca [88 x i32], align 4 |
| // CHECK3-NEXT: [[Z:%.*]] = alloca [99 x i32], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [3 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [3 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [3 x ptr], align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.11, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP16]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP19]], align 8 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP20]], align 8 |
| // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP22]], align 4 |
| // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP23]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63(ptr [[Y]], ptr [[Z]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP26]], align 4 |
| // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[TMP27]], align 4 |
| // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 |
| // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[TMP29]], align 4 |
| // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[TMP30]], align 4 |
| // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP31]], align 4 |
| // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP32]], align 4 |
| // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[X]], ptr [[TMP33]], align 4 |
| // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP34]], align 4 |
| // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP37]], align 4 |
| // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP38]], align 4 |
| // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP35]], ptr [[TMP39]], align 4 |
| // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 4 |
| // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.13, ptr [[TMP41]], align 4 |
| // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.14, ptr [[TMP42]], align 4 |
| // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP43]], align 4 |
| // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP44]], align 4 |
| // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP45]], align 8 |
| // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP46]], align 8 |
| // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4 |
| // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4 |
| // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP49]], align 4 |
| // CHECK3-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.region_id, ptr [[KERNEL_ARGS4]]) |
| // CHECK3-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 |
| // CHECK3-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] |
| // CHECK3: omp_offload.failed5: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65(ptr [[Y]], ptr [[Z]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]] |
| // CHECK3: omp_offload.cont6: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK3-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK3-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i32 352, i1 false) |
| // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK3: omp.arrayinit.body: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK3-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK3: omp.arrayinit.done: |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK3-NEXT: ] |
| // CHECK3: .omp.reduction.case1: |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK3: omp.arraycpy.body: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK3: omp.arraycpy.done6: |
| // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK3: .omp.reduction.case2: |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK3: omp.arraycpy.body8: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK3: omp.arraycpy.done14: |
| // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK3: .omp.reduction.default: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func |
| // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK3: omp.arraycpy.body: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK3: omp.arraycpy.done2: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK3-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK3-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i32 352, i1 false) |
| // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK3: omp.arrayinit.body: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK3-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK3: omp.arrayinit.done: |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK3-NEXT: ] |
| // CHECK3: .omp.reduction.case1: |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK3: omp.arraycpy.body: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK3: omp.arraycpy.done6: |
| // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK3: .omp.reduction.case2: |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK3: omp.arraycpy.body8: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK3: omp.arraycpy.done14: |
| // CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK3: .omp.reduction.default: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func |
| // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 99 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK3: omp.arraycpy.body: |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK3: omp.arraycpy.done2: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[Y_CASTED]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP3]], i64 [[TMP5]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: store i64 [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X1:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[Y2:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 8 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store i32 0, ptr [[X1]], align 4 |
| // CHECK5-NEXT: store i32 0, ptr [[Y2]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK5-NEXT: store ptr [[X1]], ptr [[TMP2]], align 8 |
| // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 |
| // CHECK5-NEXT: store ptr [[Y2]], ptr [[TMP3]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 2, i64 16, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK5-NEXT: ] |
| // CHECK5: .omp.reduction.case1: |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] |
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4 |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[TMP1]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.case2: |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK5-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK5-NEXT: [[TMP14:%.*]] = atomicrmw add ptr [[TMP1]], i32 [[TMP13]] monotonic, align 4 |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.default: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func |
| // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 1 |
| // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 |
| // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i64 0, i64 1 |
| // CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 |
| // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] |
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 |
| // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP11]], align 4 |
| // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP9]], align 4 |
| // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] |
| // CHECK5-NEXT: store i32 [[ADD2]], ptr [[TMP11]], align 4 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP2]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP2]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP2]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK5-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK5-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i64 352, i1 false) |
| // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK5: omp.arrayinit.body: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK5-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK5: omp.arrayinit.done: |
| // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK5-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK5-NEXT: ] |
| // CHECK5: .omp.reduction.case1: |
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK5: omp.arraycpy.body: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK5: omp.arraycpy.done6: |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.case2: |
| // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK5: omp.arraycpy.body8: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK5-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK5: omp.arraycpy.done14: |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.default: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func |
| // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK5: omp.arraycpy.body: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK5: omp.arraycpy.done2: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK5-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK5-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i64 352, i1 false) |
| // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK5: omp.arrayinit.body: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK5-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK5: omp.arrayinit.done: |
| // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK5-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK5-NEXT: ] |
| // CHECK5: .omp.reduction.case1: |
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK5: omp.arraycpy.body: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK5: omp.arraycpy.done6: |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.case2: |
| // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK5: omp.arraycpy.body8: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK5-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK5: omp.arraycpy.done14: |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.default: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func |
| // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 99 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK5: omp.arraycpy.body: |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK5: omp.arraycpy.done2: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y1:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[X:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[Z2:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK5-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 16 |
| // CHECK5-NEXT: store i128 [[TMP2]], ptr [[Y1]], align 16 |
| // CHECK5-NEXT: store i128 0, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK5-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK5-NEXT: ] |
| // CHECK5: .omp.reduction.case1: |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i128, ptr [[TMP1]], align 16 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP7]], [[TMP8]] |
| // CHECK5-NEXT: store i128 [[ADD]], ptr [[TMP1]], align 16 |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.case2: |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: call void @__atomic_load(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], i32 noundef signext 0) |
| // CHECK5-NEXT: br label [[ATOMIC_CONT:%.*]] |
| // CHECK5: atomic_cont: |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16 |
| // CHECK5-NEXT: store i128 [[TMP10]], ptr [[TMP]], align 16 |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i128, ptr [[TMP]], align 16 |
| // CHECK5-NEXT: [[TMP12:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i128 [[TMP11]], [[TMP12]] |
| // CHECK5-NEXT: store i128 [[ADD4]], ptr [[ATOMIC_TEMP3]], align 16 |
| // CHECK5-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], ptr noundef [[ATOMIC_TEMP3]], i32 noundef signext 0, i32 noundef signext 0) |
| // CHECK5-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] |
| // CHECK5: atomic_exit: |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.default: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined.omp.reduction.reduction_func |
| // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP7]], align 16 |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i128, ptr [[TMP5]], align 16 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP8]], [[TMP9]] |
| // CHECK5-NEXT: store i128 [[ADD]], ptr [[TMP7]], align 16 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 |
| // CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined |
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[Y1:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[X:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[Z2:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK5-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i128, align 16 |
| // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 16 |
| // CHECK5-NEXT: store i128 [[TMP2]], ptr [[Y1]], align 16 |
| // CHECK5-NEXT: store i128 0, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 |
| // CHECK5-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK5-NEXT: ] |
| // CHECK5: .omp.reduction.case1: |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i128, ptr [[TMP1]], align 16 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP7]], [[TMP8]] |
| // CHECK5-NEXT: store i128 [[ADD]], ptr [[TMP1]], align 16 |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.case2: |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: call void @__atomic_load(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], i32 noundef signext 0) |
| // CHECK5-NEXT: br label [[ATOMIC_CONT:%.*]] |
| // CHECK5: atomic_cont: |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16 |
| // CHECK5-NEXT: store i128 [[TMP10]], ptr [[TMP]], align 16 |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i128, ptr [[TMP]], align 16 |
| // CHECK5-NEXT: [[TMP12:%.*]] = load i128, ptr [[Z2]], align 16 |
| // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i128 [[TMP11]], [[TMP12]] |
| // CHECK5-NEXT: store i128 [[ADD4]], ptr [[ATOMIC_TEMP3]], align 16 |
| // CHECK5-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP]], ptr noundef [[ATOMIC_TEMP3]], i32 noundef signext 0, i32 noundef signext 0) |
| // CHECK5-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] |
| // CHECK5: atomic_exit: |
| // CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK5: .omp.reduction.default: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined.omp.reduction.reduction_func |
| // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 |
| // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 |
| // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP7]], align 16 |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i128, ptr [[TMP5]], align 16 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP8]], [[TMP9]] |
| // CHECK5-NEXT: store i128 [[ADD]], ptr [[TMP7]], align 16 |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: [[Y:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: [[Y_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK7-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4 |
| // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y_CASTED]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP3]], i32 [[TMP5]]) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: store i32 [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X1:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: [[Y2:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: store i32 0, ptr [[X1]], align 4 |
| // CHECK7-NEXT: store i32 0, ptr [[Y2]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 |
| // CHECK7-NEXT: store ptr [[X1]], ptr [[TMP2]], align 4 |
| // CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 1 |
| // CHECK7-NEXT: store ptr [[Y2]], ptr [[TMP3]], align 4 |
| // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK7-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 2, i32 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK7-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK7-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK7-NEXT: ] |
| // CHECK7: .omp.reduction.case1: |
| // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] |
| // CHECK7-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4 |
| // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK7-NEXT: store i32 [[ADD3]], ptr [[TMP1]], align 4 |
| // CHECK7-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK7: .omp.reduction.case2: |
| // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[X1]], align 4 |
| // CHECK7-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[Y2]], align 4 |
| // CHECK7-NEXT: [[TMP14:%.*]] = atomicrmw add ptr [[TMP1]], i32 [[TMP13]] monotonic, align 4 |
| // CHECK7-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK7: .omp.reduction.default: |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined.omp.reduction.reduction_func |
| // CHECK7-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 |
| // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 |
| // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 |
| // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 |
| // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i32 0, i32 1 |
| // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4 |
| // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP2]], i32 0, i32 1 |
| // CHECK7-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4 |
| // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4 |
| // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] |
| // CHECK7-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 |
| // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP11]], align 4 |
| // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP9]], align 4 |
| // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] |
| // CHECK7-NEXT: store i32 [[ADD2]], ptr [[TMP11]], align 4 |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP2]]) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP2]]) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP2]]) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4 |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK7-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK7-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK7-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i32 352, i1 false) |
| // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK7: omp.arrayinit.body: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK7-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK7: omp.arrayinit.done: |
| // CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 |
| // CHECK7-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 4 |
| // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK7-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK7-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK7-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK7-NEXT: ] |
| // CHECK7: .omp.reduction.case1: |
| // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK7: omp.arraycpy.body: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK7-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK7: omp.arraycpy.done6: |
| // CHECK7-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK7: .omp.reduction.case2: |
| // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK7: omp.arraycpy.body8: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK7-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK7: omp.arraycpy.done14: |
| // CHECK7-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK7: .omp.reduction.default: |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined.omp.reduction.reduction_func |
| // CHECK7-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 |
| // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 |
| // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 |
| // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 |
| // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK7: omp.arraycpy.body: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK7-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK7: omp.arraycpy.done2: |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 |
| // CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]]) |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined |
| // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[Y1:%.*]] = alloca [88 x i32], align 4 |
| // CHECK7-NEXT: [[X:%.*]] = alloca [77 x i32], align 4 |
| // CHECK7-NEXT: [[Z2:%.*]] = alloca [99 x i32], align 4 |
| // CHECK7-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4 |
| // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Y1]], ptr align 4 [[TMP0]], i32 352, i1 false) |
| // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [99 x i32], ptr [[Z2]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] |
| // CHECK7: omp.arrayinit.body: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] |
| // CHECK7-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] |
| // CHECK7: omp.arrayinit.done: |
| // CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 |
| // CHECK7-NEXT: store ptr [[Z2]], ptr [[TMP3]], align 4 |
| // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK7-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP5]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: switch i32 [[TMP6]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ |
| // CHECK7-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] |
| // CHECK7-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] |
| // CHECK7-NEXT: ] |
| // CHECK7: .omp.reduction.case1: |
| // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP7]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK7: omp.arraycpy.body: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST3:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] |
| // CHECK7-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST3]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE5:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP7]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK7: omp.arraycpy.done6: |
| // CHECK7-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK7: .omp.reduction.case2: |
| // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP1]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY7:%.*]] = icmp eq ptr [[TMP1]], [[TMP10]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY7]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY8:%.*]] |
| // CHECK7: omp.arraycpy.body8: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST9:%.*]] = phi ptr [ [[Z2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT12:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT11:%.*]], [[OMP_ARRAYCPY_BODY8]] ] |
| // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], align 4 |
| // CHECK7-NEXT: [[TMP12:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 [[TMP11]] monotonic, align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT12]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST9]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP10]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY8]] |
| // CHECK7: omp.arraycpy.done14: |
| // CHECK7-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP5]], ptr @.gomp_critical_user_.reduction.var) |
| // CHECK7-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] |
| // CHECK7: .omp.reduction.default: |
| // CHECK7-NEXT: ret void |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined.omp.reduction.reduction_func |
| // CHECK7-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 |
| // CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 |
| // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 |
| // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 |
| // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 |
| // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 99 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK7: omp.arraycpy.body: |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] |
| // CHECK7-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] |
| // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK7: omp.arraycpy.done2: |
| // CHECK7-NEXT: ret void |
| // |
