| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // expected-no-diagnostics |
| #ifndef HEADER |
| #define HEADER |
| |
| struct St { |
| int a, b; |
| St() : a(0), b(0) {} |
| St(const St &st) : a(st.a + st.b), b(0) {} |
| ~St() {} |
| }; |
| |
| volatile int g = 1212; |
| |
| template <class T> |
| struct S { |
| T f; |
| S(T a) : f(a + g) {} |
| S() : f(g) {} |
| S(const S &s, St t = St()) : f(s.f + t.a) {} |
| operator T() { return T(); } |
| ~S() {} |
| }; |
| |
| |
| template <typename T> |
| T tmain() { |
| S<T> test; |
| T t_var = T(); |
| T vec[] = {1, 2}; |
| S<T> s_arr[] = {1, 2}; |
| S<T> var(3); |
| #pragma omp parallel |
| #pragma omp single firstprivate(t_var, vec, s_arr, var) |
| { |
| vec[0] = t_var; |
| s_arr[0] = var; |
| } |
| return T(); |
| } |
| |
| S<float> test; |
| int t_var = 333; |
| int vec[] = {1, 2}; |
| S<float> s_arr[] = {1, 2}; |
| S<float> var(3); |
| |
| int main() { |
| static int sivar; |
| #ifdef LAMBDA |
| [&]() { |
| #pragma omp parallel |
| #pragma omp single firstprivate(g, sivar) |
| { |
| g = 1; |
| sivar = 17; |
| [&]() { |
| g = 2; |
| sivar = 31; |
| }(); |
| } |
| }(); |
| return 0; |
| #elif defined(BLOCKS) |
| ^{ |
| #pragma omp parallel |
| #pragma omp single firstprivate(g, sivar) |
| { |
| g = 1; |
| sivar = 37; |
| ^{ |
| g = 2; |
| sivar = 31; |
| }(); |
| } |
| }(); |
| return 0; |
| #else |
| #pragma omp single firstprivate(t_var, vec, s_arr, var, sivar) nowait |
| { |
| { |
| vec[0] = t_var; |
| s_arr[0] = var; |
| sivar = 41; |
| } |
| } |
| return tmain<int>(); |
| #endif |
| } |
| |
| |
| // firstprivate t_var(t_var) |
| |
| // firstprivate vec(vec) |
| |
| // firstprivate s_arr(s_arr) |
| |
| // firstprivate var(var) |
| |
| // firstprivate isvar |
| // CHEC: [[SIVAR_VAL:%.+]] = load i{{[0-9]+}}, iptr [[SIVAR]], |
| // CHEC: store i{{[0-9]+}} [[SIVAR_VAL]], iptr [[SIVAR_PRIV]], |
| |
| // ~(firstprivate var), ~(firstprivate s_arr) |
| |
| |
| |
| |
| |
| |
| |
| // firstprivate t_var(t_var) |
| |
| // firstprivate vec(vec) |
| |
| // firstprivate s_arr(s_arr) |
| |
| // firstprivate var(var) |
| |
| // ~(firstprivate var), ~(firstprivate s_arr) |
| |
| |
| #endif |
| |
| // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init |
| // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test) |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float |
| // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 |
| // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00) |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00) |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor |
| // CHECK1-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done1: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float |
| // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] |
| // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 |
| // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@main |
| // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 |
| // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 |
| // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) |
| // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 |
| // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] |
| // CHECK1: omp_if.then: |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @t_var, align 4 |
| // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false) |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @s_arr, [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done1: |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) |
| // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR]], ptr nonnull align 4 dereferenceable(4) @var, ptr [[AGG_TMP2]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 |
| // CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) |
| // CHECK1-NEXT: store i32 41, ptr [[SIVAR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE1]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done5: |
| // CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: br label [[OMP_IF_END]] |
| // CHECK1: omp_if.end: |
| // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() |
| // CHECK1-NEXT: ret i32 [[CALL]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK1-SAME: () #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], i32 1) |
| // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3) |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) |
| // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done1: |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: ret i32 [[TMP1]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float |
| // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] |
| // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined |
| // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 |
| // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 |
| // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK1-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP6]], 0 |
| // CHECK1-NEXT: br i1 [[TMP7]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] |
| // CHECK1: omp_if.then: |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP8]], ptr [[T_VAR1]], align 4 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP1]], i64 8, i1 false) |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP9]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done4: |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) |
| // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 |
| // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR5]], i64 4, i1 false) |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done9: |
| // CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK1-NEXT: br label [[OMP_IF_END]] |
| // CHECK1: omp_if.end: |
| // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp |
| // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void @__cxx_global_var_init() |
| // CHECK1-NEXT: call void @__cxx_global_var_init.1() |
| // CHECK1-NEXT: call void @__cxx_global_var_init.2() |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init |
| // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test) |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float |
| // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 |
| // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00) |
| // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00) |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor |
| // CHECK3-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK3: arraydestroy.body: |
| // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] |
| // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr |
| // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK3: arraydestroy.done1: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float |
| // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] |
| // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 |
| // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@main |
| // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 |
| // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8 |
| // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 8 dereferenceable(8) [[REF_TMP]]) |
| // CHECK3-NEXT: ret i32 0 |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp |
| // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void @__cxx_global_var_init() |
| // CHECK3-NEXT: call void @__cxx_global_var_init.1() |
| // CHECK3-NEXT: call void @__cxx_global_var_init.2() |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init |
| // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test) |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float |
| // CHECK4-NEXT: store float [[CONV]], ptr [[F]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 |
| // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00) |
| // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00) |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor |
| // CHECK4-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 |
| // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK4: arraydestroy.body: |
| // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] |
| // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr |
| // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK4: arraydestroy.done1: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float |
| // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] |
| // CHECK4-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 |
| // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@main |
| // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8 |
| // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 |
| // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 |
| // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 |
| // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8 |
| // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK4-NEXT: store ptr @__block_descriptor_tmp.3, ptr [[BLOCK_DESCRIPTOR]], align 8 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK4-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8 |
| // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 |
| // CHECK4-NEXT: call void [[TMP2]](ptr [[BLOCK]]) |
| // CHECK4-NEXT: ret i32 0 |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke |
| // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 |
| // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr @_ZZ4mainE5sivar) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined |
| // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, align 8 |
| // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP2]]) |
| // CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 |
| // CHECK4-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] |
| // CHECK4: omp_if.then: |
| // CHECK4-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @g, align 4 |
| // CHECK4-NEXT: store i32 [[TMP5]], ptr [[G]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP6]], ptr [[SIVAR1]], align 4 |
| // CHECK4-NEXT: store i32 1, ptr [[G]], align 4 |
| // CHECK4-NEXT: store i32 37, ptr [[SIVAR1]], align 4 |
| // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 |
| // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 |
| // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 |
| // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: store ptr @var_block_invoke, ptr [[BLOCK_INVOKE]], align 8 |
| // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load volatile i32, ptr [[G]], align 4 |
| // CHECK4-NEXT: store volatile i32 [[TMP7]], ptr [[BLOCK_CAPTURED]], align 8 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 6 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR1]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP8]], ptr [[BLOCK_CAPTURED2]], align 4 |
| // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 |
| // CHECK4-NEXT: call void [[TMP10]](ptr [[BLOCK]]) |
| // CHECK4-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP2]]) |
| // CHECK4-NEXT: br label [[OMP_IF_END]] |
| // CHECK4: omp_if.end: |
| // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke |
| // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 |
| // CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 8 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 |
| // CHECK4-NEXT: store i32 31, ptr [[BLOCK_CAPTURE_ADDR1]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp |
| // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void @__cxx_global_var_init() |
| // CHECK4-NEXT: call void @__cxx_global_var_init.1() |
| // CHECK4-NEXT: call void @__cxx_global_var_init.2() |
| // CHECK4-NEXT: ret void |
| // |
