[AMDGPU][CodeGen] Incrementally update reserved regs for SIPreAllocateWWMRegs pass in RegisterClassInfo (#212201) Based on this TODO comment in SIPreAllocateWWMRegs.cpp: 76 // TODO: Update RCI with the additional reserved registers the pass sets. 77 AU.addRequired<MachineRegisterClassInfoWrapperPass>(); Creates function updateReservedRegs in RegisterClassInfo.cpp which takes the BitVector containing reserved register information without requiring any unnecessary recomputations of the entire RegisterClassInfo object. It: - Compares the new reserved-register set with the cached set. - Removes newly reserved registers from cached allocation orders. - Updates register counts, costs, subclass information, and pressure limits. - Invalidates entries when incremental updating is unsafe; they are recomputed only when next requested. - Allows `SIPreAllocateWWMRegs` to preserve `RegisterClassInfo` after reserving WWM registers. Also drops the unconditional compute(RC) in computePSetLimit, which was redundant since getNumAllocatableRegs already recomputes stale entries. This is within the scope of my PR because it would unnecessarily rebuild an already-valid entry, rendering the incremental update pointless. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
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