)]}'
{
  "commit": "ad3c19a8984263286bc930c4d7a127cced8200ec",
  "tree": "db2d6b85ebe7dadd75def307e859ba824efabf91",
  "parents": [
    "16bea755713721f967029aabb4da153e2cc40f62"
  ],
  "author": {
    "name": "Nikhil Kotikalapudi",
    "email": "nak00001@outlook.com",
    "time": "Fri Aug 28 11:35:57 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Aug 28 17:35:57 2026 +0200"
  },
  "message": "[AMDGPU][CodeGen] Incrementally update reserved regs for SIPreAllocateWWMRegs pass in RegisterClassInfo (#212201)\n\nBased on this TODO comment in SIPreAllocateWWMRegs.cpp:\n\n76    // TODO: Update RCI with the additional reserved registers the pass sets.\n77    AU.addRequired\u003cMachineRegisterClassInfoWrapperPass\u003e();\n\nCreates function updateReservedRegs in RegisterClassInfo.cpp which takes\nthe BitVector containing reserved register information without requiring\nany unnecessary recomputations of the entire RegisterClassInfo object.\nIt:\n- Compares the new reserved-register set with the cached set.\n- Removes newly reserved registers from cached allocation orders.\n- Updates register counts, costs, subclass information, and pressure\nlimits.\n- Invalidates entries when incremental updating is unsafe; they are\nrecomputed only when next requested.\n- Allows `SIPreAllocateWWMRegs` to preserve `RegisterClassInfo` after\nreserving WWM registers.\n\nAlso drops the unconditional compute(RC) in computePSetLimit, which was\nredundant since getNumAllocatableRegs already recomputes stale entries.\nThis is within the scope of my PR because it would unnecessarily rebuild\nan already-valid entry, rendering the incremental update pointless.\n\n---------\n\nCo-authored-by: Matt Arsenault \u003carsenm2@gmail.com\u003e",
  "tree_diff": [
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