llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64

define <vscale x 1 x i8> @vrem_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vrem_vv_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 1 x i8> %va, %vb
  ret <vscale x 1 x i8> %vc
}

define <vscale x 1 x i8> @vrem_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vrem_vx_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i8> %va, %splat
  ret <vscale x 1 x i8> %vc
}

define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vrem_vi_nxv1i8_0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 109
; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT:    vmulh.vx v9, v8, a0
; CHECK-NEXT:    vsub.vv v9, v9, v8
; CHECK-NEXT:    vsra.vi v9, v9, 2
; CHECK-NEXT:    vsrl.vi v10, v9, 7
; CHECK-NEXT:    vadd.vv v9, v9, v10
; CHECK-NEXT:    li a0, -7
; CHECK-NEXT:    vnmsac.vx v8, a0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i8> %va, %splat
  ret <vscale x 1 x i8> %vc
}

define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-LABEL: vrem_vv_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 2 x i8> %va, %vb
  ret <vscale x 2 x i8> %vc
}

define <vscale x 2 x i8> @vrem_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vrem_vx_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i8> %va, %splat
  ret <vscale x 2 x i8> %vc
}

define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vrem_vi_nxv2i8_0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 109
; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT:    vmulh.vx v9, v8, a0
; CHECK-NEXT:    vsub.vv v9, v9, v8
; CHECK-NEXT:    vsra.vi v9, v9, 2
; CHECK-NEXT:    vsrl.vi v10, v9, 7
; CHECK-NEXT:    vadd.vv v9, v9, v10
; CHECK-NEXT:    li a0, -7
; CHECK-NEXT:    vnmsac.vx v8, a0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i8> %va, %splat
  ret <vscale x 2 x i8> %vc
}

define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-LABEL: vrem_vv_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 4 x i8> %va, %vb
  ret <vscale x 4 x i8> %vc
}

define <vscale x 4 x i8> @vrem_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vrem_vx_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i8> %va, %splat
  ret <vscale x 4 x i8> %vc
}

define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vrem_vi_nxv4i8_0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 109
; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT:    vmulh.vx v9, v8, a0
; CHECK-NEXT:    vsub.vv v9, v9, v8
; CHECK-NEXT:    vsra.vi v9, v9, 2
; CHECK-NEXT:    vsrl.vi v10, v9, 7
; CHECK-NEXT:    vadd.vv v9, v9, v10
; CHECK-NEXT:    li a0, -7
; CHECK-NEXT:    vnmsac.vx v8, a0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i8> %va, %splat
  ret <vscale x 4 x i8> %vc
}

define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: vrem_vv_nxv8i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 8 x i8> %va, %vb
  ret <vscale x 8 x i8> %vc
}

define <vscale x 8 x i8> @vrem_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vrem_vx_nxv8i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i8> %va, %splat
  ret <vscale x 8 x i8> %vc
}

define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vrem_vi_nxv8i8_0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 109
; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT:    vmulh.vx v9, v8, a0
; CHECK-NEXT:    vsub.vv v9, v9, v8
; CHECK-NEXT:    vsra.vi v9, v9, 2
; CHECK-NEXT:    vsrl.vi v10, v9, 7
; CHECK-NEXT:    vadd.vv v9, v9, v10
; CHECK-NEXT:    li a0, -7
; CHECK-NEXT:    vnmsac.vx v8, a0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i8> %va, %splat
  ret <vscale x 8 x i8> %vc
}

define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-LABEL: vrem_vv_nxv16i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v10
; CHECK-NEXT:    ret
  %vc = srem <vscale x 16 x i8> %va, %vb
  ret <vscale x 16 x i8> %vc
}

define <vscale x 16 x i8> @vrem_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vrem_vx_nxv16i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
  %vc = srem <vscale x 16 x i8> %va, %splat
  ret <vscale x 16 x i8> %vc
}

define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vrem_vi_nxv16i8_0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 109
; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
; CHECK-NEXT:    vmulh.vx v10, v8, a0
; CHECK-NEXT:    vsub.vv v10, v10, v8
; CHECK-NEXT:    vsra.vi v10, v10, 2
; CHECK-NEXT:    vsrl.vi v12, v10, 7
; CHECK-NEXT:    vadd.vv v10, v10, v12
; CHECK-NEXT:    li a0, -7
; CHECK-NEXT:    vnmsac.vx v8, a0, v10
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
  %vc = srem <vscale x 16 x i8> %va, %splat
  ret <vscale x 16 x i8> %vc
}

define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-LABEL: vrem_vv_nxv32i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v12
; CHECK-NEXT:    ret
  %vc = srem <vscale x 32 x i8> %va, %vb
  ret <vscale x 32 x i8> %vc
}

define <vscale x 32 x i8> @vrem_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vrem_vx_nxv32i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
  %vc = srem <vscale x 32 x i8> %va, %splat
  ret <vscale x 32 x i8> %vc
}

define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vrem_vi_nxv32i8_0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 109
; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT:    vmulh.vx v12, v8, a0
; CHECK-NEXT:    vsub.vv v12, v12, v8
; CHECK-NEXT:    vsra.vi v12, v12, 2
; CHECK-NEXT:    vsrl.vi v16, v12, 7
; CHECK-NEXT:    vadd.vv v12, v12, v16
; CHECK-NEXT:    li a0, -7
; CHECK-NEXT:    vnmsac.vx v8, a0, v12
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
  %vc = srem <vscale x 32 x i8> %va, %splat
  ret <vscale x 32 x i8> %vc
}

define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-LABEL: vrem_vv_nxv64i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v16
; CHECK-NEXT:    ret
  %vc = srem <vscale x 64 x i8> %va, %vb
  ret <vscale x 64 x i8> %vc
}

define <vscale x 64 x i8> @vrem_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vrem_vx_nxv64i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
  %vc = srem <vscale x 64 x i8> %va, %splat
  ret <vscale x 64 x i8> %vc
}

define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vrem_vi_nxv64i8_0:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 109
; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT:    vmulh.vx v16, v8, a0
; CHECK-NEXT:    vsub.vv v16, v16, v8
; CHECK-NEXT:    vsra.vi v16, v16, 2
; CHECK-NEXT:    vsrl.vi v24, v16, 7
; CHECK-NEXT:    vadd.vv v16, v16, v24
; CHECK-NEXT:    li a0, -7
; CHECK-NEXT:    vnmsac.vx v8, a0, v16
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
  %vc = srem <vscale x 64 x i8> %va, %splat
  ret <vscale x 64 x i8> %vc
}

define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-LABEL: vrem_vv_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 1 x i16> %va, %vb
  ret <vscale x 1 x i16> %vc
}

define <vscale x 1 x i16> @vrem_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vrem_vx_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i16> %va, %splat
  ret <vscale x 1 x i16> %vc
}

define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; RV32-LABEL: vrem_vi_nxv1i16_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 1048571
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
; RV32-NEXT:    vmulh.vx v9, v8, a0
; RV32-NEXT:    vsra.vi v9, v9, 1
; RV32-NEXT:    vsrl.vi v10, v9, 15
; RV32-NEXT:    vadd.vv v9, v9, v10
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v9
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv1i16_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1048571
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
; RV64-NEXT:    vmulh.vx v9, v8, a0
; RV64-NEXT:    vsra.vi v9, v9, 1
; RV64-NEXT:    vsrl.vi v10, v9, 15
; RV64-NEXT:    vadd.vv v9, v9, v10
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v9
; RV64-NEXT:    ret
  %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i16> %va, %splat
  ret <vscale x 1 x i16> %vc
}

define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-LABEL: vrem_vv_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 2 x i16> %va, %vb
  ret <vscale x 2 x i16> %vc
}

define <vscale x 2 x i16> @vrem_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vrem_vx_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i16> %va, %splat
  ret <vscale x 2 x i16> %vc
}

define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; RV32-LABEL: vrem_vi_nxv2i16_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 1048571
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
; RV32-NEXT:    vmulh.vx v9, v8, a0
; RV32-NEXT:    vsra.vi v9, v9, 1
; RV32-NEXT:    vsrl.vi v10, v9, 15
; RV32-NEXT:    vadd.vv v9, v9, v10
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v9
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv2i16_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1048571
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
; RV64-NEXT:    vmulh.vx v9, v8, a0
; RV64-NEXT:    vsra.vi v9, v9, 1
; RV64-NEXT:    vsrl.vi v10, v9, 15
; RV64-NEXT:    vadd.vv v9, v9, v10
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v9
; RV64-NEXT:    ret
  %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i16> %va, %splat
  ret <vscale x 2 x i16> %vc
}

define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-LABEL: vrem_vv_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 4 x i16> %va, %vb
  ret <vscale x 4 x i16> %vc
}

define <vscale x 4 x i16> @vrem_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vrem_vx_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i16> %va, %splat
  ret <vscale x 4 x i16> %vc
}

define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; RV32-LABEL: vrem_vi_nxv4i16_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 1048571
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
; RV32-NEXT:    vmulh.vx v9, v8, a0
; RV32-NEXT:    vsra.vi v9, v9, 1
; RV32-NEXT:    vsrl.vi v10, v9, 15
; RV32-NEXT:    vadd.vv v9, v9, v10
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v9
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv4i16_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1048571
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
; RV64-NEXT:    vmulh.vx v9, v8, a0
; RV64-NEXT:    vsra.vi v9, v9, 1
; RV64-NEXT:    vsrl.vi v10, v9, 15
; RV64-NEXT:    vadd.vv v9, v9, v10
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v9
; RV64-NEXT:    ret
  %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i16> %va, %splat
  ret <vscale x 4 x i16> %vc
}

define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: vrem_vv_nxv8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v10
; CHECK-NEXT:    ret
  %vc = srem <vscale x 8 x i16> %va, %vb
  ret <vscale x 8 x i16> %vc
}

define <vscale x 8 x i16> @vrem_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vrem_vx_nxv8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i16> %va, %splat
  ret <vscale x 8 x i16> %vc
}

define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; RV32-LABEL: vrem_vi_nxv8i16_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 1048571
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
; RV32-NEXT:    vmulh.vx v10, v8, a0
; RV32-NEXT:    vsra.vi v10, v10, 1
; RV32-NEXT:    vsrl.vi v12, v10, 15
; RV32-NEXT:    vadd.vv v10, v10, v12
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v10
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv8i16_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1048571
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
; RV64-NEXT:    vmulh.vx v10, v8, a0
; RV64-NEXT:    vsra.vi v10, v10, 1
; RV64-NEXT:    vsrl.vi v12, v10, 15
; RV64-NEXT:    vadd.vv v10, v10, v12
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v10
; RV64-NEXT:    ret
  %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i16> %va, %splat
  ret <vscale x 8 x i16> %vc
}

define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-LABEL: vrem_vv_nxv16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v12
; CHECK-NEXT:    ret
  %vc = srem <vscale x 16 x i16> %va, %vb
  ret <vscale x 16 x i16> %vc
}

define <vscale x 16 x i16> @vrem_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vrem_vx_nxv16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
  %vc = srem <vscale x 16 x i16> %va, %splat
  ret <vscale x 16 x i16> %vc
}

define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; RV32-LABEL: vrem_vi_nxv16i16_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 1048571
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
; RV32-NEXT:    vmulh.vx v12, v8, a0
; RV32-NEXT:    vsra.vi v12, v12, 1
; RV32-NEXT:    vsrl.vi v16, v12, 15
; RV32-NEXT:    vadd.vv v12, v12, v16
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v12
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv16i16_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1048571
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
; RV64-NEXT:    vmulh.vx v12, v8, a0
; RV64-NEXT:    vsra.vi v12, v12, 1
; RV64-NEXT:    vsrl.vi v16, v12, 15
; RV64-NEXT:    vadd.vv v12, v12, v16
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v12
; RV64-NEXT:    ret
  %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
  %vc = srem <vscale x 16 x i16> %va, %splat
  ret <vscale x 16 x i16> %vc
}

define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-LABEL: vrem_vv_nxv32i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v16
; CHECK-NEXT:    ret
  %vc = srem <vscale x 32 x i16> %va, %vb
  ret <vscale x 32 x i16> %vc
}

define <vscale x 32 x i16> @vrem_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
; CHECK-LABEL: vrem_vx_nxv32i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
  %vc = srem <vscale x 32 x i16> %va, %splat
  ret <vscale x 32 x i16> %vc
}

define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; RV32-LABEL: vrem_vi_nxv32i16_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 1048571
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
; RV32-NEXT:    vmulh.vx v16, v8, a0
; RV32-NEXT:    vsra.vi v16, v16, 1
; RV32-NEXT:    vsrl.vi v24, v16, 15
; RV32-NEXT:    vadd.vv v16, v16, v24
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv32i16_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1048571
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
; RV64-NEXT:    vmulh.vx v16, v8, a0
; RV64-NEXT:    vsra.vi v16, v16, 1
; RV64-NEXT:    vsrl.vi v24, v16, 15
; RV64-NEXT:    vadd.vv v16, v16, v24
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v16
; RV64-NEXT:    ret
  %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
  %vc = srem <vscale x 32 x i16> %va, %splat
  ret <vscale x 32 x i16> %vc
}

define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vrem_vv_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 1 x i32> %va, %vb
  ret <vscale x 1 x i32> %vc
}

define <vscale x 1 x i32> @vrem_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vrem_vx_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i32> %va, %splat
  ret <vscale x 1 x i32> %vc
}

define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; RV32-LABEL: vrem_vi_nxv1i32_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 449390
; RV32-NEXT:    addi a0, a0, -1171
; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
; RV32-NEXT:    vmulh.vx v9, v8, a0
; RV32-NEXT:    vsub.vv v9, v9, v8
; RV32-NEXT:    vsrl.vi v10, v9, 31
; RV32-NEXT:    vsra.vi v9, v9, 2
; RV32-NEXT:    vadd.vv v9, v9, v10
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v9
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv1i32_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 449390
; RV64-NEXT:    addiw a0, a0, -1171
; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
; RV64-NEXT:    vmulh.vx v9, v8, a0
; RV64-NEXT:    vsub.vv v9, v9, v8
; RV64-NEXT:    vsra.vi v9, v9, 2
; RV64-NEXT:    vsrl.vi v10, v9, 31
; RV64-NEXT:    vadd.vv v9, v9, v10
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v9
; RV64-NEXT:    ret
  %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i32> %va, %splat
  ret <vscale x 1 x i32> %vc
}

define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vrem_vv_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 2 x i32> %va, %vb
  ret <vscale x 2 x i32> %vc
}

define <vscale x 2 x i32> @vrem_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vrem_vx_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i32> %va, %splat
  ret <vscale x 2 x i32> %vc
}

define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; RV32-LABEL: vrem_vi_nxv2i32_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 449390
; RV32-NEXT:    addi a0, a0, -1171
; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
; RV32-NEXT:    vmulh.vx v9, v8, a0
; RV32-NEXT:    vsub.vv v9, v9, v8
; RV32-NEXT:    vsrl.vi v10, v9, 31
; RV32-NEXT:    vsra.vi v9, v9, 2
; RV32-NEXT:    vadd.vv v9, v9, v10
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v9
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv2i32_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 449390
; RV64-NEXT:    addiw a0, a0, -1171
; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
; RV64-NEXT:    vmulh.vx v9, v8, a0
; RV64-NEXT:    vsub.vv v9, v9, v8
; RV64-NEXT:    vsra.vi v9, v9, 2
; RV64-NEXT:    vsrl.vi v10, v9, 31
; RV64-NEXT:    vadd.vv v9, v9, v10
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v9
; RV64-NEXT:    ret
  %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i32> %va, %splat
  ret <vscale x 2 x i32> %vc
}

define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vrem_vv_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v10
; CHECK-NEXT:    ret
  %vc = srem <vscale x 4 x i32> %va, %vb
  ret <vscale x 4 x i32> %vc
}

define <vscale x 4 x i32> @vrem_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vrem_vx_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i32> %va, %splat
  ret <vscale x 4 x i32> %vc
}

define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; RV32-LABEL: vrem_vi_nxv4i32_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 449390
; RV32-NEXT:    addi a0, a0, -1171
; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
; RV32-NEXT:    vmulh.vx v10, v8, a0
; RV32-NEXT:    vsub.vv v10, v10, v8
; RV32-NEXT:    vsrl.vi v12, v10, 31
; RV32-NEXT:    vsra.vi v10, v10, 2
; RV32-NEXT:    vadd.vv v10, v10, v12
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v10
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv4i32_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 449390
; RV64-NEXT:    addiw a0, a0, -1171
; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
; RV64-NEXT:    vmulh.vx v10, v8, a0
; RV64-NEXT:    vsub.vv v10, v10, v8
; RV64-NEXT:    vsra.vi v10, v10, 2
; RV64-NEXT:    vsrl.vi v12, v10, 31
; RV64-NEXT:    vadd.vv v10, v10, v12
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v10
; RV64-NEXT:    ret
  %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i32> %va, %splat
  ret <vscale x 4 x i32> %vc
}

define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vrem_vv_nxv8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v12
; CHECK-NEXT:    ret
  %vc = srem <vscale x 8 x i32> %va, %vb
  ret <vscale x 8 x i32> %vc
}

define <vscale x 8 x i32> @vrem_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vrem_vx_nxv8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i32> %va, %splat
  ret <vscale x 8 x i32> %vc
}

define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; RV32-LABEL: vrem_vi_nxv8i32_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 449390
; RV32-NEXT:    addi a0, a0, -1171
; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
; RV32-NEXT:    vmulh.vx v12, v8, a0
; RV32-NEXT:    vsub.vv v12, v12, v8
; RV32-NEXT:    vsrl.vi v16, v12, 31
; RV32-NEXT:    vsra.vi v12, v12, 2
; RV32-NEXT:    vadd.vv v12, v12, v16
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v12
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv8i32_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 449390
; RV64-NEXT:    addiw a0, a0, -1171
; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
; RV64-NEXT:    vmulh.vx v12, v8, a0
; RV64-NEXT:    vsub.vv v12, v12, v8
; RV64-NEXT:    vsra.vi v12, v12, 2
; RV64-NEXT:    vsrl.vi v16, v12, 31
; RV64-NEXT:    vadd.vv v12, v12, v16
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v12
; RV64-NEXT:    ret
  %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i32> %va, %splat
  ret <vscale x 8 x i32> %vc
}

define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vrem_vv_nxv16i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v16
; CHECK-NEXT:    ret
  %vc = srem <vscale x 16 x i32> %va, %vb
  ret <vscale x 16 x i32> %vc
}

define <vscale x 16 x i32> @vrem_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vrem_vx_nxv16i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
; CHECK-NEXT:    vrem.vx v8, v8, a0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
  %vc = srem <vscale x 16 x i32> %va, %splat
  ret <vscale x 16 x i32> %vc
}

define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
; RV32-LABEL: vrem_vi_nxv16i32_0:
; RV32:       # %bb.0:
; RV32-NEXT:    lui a0, 449390
; RV32-NEXT:    addi a0, a0, -1171
; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
; RV32-NEXT:    vmulh.vx v16, v8, a0
; RV32-NEXT:    vsub.vv v16, v16, v8
; RV32-NEXT:    vsrl.vi v24, v16, 31
; RV32-NEXT:    vsra.vi v16, v16, 2
; RV32-NEXT:    vadd.vv v16, v16, v24
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv16i32_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 449390
; RV64-NEXT:    addiw a0, a0, -1171
; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
; RV64-NEXT:    vmulh.vx v16, v8, a0
; RV64-NEXT:    vsub.vv v16, v16, v8
; RV64-NEXT:    vsra.vi v16, v16, 2
; RV64-NEXT:    vsrl.vi v24, v16, 31
; RV64-NEXT:    vadd.vv v16, v16, v24
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v16
; RV64-NEXT:    ret
  %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
  %vc = srem <vscale x 16 x i32> %va, %splat
  ret <vscale x 16 x i32> %vc
}

define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vrem_vv_nxv1i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v9
; CHECK-NEXT:    ret
  %vc = srem <vscale x 1 x i64> %va, %vb
  ret <vscale x 1 x i64> %vc
}

define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw a1, 12(sp)
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v9, (a0), zero
; RV32-NEXT:    vrem.vv v8, v8, v9
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vx_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
; RV64-NEXT:    vrem.vx v8, v8, a0
; RV64-NEXT:    ret
  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i64> %va, %splat
  ret <vscale x 1 x i64> %vc
}

define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; RV32-LABEL: vrem_vi_nxv1i64_0:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    lui a0, 748983
; RV32-NEXT:    addi a0, a0, -586
; RV32-NEXT:    sw a0, 12(sp)
; RV32-NEXT:    lui a0, 898779
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v9, (a0), zero
; RV32-NEXT:    vmulh.vv v9, v8, v9
; RV32-NEXT:    li a0, 63
; RV32-NEXT:    vsrl.vx v10, v9, a0
; RV32-NEXT:    vsra.vi v9, v9, 1
; RV32-NEXT:    vadd.vv v9, v9, v10
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v9
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv1i64_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1029851
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
; RV64-NEXT:    vmulh.vx v9, v8, a0
; RV64-NEXT:    li a0, 63
; RV64-NEXT:    vsrl.vx v10, v9, a0
; RV64-NEXT:    vsra.vi v9, v9, 1
; RV64-NEXT:    vadd.vv v9, v9, v10
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v9
; RV64-NEXT:    ret
  %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
  %vc = srem <vscale x 1 x i64> %va, %splat
  ret <vscale x 1 x i64> %vc
}

define <vscale x 2 x i64> @vrem_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vrem_vv_nxv2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v10
; CHECK-NEXT:    ret
  %vc = srem <vscale x 2 x i64> %va, %vb
  ret <vscale x 2 x i64> %vc
}

define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw a1, 12(sp)
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v10, (a0), zero
; RV32-NEXT:    vrem.vv v8, v8, v10
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vx_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
; RV64-NEXT:    vrem.vx v8, v8, a0
; RV64-NEXT:    ret
  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i64> %va, %splat
  ret <vscale x 2 x i64> %vc
}

define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; RV32-LABEL: vrem_vi_nxv2i64_0:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    lui a0, 748983
; RV32-NEXT:    addi a0, a0, -586
; RV32-NEXT:    sw a0, 12(sp)
; RV32-NEXT:    lui a0, 898779
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v10, (a0), zero
; RV32-NEXT:    vmulh.vv v10, v8, v10
; RV32-NEXT:    li a0, 63
; RV32-NEXT:    vsrl.vx v12, v10, a0
; RV32-NEXT:    vsra.vi v10, v10, 1
; RV32-NEXT:    vadd.vv v10, v10, v12
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v10
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv2i64_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1029851
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
; RV64-NEXT:    vmulh.vx v10, v8, a0
; RV64-NEXT:    li a0, 63
; RV64-NEXT:    vsrl.vx v12, v10, a0
; RV64-NEXT:    vsra.vi v10, v10, 1
; RV64-NEXT:    vadd.vv v10, v10, v12
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v10
; RV64-NEXT:    ret
  %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
  %vc = srem <vscale x 2 x i64> %va, %splat
  ret <vscale x 2 x i64> %vc
}

define <vscale x 4 x i64> @vrem_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vrem_vv_nxv4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v12
; CHECK-NEXT:    ret
  %vc = srem <vscale x 4 x i64> %va, %vb
  ret <vscale x 4 x i64> %vc
}

define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw a1, 12(sp)
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v12, (a0), zero
; RV32-NEXT:    vrem.vv v8, v8, v12
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vx_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
; RV64-NEXT:    vrem.vx v8, v8, a0
; RV64-NEXT:    ret
  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i64> %va, %splat
  ret <vscale x 4 x i64> %vc
}

define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; RV32-LABEL: vrem_vi_nxv4i64_0:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    lui a0, 748983
; RV32-NEXT:    addi a0, a0, -586
; RV32-NEXT:    sw a0, 12(sp)
; RV32-NEXT:    lui a0, 898779
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v12, (a0), zero
; RV32-NEXT:    vmulh.vv v12, v8, v12
; RV32-NEXT:    li a0, 63
; RV32-NEXT:    vsrl.vx v16, v12, a0
; RV32-NEXT:    vsra.vi v12, v12, 1
; RV32-NEXT:    vadd.vv v12, v12, v16
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v12
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv4i64_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1029851
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
; RV64-NEXT:    vmulh.vx v12, v8, a0
; RV64-NEXT:    li a0, 63
; RV64-NEXT:    vsrl.vx v16, v12, a0
; RV64-NEXT:    vsra.vi v12, v12, 1
; RV64-NEXT:    vadd.vv v12, v12, v16
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v12
; RV64-NEXT:    ret
  %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
  %vc = srem <vscale x 4 x i64> %va, %splat
  ret <vscale x 4 x i64> %vc
}

define <vscale x 8 x i64> @vrem_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vrem_vv_nxv8i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT:    vrem.vv v8, v8, v16
; CHECK-NEXT:    ret
  %vc = srem <vscale x 8 x i64> %va, %vb
  ret <vscale x 8 x i64> %vc
}

define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv8i64:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw a1, 12(sp)
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v16, (a0), zero
; RV32-NEXT:    vrem.vv v8, v8, v16
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vx_nxv8i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT:    vrem.vx v8, v8, a0
; RV64-NEXT:    ret
  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i64> %va, %splat
  ret <vscale x 8 x i64> %vc
}

define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; RV32-LABEL: vrem_vi_nxv8i64_0:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    lui a0, 748983
; RV32-NEXT:    addi a0, a0, -586
; RV32-NEXT:    sw a0, 12(sp)
; RV32-NEXT:    lui a0, 898779
; RV32-NEXT:    addi a0, a0, 1755
; RV32-NEXT:    sw a0, 8(sp)
; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    vlse64.v v16, (a0), zero
; RV32-NEXT:    vmulh.vv v16, v8, v16
; RV32-NEXT:    li a0, 63
; RV32-NEXT:    vsrl.vx v24, v16, a0
; RV32-NEXT:    vsra.vi v16, v16, 1
; RV32-NEXT:    vadd.vv v16, v16, v24
; RV32-NEXT:    li a0, -7
; RV32-NEXT:    vnmsac.vx v8, a0, v16
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vrem_vi_nxv8i64_0:
; RV64:       # %bb.0:
; RV64-NEXT:    lui a0, 1029851
; RV64-NEXT:    addiw a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    slli a0, a0, 12
; RV64-NEXT:    addi a0, a0, 1755
; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT:    vmulh.vx v16, v8, a0
; RV64-NEXT:    li a0, 63
; RV64-NEXT:    vsrl.vx v24, v16, a0
; RV64-NEXT:    vsra.vi v16, v16, 1
; RV64-NEXT:    vadd.vv v16, v16, v24
; RV64-NEXT:    li a0, -7
; RV64-NEXT:    vnmsac.vx v8, a0, v16
; RV64-NEXT:    ret
  %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
  %vc = srem <vscale x 8 x i64> %va, %splat
  ret <vscale x 8 x i64> %vc
}