llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv64 -mattr=+experimental-v -o - %s \
# RUN:   -stop-after=prologepilog | FileCheck %s

--- |
  define void @foo() !dbg !0 {
  entry:
    %va = alloca <vscale x 2 x i32>, align 4, !dbg !1
    br label %end
  end:
    ret void, !dbg !2
  }

  !0 = distinct !DISubprogram(name: "foo", line: 3, scopeLine: 3)
  !1 = !DILocation(line: 4, column: 14, scope: !0)
  !2 = !DILocation(line: 5, column: 3, scope: !0)

...
---
name: foo
tracksRegLiveness: true
stack:
  - { id: 0, stack-id: scalable-vector, offset: 0, size: 8, alignment: 8 }
body: |
  ; CHECK-LABEL: name: foo
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 0
  ; CHECK-NEXT:   $x10 = frame-setup PseudoReadVLENB
  ; CHECK-NEXT:   $x10 = frame-setup SLLI killed $x10, 1
  ; CHECK-NEXT:   $x2 = frame-setup SUB $x2, killed $x10
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   $x10 = frame-destroy PseudoReadVLENB
  ; CHECK-NEXT:   $x10 = frame-destroy SLLI killed $x10, 1
  ; CHECK-NEXT:   $x2 = frame-destroy ADD $x2, killed $x10
  ; CHECK-NEXT:   PseudoRET
  bb.0:
  bb.1:
    PseudoRET