llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir

# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# RUN: llc -mtriple riscv64 -mattr=+experimental-v -start-before=prologepilog -o - \
# RUN:     -verify-machineinstrs %s | FileCheck %s
--- |
  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
  target triple = "riscv64"

  define weak_odr dso_local void @fixedlen_vector_spillslot(i8* %ay) nounwind {
  ; CHECK-LABEL: fixedlen_vector_spillslot:
  ; CHECK:       # %bb.0: # %entry
  ; CHECK-NEXT:    addi sp, sp, -48
  ; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
  ; CHECK-NEXT:    sd a0, 32(sp)
  ; CHECK-NEXT:    sd a0, 16(sp)
  ; CHECK-NEXT:    vsetivli a5, 1, e16, m1, ta, mu
  ; CHECK-NEXT:    sd a1, 8(sp)
  ; CHECK-NEXT:    addi a1, sp, 24
  ; CHECK-NEXT:    vs1r.v v25, (a1) # Unknown-size Folded Spill
  ; CHECK-NEXT:    ld a1, 8(sp)
  ; CHECK-NEXT:    call fixedlen_vector_spillslot@plt
  ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
  ; CHECK-NEXT:    addi sp, sp, 48
  ; CHECK-NEXT:    ret
  entry:
    ret void
  }

...
---
name:            fixedlen_vector_spillslot
alignment:       2
tracksRegLiveness: false
fixedStack:      []
stack:
  - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: 0, size: 2, alignment: 8,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body:             |
  bb.0.entry:
    liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v25

    SD $x10, %stack.0, 0
    SD $x10, %stack.2, 0
    dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
    PseudoVSPILL_M1 killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8)
    ; This is here just to make all the eligible registers live at this point.
    ; This way when we replace the frame index %stack.1 with its actual address
    ; we have to allocate a virtual register to compute it.
    ; A later run of the the register scavenger won't find an available register
    ; either so it will have to spill one to the emergency spill slot.
    PseudoCALL target-flags(riscv-plt) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
    PseudoRET
...