llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s

define void @combine_fp_zero_stores_crash(float* %ptr)  {
; CHECK-LABEL: combine_fp_zero_stores_crash:
; CHECK:       # %bb.0:
; CHECK-NEXT:    addi a0, a0, 4
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vse32.v v8, (a0)
; CHECK-NEXT:    ret
  %addr1 = getelementptr float, float * %ptr, i64 1
  %addr2 = getelementptr float, float * %ptr, i64 2
  store float 0.000000e+00, float * %addr1, align 4
  store float 0.000000e+00, float * %addr2, align 4
  ret void
}