| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 |
| ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 |
| |
| define <vscale x 1 x i8> @bitreverse_nxv1i8(<vscale x 1 x i8> %va) { |
| ; CHECK-LABEL: bitreverse_nxv1i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu |
| ; CHECK-NEXT: vand.vi v9, v8, 15 |
| ; CHECK-NEXT: vsll.vi v9, v9, 4 |
| ; CHECK-NEXT: vsrl.vi v8, v8, 4 |
| ; CHECK-NEXT: vand.vi v8, v8, 15 |
| ; CHECK-NEXT: vor.vv v8, v8, v9 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 2 |
| ; CHECK-NEXT: li a0, 51 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vsll.vi v8, v8, 2 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 1 |
| ; CHECK-NEXT: li a0, 85 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: ret |
| %a = call <vscale x 1 x i8> @llvm.bitreverse.nxv1i8(<vscale x 1 x i8> %va) |
| ret <vscale x 1 x i8> %a |
| } |
| declare <vscale x 1 x i8> @llvm.bitreverse.nxv1i8(<vscale x 1 x i8>) |
| |
| define <vscale x 2 x i8> @bitreverse_nxv2i8(<vscale x 2 x i8> %va) { |
| ; CHECK-LABEL: bitreverse_nxv2i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu |
| ; CHECK-NEXT: vand.vi v9, v8, 15 |
| ; CHECK-NEXT: vsll.vi v9, v9, 4 |
| ; CHECK-NEXT: vsrl.vi v8, v8, 4 |
| ; CHECK-NEXT: vand.vi v8, v8, 15 |
| ; CHECK-NEXT: vor.vv v8, v8, v9 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 2 |
| ; CHECK-NEXT: li a0, 51 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vsll.vi v8, v8, 2 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 1 |
| ; CHECK-NEXT: li a0, 85 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: ret |
| %a = call <vscale x 2 x i8> @llvm.bitreverse.nxv2i8(<vscale x 2 x i8> %va) |
| ret <vscale x 2 x i8> %a |
| } |
| declare <vscale x 2 x i8> @llvm.bitreverse.nxv2i8(<vscale x 2 x i8>) |
| |
| define <vscale x 4 x i8> @bitreverse_nxv4i8(<vscale x 4 x i8> %va) { |
| ; CHECK-LABEL: bitreverse_nxv4i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu |
| ; CHECK-NEXT: vand.vi v9, v8, 15 |
| ; CHECK-NEXT: vsll.vi v9, v9, 4 |
| ; CHECK-NEXT: vsrl.vi v8, v8, 4 |
| ; CHECK-NEXT: vand.vi v8, v8, 15 |
| ; CHECK-NEXT: vor.vv v8, v8, v9 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 2 |
| ; CHECK-NEXT: li a0, 51 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vsll.vi v8, v8, 2 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 1 |
| ; CHECK-NEXT: li a0, 85 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: ret |
| %a = call <vscale x 4 x i8> @llvm.bitreverse.nxv4i8(<vscale x 4 x i8> %va) |
| ret <vscale x 4 x i8> %a |
| } |
| declare <vscale x 4 x i8> @llvm.bitreverse.nxv4i8(<vscale x 4 x i8>) |
| |
| define <vscale x 8 x i8> @bitreverse_nxv8i8(<vscale x 8 x i8> %va) { |
| ; CHECK-LABEL: bitreverse_nxv8i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu |
| ; CHECK-NEXT: vand.vi v9, v8, 15 |
| ; CHECK-NEXT: vsll.vi v9, v9, 4 |
| ; CHECK-NEXT: vsrl.vi v8, v8, 4 |
| ; CHECK-NEXT: vand.vi v8, v8, 15 |
| ; CHECK-NEXT: vor.vv v8, v8, v9 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 2 |
| ; CHECK-NEXT: li a0, 51 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vsll.vi v8, v8, 2 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: vsrl.vi v9, v8, 1 |
| ; CHECK-NEXT: li a0, 85 |
| ; CHECK-NEXT: vand.vx v9, v9, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vor.vv v8, v9, v8 |
| ; CHECK-NEXT: ret |
| %a = call <vscale x 8 x i8> @llvm.bitreverse.nxv8i8(<vscale x 8 x i8> %va) |
| ret <vscale x 8 x i8> %a |
| } |
| declare <vscale x 8 x i8> @llvm.bitreverse.nxv8i8(<vscale x 8 x i8>) |
| |
| define <vscale x 16 x i8> @bitreverse_nxv16i8(<vscale x 16 x i8> %va) { |
| ; CHECK-LABEL: bitreverse_nxv16i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu |
| ; CHECK-NEXT: vand.vi v10, v8, 15 |
| ; CHECK-NEXT: vsll.vi v10, v10, 4 |
| ; CHECK-NEXT: vsrl.vi v8, v8, 4 |
| ; CHECK-NEXT: vand.vi v8, v8, 15 |
| ; CHECK-NEXT: vor.vv v8, v8, v10 |
| ; CHECK-NEXT: vsrl.vi v10, v8, 2 |
| ; CHECK-NEXT: li a0, 51 |
| ; CHECK-NEXT: vand.vx v10, v10, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vsll.vi v8, v8, 2 |
| ; CHECK-NEXT: vor.vv v8, v10, v8 |
| ; CHECK-NEXT: vsrl.vi v10, v8, 1 |
| ; CHECK-NEXT: li a0, 85 |
| ; CHECK-NEXT: vand.vx v10, v10, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vor.vv v8, v10, v8 |
| ; CHECK-NEXT: ret |
| %a = call <vscale x 16 x i8> @llvm.bitreverse.nxv16i8(<vscale x 16 x i8> %va) |
| ret <vscale x 16 x i8> %a |
| } |
| declare <vscale x 16 x i8> @llvm.bitreverse.nxv16i8(<vscale x 16 x i8>) |
| |
| define <vscale x 32 x i8> @bitreverse_nxv32i8(<vscale x 32 x i8> %va) { |
| ; CHECK-LABEL: bitreverse_nxv32i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu |
| ; CHECK-NEXT: vand.vi v12, v8, 15 |
| ; CHECK-NEXT: vsll.vi v12, v12, 4 |
| ; CHECK-NEXT: vsrl.vi v8, v8, 4 |
| ; CHECK-NEXT: vand.vi v8, v8, 15 |
| ; CHECK-NEXT: vor.vv v8, v8, v12 |
| ; CHECK-NEXT: vsrl.vi v12, v8, 2 |
| ; CHECK-NEXT: li a0, 51 |
| ; CHECK-NEXT: vand.vx v12, v12, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vsll.vi v8, v8, 2 |
| ; CHECK-NEXT: vor.vv v8, v12, v8 |
| ; CHECK-NEXT: vsrl.vi v12, v8, 1 |
| ; CHECK-NEXT: li a0, 85 |
| ; CHECK-NEXT: vand.vx v12, v12, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vor.vv v8, v12, v8 |
| ; CHECK-NEXT: ret |
| %a = call <vscale x 32 x i8> @llvm.bitreverse.nxv32i8(<vscale x 32 x i8> %va) |
| ret <vscale x 32 x i8> %a |
| } |
| declare <vscale x 32 x i8> @llvm.bitreverse.nxv32i8(<vscale x 32 x i8>) |
| |
| define <vscale x 64 x i8> @bitreverse_nxv64i8(<vscale x 64 x i8> %va) { |
| ; CHECK-LABEL: bitreverse_nxv64i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu |
| ; CHECK-NEXT: vand.vi v16, v8, 15 |
| ; CHECK-NEXT: vsll.vi v16, v16, 4 |
| ; CHECK-NEXT: vsrl.vi v8, v8, 4 |
| ; CHECK-NEXT: vand.vi v8, v8, 15 |
| ; CHECK-NEXT: vor.vv v8, v8, v16 |
| ; CHECK-NEXT: vsrl.vi v16, v8, 2 |
| ; CHECK-NEXT: li a0, 51 |
| ; CHECK-NEXT: vand.vx v16, v16, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vsll.vi v8, v8, 2 |
| ; CHECK-NEXT: vor.vv v8, v16, v8 |
| ; CHECK-NEXT: vsrl.vi v16, v8, 1 |
| ; CHECK-NEXT: li a0, 85 |
| ; CHECK-NEXT: vand.vx v16, v16, a0 |
| ; CHECK-NEXT: vand.vx v8, v8, a0 |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vor.vv v8, v16, v8 |
| ; CHECK-NEXT: ret |
| %a = call <vscale x 64 x i8> @llvm.bitreverse.nxv64i8(<vscale x 64 x i8> %va) |
| ret <vscale x 64 x i8> %a |
| } |
| declare <vscale x 64 x i8> @llvm.bitreverse.nxv64i8(<vscale x 64 x i8>) |
| |
| define <vscale x 1 x i16> @bitreverse_nxv1i16(<vscale x 1 x i16> %va) { |
| ; RV32-LABEL: bitreverse_nxv1i16: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, mu |
| ; RV32-NEXT: vsrl.vi v9, v8, 8 |
| ; RV32-NEXT: vsll.vi v8, v8, 8 |
| ; RV32-NEXT: vor.vv v8, v8, v9 |
| ; RV32-NEXT: vsrl.vi v9, v8, 4 |
| ; RV32-NEXT: lui a0, 1 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 2 |
| ; RV32-NEXT: lui a0, 3 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 1 |
| ; RV32-NEXT: lui a0, 5 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv1i16: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, mu |
| ; RV64-NEXT: vsrl.vi v9, v8, 8 |
| ; RV64-NEXT: vsll.vi v8, v8, 8 |
| ; RV64-NEXT: vor.vv v8, v8, v9 |
| ; RV64-NEXT: vsrl.vi v9, v8, 4 |
| ; RV64-NEXT: lui a0, 1 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 2 |
| ; RV64-NEXT: lui a0, 3 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 1 |
| ; RV64-NEXT: lui a0, 5 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 1 x i16> @llvm.bitreverse.nxv1i16(<vscale x 1 x i16> %va) |
| ret <vscale x 1 x i16> %a |
| } |
| declare <vscale x 1 x i16> @llvm.bitreverse.nxv1i16(<vscale x 1 x i16>) |
| |
| define <vscale x 2 x i16> @bitreverse_nxv2i16(<vscale x 2 x i16> %va) { |
| ; RV32-LABEL: bitreverse_nxv2i16: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu |
| ; RV32-NEXT: vsrl.vi v9, v8, 8 |
| ; RV32-NEXT: vsll.vi v8, v8, 8 |
| ; RV32-NEXT: vor.vv v8, v8, v9 |
| ; RV32-NEXT: vsrl.vi v9, v8, 4 |
| ; RV32-NEXT: lui a0, 1 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 2 |
| ; RV32-NEXT: lui a0, 3 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 1 |
| ; RV32-NEXT: lui a0, 5 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv2i16: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu |
| ; RV64-NEXT: vsrl.vi v9, v8, 8 |
| ; RV64-NEXT: vsll.vi v8, v8, 8 |
| ; RV64-NEXT: vor.vv v8, v8, v9 |
| ; RV64-NEXT: vsrl.vi v9, v8, 4 |
| ; RV64-NEXT: lui a0, 1 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 2 |
| ; RV64-NEXT: lui a0, 3 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 1 |
| ; RV64-NEXT: lui a0, 5 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 2 x i16> @llvm.bitreverse.nxv2i16(<vscale x 2 x i16> %va) |
| ret <vscale x 2 x i16> %a |
| } |
| declare <vscale x 2 x i16> @llvm.bitreverse.nxv2i16(<vscale x 2 x i16>) |
| |
| define <vscale x 4 x i16> @bitreverse_nxv4i16(<vscale x 4 x i16> %va) { |
| ; RV32-LABEL: bitreverse_nxv4i16: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu |
| ; RV32-NEXT: vsrl.vi v9, v8, 8 |
| ; RV32-NEXT: vsll.vi v8, v8, 8 |
| ; RV32-NEXT: vor.vv v8, v8, v9 |
| ; RV32-NEXT: vsrl.vi v9, v8, 4 |
| ; RV32-NEXT: lui a0, 1 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 2 |
| ; RV32-NEXT: lui a0, 3 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 1 |
| ; RV32-NEXT: lui a0, 5 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv4i16: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu |
| ; RV64-NEXT: vsrl.vi v9, v8, 8 |
| ; RV64-NEXT: vsll.vi v8, v8, 8 |
| ; RV64-NEXT: vor.vv v8, v8, v9 |
| ; RV64-NEXT: vsrl.vi v9, v8, 4 |
| ; RV64-NEXT: lui a0, 1 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 2 |
| ; RV64-NEXT: lui a0, 3 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 1 |
| ; RV64-NEXT: lui a0, 5 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 4 x i16> @llvm.bitreverse.nxv4i16(<vscale x 4 x i16> %va) |
| ret <vscale x 4 x i16> %a |
| } |
| declare <vscale x 4 x i16> @llvm.bitreverse.nxv4i16(<vscale x 4 x i16>) |
| |
| define <vscale x 8 x i16> @bitreverse_nxv8i16(<vscale x 8 x i16> %va) { |
| ; RV32-LABEL: bitreverse_nxv8i16: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, mu |
| ; RV32-NEXT: vsrl.vi v10, v8, 8 |
| ; RV32-NEXT: vsll.vi v8, v8, 8 |
| ; RV32-NEXT: vor.vv v8, v8, v10 |
| ; RV32-NEXT: vsrl.vi v10, v8, 4 |
| ; RV32-NEXT: lui a0, 1 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: vsrl.vi v10, v8, 2 |
| ; RV32-NEXT: lui a0, 3 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: vsrl.vi v10, v8, 1 |
| ; RV32-NEXT: lui a0, 5 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv8i16: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, mu |
| ; RV64-NEXT: vsrl.vi v10, v8, 8 |
| ; RV64-NEXT: vsll.vi v8, v8, 8 |
| ; RV64-NEXT: vor.vv v8, v8, v10 |
| ; RV64-NEXT: vsrl.vi v10, v8, 4 |
| ; RV64-NEXT: lui a0, 1 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: vsrl.vi v10, v8, 2 |
| ; RV64-NEXT: lui a0, 3 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: vsrl.vi v10, v8, 1 |
| ; RV64-NEXT: lui a0, 5 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 8 x i16> @llvm.bitreverse.nxv8i16(<vscale x 8 x i16> %va) |
| ret <vscale x 8 x i16> %a |
| } |
| declare <vscale x 8 x i16> @llvm.bitreverse.nxv8i16(<vscale x 8 x i16>) |
| |
| define <vscale x 16 x i16> @bitreverse_nxv16i16(<vscale x 16 x i16> %va) { |
| ; RV32-LABEL: bitreverse_nxv16i16: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, mu |
| ; RV32-NEXT: vsrl.vi v12, v8, 8 |
| ; RV32-NEXT: vsll.vi v8, v8, 8 |
| ; RV32-NEXT: vor.vv v8, v8, v12 |
| ; RV32-NEXT: vsrl.vi v12, v8, 4 |
| ; RV32-NEXT: lui a0, 1 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: vsrl.vi v12, v8, 2 |
| ; RV32-NEXT: lui a0, 3 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: vsrl.vi v12, v8, 1 |
| ; RV32-NEXT: lui a0, 5 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv16i16: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e16, m4, ta, mu |
| ; RV64-NEXT: vsrl.vi v12, v8, 8 |
| ; RV64-NEXT: vsll.vi v8, v8, 8 |
| ; RV64-NEXT: vor.vv v8, v8, v12 |
| ; RV64-NEXT: vsrl.vi v12, v8, 4 |
| ; RV64-NEXT: lui a0, 1 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: vsrl.vi v12, v8, 2 |
| ; RV64-NEXT: lui a0, 3 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: vsrl.vi v12, v8, 1 |
| ; RV64-NEXT: lui a0, 5 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 16 x i16> @llvm.bitreverse.nxv16i16(<vscale x 16 x i16> %va) |
| ret <vscale x 16 x i16> %a |
| } |
| declare <vscale x 16 x i16> @llvm.bitreverse.nxv16i16(<vscale x 16 x i16>) |
| |
| define <vscale x 32 x i16> @bitreverse_nxv32i16(<vscale x 32 x i16> %va) { |
| ; RV32-LABEL: bitreverse_nxv32i16: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e16, m8, ta, mu |
| ; RV32-NEXT: vsrl.vi v16, v8, 8 |
| ; RV32-NEXT: vsll.vi v8, v8, 8 |
| ; RV32-NEXT: vor.vv v8, v8, v16 |
| ; RV32-NEXT: vsrl.vi v16, v8, 4 |
| ; RV32-NEXT: lui a0, 1 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v16, v8 |
| ; RV32-NEXT: vsrl.vi v16, v8, 2 |
| ; RV32-NEXT: lui a0, 3 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v16, v8 |
| ; RV32-NEXT: vsrl.vi v16, v8, 1 |
| ; RV32-NEXT: lui a0, 5 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v16, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv32i16: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e16, m8, ta, mu |
| ; RV64-NEXT: vsrl.vi v16, v8, 8 |
| ; RV64-NEXT: vsll.vi v8, v8, 8 |
| ; RV64-NEXT: vor.vv v8, v8, v16 |
| ; RV64-NEXT: vsrl.vi v16, v8, 4 |
| ; RV64-NEXT: lui a0, 1 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: vsrl.vi v16, v8, 2 |
| ; RV64-NEXT: lui a0, 3 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: vsrl.vi v16, v8, 1 |
| ; RV64-NEXT: lui a0, 5 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 32 x i16> @llvm.bitreverse.nxv32i16(<vscale x 32 x i16> %va) |
| ret <vscale x 32 x i16> %a |
| } |
| declare <vscale x 32 x i16> @llvm.bitreverse.nxv32i16(<vscale x 32 x i16>) |
| |
| define <vscale x 1 x i32> @bitreverse_nxv1i32(<vscale x 1 x i32> %va) { |
| ; RV32-LABEL: bitreverse_nxv1i32: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu |
| ; RV32-NEXT: vsrl.vi v9, v8, 8 |
| ; RV32-NEXT: lui a0, 16 |
| ; RV32-NEXT: addi a0, a0, -256 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vsrl.vi v10, v8, 24 |
| ; RV32-NEXT: vor.vv v9, v9, v10 |
| ; RV32-NEXT: vsll.vi v10, v8, 8 |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vor.vv v8, v8, v10 |
| ; RV32-NEXT: vor.vv v8, v8, v9 |
| ; RV32-NEXT: vsrl.vi v9, v8, 4 |
| ; RV32-NEXT: lui a0, 61681 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 2 |
| ; RV32-NEXT: lui a0, 209715 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 1 |
| ; RV32-NEXT: lui a0, 349525 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv1i32: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu |
| ; RV64-NEXT: vsrl.vi v9, v8, 8 |
| ; RV64-NEXT: lui a0, 16 |
| ; RV64-NEXT: addiw a0, a0, -256 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vsrl.vi v10, v8, 24 |
| ; RV64-NEXT: vor.vv v9, v9, v10 |
| ; RV64-NEXT: vsll.vi v10, v8, 8 |
| ; RV64-NEXT: lui a0, 4080 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 24 |
| ; RV64-NEXT: vor.vv v8, v8, v10 |
| ; RV64-NEXT: vor.vv v8, v8, v9 |
| ; RV64-NEXT: vsrl.vi v9, v8, 4 |
| ; RV64-NEXT: lui a0, 61681 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 2 |
| ; RV64-NEXT: lui a0, 209715 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 1 |
| ; RV64-NEXT: lui a0, 349525 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 1 x i32> @llvm.bitreverse.nxv1i32(<vscale x 1 x i32> %va) |
| ret <vscale x 1 x i32> %a |
| } |
| declare <vscale x 1 x i32> @llvm.bitreverse.nxv1i32(<vscale x 1 x i32>) |
| |
| define <vscale x 2 x i32> @bitreverse_nxv2i32(<vscale x 2 x i32> %va) { |
| ; RV32-LABEL: bitreverse_nxv2i32: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu |
| ; RV32-NEXT: vsrl.vi v9, v8, 8 |
| ; RV32-NEXT: lui a0, 16 |
| ; RV32-NEXT: addi a0, a0, -256 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vsrl.vi v10, v8, 24 |
| ; RV32-NEXT: vor.vv v9, v9, v10 |
| ; RV32-NEXT: vsll.vi v10, v8, 8 |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vor.vv v8, v8, v10 |
| ; RV32-NEXT: vor.vv v8, v8, v9 |
| ; RV32-NEXT: vsrl.vi v9, v8, 4 |
| ; RV32-NEXT: lui a0, 61681 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 2 |
| ; RV32-NEXT: lui a0, 209715 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 1 |
| ; RV32-NEXT: lui a0, 349525 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v9, v9, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv2i32: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu |
| ; RV64-NEXT: vsrl.vi v9, v8, 8 |
| ; RV64-NEXT: lui a0, 16 |
| ; RV64-NEXT: addiw a0, a0, -256 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vsrl.vi v10, v8, 24 |
| ; RV64-NEXT: vor.vv v9, v9, v10 |
| ; RV64-NEXT: vsll.vi v10, v8, 8 |
| ; RV64-NEXT: lui a0, 4080 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 24 |
| ; RV64-NEXT: vor.vv v8, v8, v10 |
| ; RV64-NEXT: vor.vv v8, v8, v9 |
| ; RV64-NEXT: vsrl.vi v9, v8, 4 |
| ; RV64-NEXT: lui a0, 61681 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 2 |
| ; RV64-NEXT: lui a0, 209715 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 1 |
| ; RV64-NEXT: lui a0, 349525 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 2 x i32> @llvm.bitreverse.nxv2i32(<vscale x 2 x i32> %va) |
| ret <vscale x 2 x i32> %a |
| } |
| declare <vscale x 2 x i32> @llvm.bitreverse.nxv2i32(<vscale x 2 x i32>) |
| |
| define <vscale x 4 x i32> @bitreverse_nxv4i32(<vscale x 4 x i32> %va) { |
| ; RV32-LABEL: bitreverse_nxv4i32: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu |
| ; RV32-NEXT: vsrl.vi v10, v8, 8 |
| ; RV32-NEXT: lui a0, 16 |
| ; RV32-NEXT: addi a0, a0, -256 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vsrl.vi v12, v8, 24 |
| ; RV32-NEXT: vor.vv v10, v10, v12 |
| ; RV32-NEXT: vsll.vi v12, v8, 8 |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vor.vv v8, v8, v12 |
| ; RV32-NEXT: vor.vv v8, v8, v10 |
| ; RV32-NEXT: vsrl.vi v10, v8, 4 |
| ; RV32-NEXT: lui a0, 61681 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: vsrl.vi v10, v8, 2 |
| ; RV32-NEXT: lui a0, 209715 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: vsrl.vi v10, v8, 1 |
| ; RV32-NEXT: lui a0, 349525 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v10, v10, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv4i32: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu |
| ; RV64-NEXT: vsrl.vi v10, v8, 8 |
| ; RV64-NEXT: lui a0, 16 |
| ; RV64-NEXT: addiw a0, a0, -256 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vsrl.vi v12, v8, 24 |
| ; RV64-NEXT: vor.vv v10, v10, v12 |
| ; RV64-NEXT: vsll.vi v12, v8, 8 |
| ; RV64-NEXT: lui a0, 4080 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 24 |
| ; RV64-NEXT: vor.vv v8, v8, v12 |
| ; RV64-NEXT: vor.vv v8, v8, v10 |
| ; RV64-NEXT: vsrl.vi v10, v8, 4 |
| ; RV64-NEXT: lui a0, 61681 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: vsrl.vi v10, v8, 2 |
| ; RV64-NEXT: lui a0, 209715 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: vsrl.vi v10, v8, 1 |
| ; RV64-NEXT: lui a0, 349525 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 4 x i32> @llvm.bitreverse.nxv4i32(<vscale x 4 x i32> %va) |
| ret <vscale x 4 x i32> %a |
| } |
| declare <vscale x 4 x i32> @llvm.bitreverse.nxv4i32(<vscale x 4 x i32>) |
| |
| define <vscale x 8 x i32> @bitreverse_nxv8i32(<vscale x 8 x i32> %va) { |
| ; RV32-LABEL: bitreverse_nxv8i32: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, mu |
| ; RV32-NEXT: vsrl.vi v12, v8, 8 |
| ; RV32-NEXT: lui a0, 16 |
| ; RV32-NEXT: addi a0, a0, -256 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vsrl.vi v16, v8, 24 |
| ; RV32-NEXT: vor.vv v12, v12, v16 |
| ; RV32-NEXT: vsll.vi v16, v8, 8 |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vor.vv v8, v8, v16 |
| ; RV32-NEXT: vor.vv v8, v8, v12 |
| ; RV32-NEXT: vsrl.vi v12, v8, 4 |
| ; RV32-NEXT: lui a0, 61681 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: vsrl.vi v12, v8, 2 |
| ; RV32-NEXT: lui a0, 209715 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: vsrl.vi v12, v8, 1 |
| ; RV32-NEXT: lui a0, 349525 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v12, v12, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv8i32: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, mu |
| ; RV64-NEXT: vsrl.vi v12, v8, 8 |
| ; RV64-NEXT: lui a0, 16 |
| ; RV64-NEXT: addiw a0, a0, -256 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vsrl.vi v16, v8, 24 |
| ; RV64-NEXT: vor.vv v12, v12, v16 |
| ; RV64-NEXT: vsll.vi v16, v8, 8 |
| ; RV64-NEXT: lui a0, 4080 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 24 |
| ; RV64-NEXT: vor.vv v8, v8, v16 |
| ; RV64-NEXT: vor.vv v8, v8, v12 |
| ; RV64-NEXT: vsrl.vi v12, v8, 4 |
| ; RV64-NEXT: lui a0, 61681 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: vsrl.vi v12, v8, 2 |
| ; RV64-NEXT: lui a0, 209715 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: vsrl.vi v12, v8, 1 |
| ; RV64-NEXT: lui a0, 349525 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 8 x i32> @llvm.bitreverse.nxv8i32(<vscale x 8 x i32> %va) |
| ret <vscale x 8 x i32> %a |
| } |
| declare <vscale x 8 x i32> @llvm.bitreverse.nxv8i32(<vscale x 8 x i32>) |
| |
| define <vscale x 16 x i32> @bitreverse_nxv16i32(<vscale x 16 x i32> %va) { |
| ; RV32-LABEL: bitreverse_nxv16i32: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu |
| ; RV32-NEXT: vsrl.vi v16, v8, 8 |
| ; RV32-NEXT: lui a0, 16 |
| ; RV32-NEXT: addi a0, a0, -256 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vsrl.vi v24, v8, 24 |
| ; RV32-NEXT: vor.vv v16, v16, v24 |
| ; RV32-NEXT: vsll.vi v24, v8, 8 |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: vand.vx v24, v24, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vor.vv v8, v8, v24 |
| ; RV32-NEXT: vor.vv v8, v8, v16 |
| ; RV32-NEXT: vsrl.vi v16, v8, 4 |
| ; RV32-NEXT: lui a0, 61681 |
| ; RV32-NEXT: addi a0, a0, -241 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v16, v8 |
| ; RV32-NEXT: vsrl.vi v16, v8, 2 |
| ; RV32-NEXT: lui a0, 209715 |
| ; RV32-NEXT: addi a0, a0, 819 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v16, v8 |
| ; RV32-NEXT: vsrl.vi v16, v8, 1 |
| ; RV32-NEXT: lui a0, 349525 |
| ; RV32-NEXT: addi a0, a0, 1365 |
| ; RV32-NEXT: vand.vx v16, v16, a0 |
| ; RV32-NEXT: vand.vx v8, v8, a0 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v16, v8 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv16i32: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu |
| ; RV64-NEXT: vsrl.vi v16, v8, 8 |
| ; RV64-NEXT: lui a0, 16 |
| ; RV64-NEXT: addiw a0, a0, -256 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vsrl.vi v24, v8, 24 |
| ; RV64-NEXT: vor.vv v16, v16, v24 |
| ; RV64-NEXT: vsll.vi v24, v8, 8 |
| ; RV64-NEXT: lui a0, 4080 |
| ; RV64-NEXT: vand.vx v24, v24, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 24 |
| ; RV64-NEXT: vor.vv v8, v8, v24 |
| ; RV64-NEXT: vor.vv v8, v8, v16 |
| ; RV64-NEXT: vsrl.vi v16, v8, 4 |
| ; RV64-NEXT: lui a0, 61681 |
| ; RV64-NEXT: addiw a0, a0, -241 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: vsrl.vi v16, v8, 2 |
| ; RV64-NEXT: lui a0, 209715 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: vsrl.vi v16, v8, 1 |
| ; RV64-NEXT: lui a0, 349525 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 16 x i32> @llvm.bitreverse.nxv16i32(<vscale x 16 x i32> %va) |
| ret <vscale x 16 x i32> %a |
| } |
| declare <vscale x 16 x i32> @llvm.bitreverse.nxv16i32(<vscale x 16 x i32>) |
| |
| define <vscale x 1 x i64> @bitreverse_nxv1i64(<vscale x 1 x i64> %va) { |
| ; RV32-LABEL: bitreverse_nxv1i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw zero, 12(sp) |
| ; RV32-NEXT: lui a0, 1044480 |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: sw a0, 12(sp) |
| ; RV32-NEXT: sw zero, 8(sp) |
| ; RV32-NEXT: li a1, 255 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a1, 16 |
| ; RV32-NEXT: addi a1, a1, -256 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a2, 61681 |
| ; RV32-NEXT: addi a2, a2, -241 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 209715 |
| ; RV32-NEXT: addi a2, a2, 819 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 349525 |
| ; RV32-NEXT: addi a2, a2, 1365 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: li a2, 56 |
| ; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, mu |
| ; RV32-NEXT: vsrl.vx v9, v8, a2 |
| ; RV32-NEXT: li a3, 40 |
| ; RV32-NEXT: vsrl.vx v10, v8, a3 |
| ; RV32-NEXT: vand.vx v10, v10, a1 |
| ; RV32-NEXT: vor.vv v9, v10, v9 |
| ; RV32-NEXT: addi a1, sp, 8 |
| ; RV32-NEXT: vlse64.v v10, (a1), zero |
| ; RV32-NEXT: vsrl.vi v11, v8, 24 |
| ; RV32-NEXT: vand.vx v11, v11, a0 |
| ; RV32-NEXT: vsrl.vi v12, v8, 8 |
| ; RV32-NEXT: vand.vv v10, v12, v10 |
| ; RV32-NEXT: vor.vv v10, v10, v11 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v11, (a0), zero |
| ; RV32-NEXT: vor.vv v9, v10, v9 |
| ; RV32-NEXT: vsll.vx v10, v8, a2 |
| ; RV32-NEXT: vsll.vx v12, v8, a3 |
| ; RV32-NEXT: vand.vv v11, v12, v11 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v12, (a0), zero |
| ; RV32-NEXT: vor.vv v10, v10, v11 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v11, (a0), zero |
| ; RV32-NEXT: vsll.vi v13, v8, 8 |
| ; RV32-NEXT: vand.vv v12, v13, v12 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vand.vv v8, v8, v11 |
| ; RV32-NEXT: vor.vv v8, v8, v12 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v11, (a0), zero |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: vor.vv v8, v8, v9 |
| ; RV32-NEXT: vsrl.vi v9, v8, 4 |
| ; RV32-NEXT: vand.vv v9, v9, v11 |
| ; RV32-NEXT: vand.vv v8, v8, v11 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v10, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 2 |
| ; RV32-NEXT: vand.vv v9, v9, v10 |
| ; RV32-NEXT: vand.vv v8, v8, v10 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v10, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: vsrl.vi v9, v8, 1 |
| ; RV32-NEXT: vand.vv v9, v9, v10 |
| ; RV32-NEXT: vand.vv v8, v8, v10 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v9, v8 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv1i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: li a0, 56 |
| ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu |
| ; RV64-NEXT: vsrl.vx v9, v8, a0 |
| ; RV64-NEXT: li a1, 40 |
| ; RV64-NEXT: vsrl.vx v10, v8, a1 |
| ; RV64-NEXT: lui a2, 16 |
| ; RV64-NEXT: addiw a2, a2, -256 |
| ; RV64-NEXT: vand.vx v10, v10, a2 |
| ; RV64-NEXT: vor.vv v9, v10, v9 |
| ; RV64-NEXT: vsrl.vi v10, v8, 24 |
| ; RV64-NEXT: lui a2, 4080 |
| ; RV64-NEXT: vand.vx v10, v10, a2 |
| ; RV64-NEXT: vsrl.vi v11, v8, 8 |
| ; RV64-NEXT: li a2, 255 |
| ; RV64-NEXT: slli a3, a2, 24 |
| ; RV64-NEXT: vand.vx v11, v11, a3 |
| ; RV64-NEXT: vor.vv v10, v11, v10 |
| ; RV64-NEXT: vor.vv v9, v10, v9 |
| ; RV64-NEXT: vsll.vi v10, v8, 8 |
| ; RV64-NEXT: slli a3, a2, 32 |
| ; RV64-NEXT: vand.vx v10, v10, a3 |
| ; RV64-NEXT: vsll.vi v11, v8, 24 |
| ; RV64-NEXT: slli a3, a2, 40 |
| ; RV64-NEXT: vand.vx v11, v11, a3 |
| ; RV64-NEXT: vor.vv v10, v11, v10 |
| ; RV64-NEXT: vsll.vx v11, v8, a0 |
| ; RV64-NEXT: vsll.vx v8, v8, a1 |
| ; RV64-NEXT: slli a0, a2, 48 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vor.vv v8, v11, v8 |
| ; RV64-NEXT: vor.vv v8, v8, v10 |
| ; RV64-NEXT: vor.vv v8, v8, v9 |
| ; RV64-NEXT: vsrl.vi v9, v8, 4 |
| ; RV64-NEXT: lui a0, 3855 |
| ; RV64-NEXT: addiw a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 2 |
| ; RV64-NEXT: lui a0, 13107 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: vsrl.vi v9, v8, 1 |
| ; RV64-NEXT: lui a0, 21845 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v9, v9, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v9, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 1 x i64> @llvm.bitreverse.nxv1i64(<vscale x 1 x i64> %va) |
| ret <vscale x 1 x i64> %a |
| } |
| declare <vscale x 1 x i64> @llvm.bitreverse.nxv1i64(<vscale x 1 x i64>) |
| |
| define <vscale x 2 x i64> @bitreverse_nxv2i64(<vscale x 2 x i64> %va) { |
| ; RV32-LABEL: bitreverse_nxv2i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw zero, 12(sp) |
| ; RV32-NEXT: lui a0, 1044480 |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: sw a0, 12(sp) |
| ; RV32-NEXT: sw zero, 8(sp) |
| ; RV32-NEXT: li a1, 255 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a1, 16 |
| ; RV32-NEXT: addi a1, a1, -256 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a2, 61681 |
| ; RV32-NEXT: addi a2, a2, -241 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 209715 |
| ; RV32-NEXT: addi a2, a2, 819 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 349525 |
| ; RV32-NEXT: addi a2, a2, 1365 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: li a2, 56 |
| ; RV32-NEXT: vsetvli a3, zero, e64, m2, ta, mu |
| ; RV32-NEXT: vsrl.vx v10, v8, a2 |
| ; RV32-NEXT: li a3, 40 |
| ; RV32-NEXT: vsrl.vx v12, v8, a3 |
| ; RV32-NEXT: vand.vx v12, v12, a1 |
| ; RV32-NEXT: vor.vv v10, v12, v10 |
| ; RV32-NEXT: addi a1, sp, 8 |
| ; RV32-NEXT: vlse64.v v12, (a1), zero |
| ; RV32-NEXT: vsrl.vi v14, v8, 24 |
| ; RV32-NEXT: vand.vx v14, v14, a0 |
| ; RV32-NEXT: vsrl.vi v16, v8, 8 |
| ; RV32-NEXT: vand.vv v12, v16, v12 |
| ; RV32-NEXT: vor.vv v12, v12, v14 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v14, (a0), zero |
| ; RV32-NEXT: vor.vv v10, v12, v10 |
| ; RV32-NEXT: vsll.vx v12, v8, a2 |
| ; RV32-NEXT: vsll.vx v16, v8, a3 |
| ; RV32-NEXT: vand.vv v14, v16, v14 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vor.vv v12, v12, v14 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v14, (a0), zero |
| ; RV32-NEXT: vsll.vi v18, v8, 8 |
| ; RV32-NEXT: vand.vv v16, v18, v16 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vand.vv v8, v8, v14 |
| ; RV32-NEXT: vor.vv v8, v8, v16 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v14, (a0), zero |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: vor.vv v8, v8, v10 |
| ; RV32-NEXT: vsrl.vi v10, v8, 4 |
| ; RV32-NEXT: vand.vv v10, v10, v14 |
| ; RV32-NEXT: vand.vv v8, v8, v14 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v12, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: vsrl.vi v10, v8, 2 |
| ; RV32-NEXT: vand.vv v10, v10, v12 |
| ; RV32-NEXT: vand.vv v8, v8, v12 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v12, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: vsrl.vi v10, v8, 1 |
| ; RV32-NEXT: vand.vv v10, v10, v12 |
| ; RV32-NEXT: vand.vv v8, v8, v12 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v10, v8 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv2i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: li a0, 56 |
| ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu |
| ; RV64-NEXT: vsrl.vx v10, v8, a0 |
| ; RV64-NEXT: li a1, 40 |
| ; RV64-NEXT: vsrl.vx v12, v8, a1 |
| ; RV64-NEXT: lui a2, 16 |
| ; RV64-NEXT: addiw a2, a2, -256 |
| ; RV64-NEXT: vand.vx v12, v12, a2 |
| ; RV64-NEXT: vor.vv v10, v12, v10 |
| ; RV64-NEXT: vsrl.vi v12, v8, 24 |
| ; RV64-NEXT: lui a2, 4080 |
| ; RV64-NEXT: vand.vx v12, v12, a2 |
| ; RV64-NEXT: vsrl.vi v14, v8, 8 |
| ; RV64-NEXT: li a2, 255 |
| ; RV64-NEXT: slli a3, a2, 24 |
| ; RV64-NEXT: vand.vx v14, v14, a3 |
| ; RV64-NEXT: vor.vv v12, v14, v12 |
| ; RV64-NEXT: vor.vv v10, v12, v10 |
| ; RV64-NEXT: vsll.vi v12, v8, 8 |
| ; RV64-NEXT: slli a3, a2, 32 |
| ; RV64-NEXT: vand.vx v12, v12, a3 |
| ; RV64-NEXT: vsll.vi v14, v8, 24 |
| ; RV64-NEXT: slli a3, a2, 40 |
| ; RV64-NEXT: vand.vx v14, v14, a3 |
| ; RV64-NEXT: vor.vv v12, v14, v12 |
| ; RV64-NEXT: vsll.vx v14, v8, a0 |
| ; RV64-NEXT: vsll.vx v8, v8, a1 |
| ; RV64-NEXT: slli a0, a2, 48 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vor.vv v8, v14, v8 |
| ; RV64-NEXT: vor.vv v8, v8, v12 |
| ; RV64-NEXT: vor.vv v8, v8, v10 |
| ; RV64-NEXT: vsrl.vi v10, v8, 4 |
| ; RV64-NEXT: lui a0, 3855 |
| ; RV64-NEXT: addiw a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: vsrl.vi v10, v8, 2 |
| ; RV64-NEXT: lui a0, 13107 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: vsrl.vi v10, v8, 1 |
| ; RV64-NEXT: lui a0, 21845 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v10, v10, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v10, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64> %va) |
| ret <vscale x 2 x i64> %a |
| } |
| declare <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64>) |
| |
| define <vscale x 4 x i64> @bitreverse_nxv4i64(<vscale x 4 x i64> %va) { |
| ; RV32-LABEL: bitreverse_nxv4i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw zero, 12(sp) |
| ; RV32-NEXT: lui a0, 1044480 |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: sw a0, 12(sp) |
| ; RV32-NEXT: sw zero, 8(sp) |
| ; RV32-NEXT: li a1, 255 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a1, 16 |
| ; RV32-NEXT: addi a1, a1, -256 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a2, 61681 |
| ; RV32-NEXT: addi a2, a2, -241 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 209715 |
| ; RV32-NEXT: addi a2, a2, 819 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 349525 |
| ; RV32-NEXT: addi a2, a2, 1365 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: li a2, 56 |
| ; RV32-NEXT: vsetvli a3, zero, e64, m4, ta, mu |
| ; RV32-NEXT: vsrl.vx v12, v8, a2 |
| ; RV32-NEXT: li a3, 40 |
| ; RV32-NEXT: vsrl.vx v16, v8, a3 |
| ; RV32-NEXT: vand.vx v16, v16, a1 |
| ; RV32-NEXT: vor.vv v12, v16, v12 |
| ; RV32-NEXT: addi a1, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a1), zero |
| ; RV32-NEXT: vsrl.vi v20, v8, 24 |
| ; RV32-NEXT: vand.vx v20, v20, a0 |
| ; RV32-NEXT: vsrl.vi v24, v8, 8 |
| ; RV32-NEXT: vand.vv v16, v24, v16 |
| ; RV32-NEXT: vor.vv v16, v16, v20 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v20, (a0), zero |
| ; RV32-NEXT: vor.vv v12, v16, v12 |
| ; RV32-NEXT: vsll.vx v16, v8, a2 |
| ; RV32-NEXT: vsll.vx v24, v8, a3 |
| ; RV32-NEXT: vand.vv v20, v24, v20 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v24, (a0), zero |
| ; RV32-NEXT: vor.vv v16, v16, v20 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v20, (a0), zero |
| ; RV32-NEXT: vsll.vi v28, v8, 8 |
| ; RV32-NEXT: vand.vv v24, v28, v24 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vand.vv v8, v8, v20 |
| ; RV32-NEXT: vor.vv v8, v8, v24 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v20, (a0), zero |
| ; RV32-NEXT: vor.vv v8, v16, v8 |
| ; RV32-NEXT: vor.vv v8, v8, v12 |
| ; RV32-NEXT: vsrl.vi v12, v8, 4 |
| ; RV32-NEXT: vand.vv v12, v12, v20 |
| ; RV32-NEXT: vand.vv v8, v8, v20 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: vsrl.vi v12, v8, 2 |
| ; RV32-NEXT: vand.vv v12, v12, v16 |
| ; RV32-NEXT: vand.vv v8, v8, v16 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: vsrl.vi v12, v8, 1 |
| ; RV32-NEXT: vand.vv v12, v12, v16 |
| ; RV32-NEXT: vand.vv v8, v8, v16 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v12, v8 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv4i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: li a0, 56 |
| ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu |
| ; RV64-NEXT: vsrl.vx v12, v8, a0 |
| ; RV64-NEXT: li a1, 40 |
| ; RV64-NEXT: vsrl.vx v16, v8, a1 |
| ; RV64-NEXT: lui a2, 16 |
| ; RV64-NEXT: addiw a2, a2, -256 |
| ; RV64-NEXT: vand.vx v16, v16, a2 |
| ; RV64-NEXT: vor.vv v12, v16, v12 |
| ; RV64-NEXT: vsrl.vi v16, v8, 24 |
| ; RV64-NEXT: lui a2, 4080 |
| ; RV64-NEXT: vand.vx v16, v16, a2 |
| ; RV64-NEXT: vsrl.vi v20, v8, 8 |
| ; RV64-NEXT: li a2, 255 |
| ; RV64-NEXT: slli a3, a2, 24 |
| ; RV64-NEXT: vand.vx v20, v20, a3 |
| ; RV64-NEXT: vor.vv v16, v20, v16 |
| ; RV64-NEXT: vor.vv v12, v16, v12 |
| ; RV64-NEXT: vsll.vi v16, v8, 8 |
| ; RV64-NEXT: slli a3, a2, 32 |
| ; RV64-NEXT: vand.vx v16, v16, a3 |
| ; RV64-NEXT: vsll.vi v20, v8, 24 |
| ; RV64-NEXT: slli a3, a2, 40 |
| ; RV64-NEXT: vand.vx v20, v20, a3 |
| ; RV64-NEXT: vor.vv v16, v20, v16 |
| ; RV64-NEXT: vsll.vx v20, v8, a0 |
| ; RV64-NEXT: vsll.vx v8, v8, a1 |
| ; RV64-NEXT: slli a0, a2, 48 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vor.vv v8, v20, v8 |
| ; RV64-NEXT: vor.vv v8, v8, v16 |
| ; RV64-NEXT: vor.vv v8, v8, v12 |
| ; RV64-NEXT: vsrl.vi v12, v8, 4 |
| ; RV64-NEXT: lui a0, 3855 |
| ; RV64-NEXT: addiw a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: vsrl.vi v12, v8, 2 |
| ; RV64-NEXT: lui a0, 13107 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: vsrl.vi v12, v8, 1 |
| ; RV64-NEXT: lui a0, 21845 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v12, v12, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v12, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 4 x i64> @llvm.bitreverse.nxv4i64(<vscale x 4 x i64> %va) |
| ret <vscale x 4 x i64> %a |
| } |
| declare <vscale x 4 x i64> @llvm.bitreverse.nxv4i64(<vscale x 4 x i64>) |
| |
| define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) { |
| ; RV32-LABEL: bitreverse_nxv8i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: csrr a0, vlenb |
| ; RV32-NEXT: slli a0, a0, 4 |
| ; RV32-NEXT: sub sp, sp, a0 |
| ; RV32-NEXT: sw zero, 12(sp) |
| ; RV32-NEXT: lui a0, 1044480 |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: lui a0, 4080 |
| ; RV32-NEXT: sw a0, 12(sp) |
| ; RV32-NEXT: sw zero, 8(sp) |
| ; RV32-NEXT: li a1, 255 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a1, 16 |
| ; RV32-NEXT: addi a1, a1, -256 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: lui a2, 61681 |
| ; RV32-NEXT: addi a2, a2, -241 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 209715 |
| ; RV32-NEXT: addi a2, a2, 819 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: lui a2, 349525 |
| ; RV32-NEXT: addi a2, a2, 1365 |
| ; RV32-NEXT: sw a2, 12(sp) |
| ; RV32-NEXT: sw a2, 8(sp) |
| ; RV32-NEXT: li a2, 56 |
| ; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, mu |
| ; RV32-NEXT: vsrl.vx v16, v8, a2 |
| ; RV32-NEXT: li a3, 40 |
| ; RV32-NEXT: vsrl.vx v24, v8, a3 |
| ; RV32-NEXT: addi a4, sp, 8 |
| ; RV32-NEXT: vlse64.v v0, (a4), zero |
| ; RV32-NEXT: vand.vx v24, v24, a1 |
| ; RV32-NEXT: vor.vv v16, v24, v16 |
| ; RV32-NEXT: csrr a1, vlenb |
| ; RV32-NEXT: slli a1, a1, 3 |
| ; RV32-NEXT: add a1, sp, a1 |
| ; RV32-NEXT: addi a1, a1, 16 |
| ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill |
| ; RV32-NEXT: vsrl.vi v24, v8, 8 |
| ; RV32-NEXT: vand.vv v24, v24, v0 |
| ; RV32-NEXT: vsrl.vi v0, v8, 24 |
| ; RV32-NEXT: vand.vx v0, v0, a0 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vor.vv v24, v24, v0 |
| ; RV32-NEXT: csrr a0, vlenb |
| ; RV32-NEXT: slli a0, a0, 3 |
| ; RV32-NEXT: add a0, sp, a0 |
| ; RV32-NEXT: addi a0, a0, 16 |
| ; RV32-NEXT: vl8re8.v v0, (a0) # Unknown-size Folded Reload |
| ; RV32-NEXT: vor.vv v24, v24, v0 |
| ; RV32-NEXT: csrr a0, vlenb |
| ; RV32-NEXT: slli a0, a0, 3 |
| ; RV32-NEXT: add a0, sp, a0 |
| ; RV32-NEXT: addi a0, a0, 16 |
| ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill |
| ; RV32-NEXT: vsll.vx v24, v8, a3 |
| ; RV32-NEXT: vand.vv v16, v24, v16 |
| ; RV32-NEXT: vsll.vx v24, v8, a2 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v0, (a0), zero |
| ; RV32-NEXT: vor.vv v16, v24, v16 |
| ; RV32-NEXT: addi a0, sp, 16 |
| ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vsll.vi v24, v8, 8 |
| ; RV32-NEXT: vand.vv v24, v24, v0 |
| ; RV32-NEXT: vsll.vi v8, v8, 24 |
| ; RV32-NEXT: vand.vv v8, v8, v16 |
| ; RV32-NEXT: vor.vv v8, v8, v24 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: addi a0, sp, 16 |
| ; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload |
| ; RV32-NEXT: vor.vv v8, v24, v8 |
| ; RV32-NEXT: csrr a0, vlenb |
| ; RV32-NEXT: slli a0, a0, 3 |
| ; RV32-NEXT: add a0, sp, a0 |
| ; RV32-NEXT: addi a0, a0, 16 |
| ; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload |
| ; RV32-NEXT: vor.vv v8, v8, v24 |
| ; RV32-NEXT: vsrl.vi v24, v8, 4 |
| ; RV32-NEXT: vand.vv v24, v24, v16 |
| ; RV32-NEXT: vand.vv v8, v8, v16 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 4 |
| ; RV32-NEXT: vor.vv v8, v24, v8 |
| ; RV32-NEXT: vsrl.vi v24, v8, 2 |
| ; RV32-NEXT: vand.vv v24, v24, v16 |
| ; RV32-NEXT: vand.vv v8, v8, v16 |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vsll.vi v8, v8, 2 |
| ; RV32-NEXT: vor.vv v8, v24, v8 |
| ; RV32-NEXT: vsrl.vi v24, v8, 1 |
| ; RV32-NEXT: vand.vv v24, v24, v16 |
| ; RV32-NEXT: vand.vv v8, v8, v16 |
| ; RV32-NEXT: vadd.vv v8, v8, v8 |
| ; RV32-NEXT: vor.vv v8, v24, v8 |
| ; RV32-NEXT: csrr a0, vlenb |
| ; RV32-NEXT: slli a0, a0, 4 |
| ; RV32-NEXT: add sp, sp, a0 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: bitreverse_nxv8i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: li a0, 56 |
| ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu |
| ; RV64-NEXT: vsrl.vx v16, v8, a0 |
| ; RV64-NEXT: li a1, 40 |
| ; RV64-NEXT: vsrl.vx v24, v8, a1 |
| ; RV64-NEXT: lui a2, 16 |
| ; RV64-NEXT: addiw a2, a2, -256 |
| ; RV64-NEXT: vand.vx v24, v24, a2 |
| ; RV64-NEXT: vor.vv v16, v24, v16 |
| ; RV64-NEXT: vsrl.vi v24, v8, 24 |
| ; RV64-NEXT: lui a2, 4080 |
| ; RV64-NEXT: vand.vx v24, v24, a2 |
| ; RV64-NEXT: vsrl.vi v0, v8, 8 |
| ; RV64-NEXT: li a2, 255 |
| ; RV64-NEXT: slli a3, a2, 24 |
| ; RV64-NEXT: vand.vx v0, v0, a3 |
| ; RV64-NEXT: vor.vv v24, v0, v24 |
| ; RV64-NEXT: vor.vv v16, v24, v16 |
| ; RV64-NEXT: vsll.vi v24, v8, 8 |
| ; RV64-NEXT: slli a3, a2, 32 |
| ; RV64-NEXT: vand.vx v24, v24, a3 |
| ; RV64-NEXT: vsll.vi v0, v8, 24 |
| ; RV64-NEXT: slli a3, a2, 40 |
| ; RV64-NEXT: vand.vx v0, v0, a3 |
| ; RV64-NEXT: vor.vv v24, v0, v24 |
| ; RV64-NEXT: vsll.vx v0, v8, a0 |
| ; RV64-NEXT: vsll.vx v8, v8, a1 |
| ; RV64-NEXT: slli a0, a2, 48 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vor.vv v8, v0, v8 |
| ; RV64-NEXT: vor.vv v8, v8, v24 |
| ; RV64-NEXT: vor.vv v8, v8, v16 |
| ; RV64-NEXT: vsrl.vi v16, v8, 4 |
| ; RV64-NEXT: lui a0, 3855 |
| ; RV64-NEXT: addiw a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 241 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, -241 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 4 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: vsrl.vi v16, v8, 2 |
| ; RV64-NEXT: lui a0, 13107 |
| ; RV64-NEXT: addiw a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 819 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vsll.vi v8, v8, 2 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: vsrl.vi v16, v8, 1 |
| ; RV64-NEXT: lui a0, 21845 |
| ; RV64-NEXT: addiw a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: slli a0, a0, 12 |
| ; RV64-NEXT: addi a0, a0, 1365 |
| ; RV64-NEXT: vand.vx v16, v16, a0 |
| ; RV64-NEXT: vand.vx v8, v8, a0 |
| ; RV64-NEXT: vadd.vv v8, v8, v8 |
| ; RV64-NEXT: vor.vv v8, v16, v8 |
| ; RV64-NEXT: ret |
| %a = call <vscale x 8 x i64> @llvm.bitreverse.nxv8i64(<vscale x 8 x i64> %va) |
| ret <vscale x 8 x i64> %a |
| } |
| declare <vscale x 8 x i64> @llvm.bitreverse.nxv8i64(<vscale x 8 x i64>) |
