| //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file describes the subset of the 32-bit PowerPC instruction set, as used |
| // by the PowerPC instruction selector. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| include "PPCInstrFormats.td" |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC specific type constraints. |
| // |
| def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx |
| SDTCisVT<0, f64>, SDTCisPtrTy<1> |
| ]>; |
| def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x |
| SDTCisVT<0, f64>, SDTCisPtrTy<1> |
| ]>; |
| def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ |
| SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> |
| ]>; |
| def SDT_PPCstxsix : SDTypeProfile<0, 3, [ |
| SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> |
| ]>; |
| def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ |
| SDTCisFP<0>, SDTCisFP<1> |
| ]>; |
| def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ |
| SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> |
| ]>; |
| def SDT_PPCVexts : SDTypeProfile<1, 2, [ |
| SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> |
| ]>; |
| |
| def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, |
| SDTCisVT<1, i32> ]>; |
| def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, |
| SDTCisVT<1, i32> ]>; |
| def SDT_PPCvperm : SDTypeProfile<1, 3, [ |
| SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> |
| ]>; |
| |
| def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, |
| SDTCisVec<1>, SDTCisInt<2> |
| ]>; |
| |
| def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, |
| SDTCisInt<1> |
| ]>; |
| |
| def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, |
| SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> |
| ]>; |
| |
| def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, |
| SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> |
| ]>; |
| |
| def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, |
| SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> |
| ]>; |
| |
| def SDT_PPCvcmp : SDTypeProfile<1, 3, [ |
| SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> |
| ]>; |
| |
| def SDT_PPCcondbr : SDTypeProfile<0, 3, [ |
| SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> |
| ]>; |
| |
| def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ |
| SDTCisVT<0, i32>]>; |
| |
| def SDT_PPClbrx : SDTypeProfile<1, 2, [ |
| SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> |
| ]>; |
| def SDT_PPCstbrx : SDTypeProfile<0, 3, [ |
| SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> |
| ]>; |
| |
| def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ |
| SDTCisPtrTy<0>, SDTCisVT<1, i32> |
| ]>; |
| |
| def tocentry32 : Operand<iPTR> { |
| let MIOperandInfo = (ops i32imm:$imm); |
| } |
| |
| def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ |
| SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> |
| ]>; |
| def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ |
| SDTCisVec<0>, SDTCisInt<1> |
| ]>; |
| def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ |
| SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> |
| ]>; |
| def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ |
| SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> |
| ]>; |
| |
| def SDT_PPCqbflt : SDTypeProfile<1, 1, [ |
| SDTCisVec<0>, SDTCisVec<1> |
| ]>; |
| |
| def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ |
| SDTCisVec<0>, SDTCisPtrTy<1> |
| ]>; |
| |
| def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli |
| SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> |
| ]>; |
| |
| def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ |
| SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> |
| ]>; |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC specific DAG Nodes. |
| // |
| |
| def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; |
| def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; |
| def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; |
| def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; |
| |
| def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; |
| def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; |
| def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; |
| def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; |
| def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; |
| def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; |
| def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; |
| def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; |
| |
| def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", |
| SDTFPUnaryOp, [SDNPHasChain]>; |
| def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", |
| SDTFPUnaryOp, [SDNPHasChain]>; |
| def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", |
| SDTFPRoundOp, [SDNPHasChain]>; |
| def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", |
| SDTFPRoundOp, [SDNPHasChain]>; |
| |
| def PPCany_fcfid : PatFrags<(ops node:$op), |
| [(PPCfcfid node:$op), |
| (PPCstrict_fcfid node:$op)]>; |
| def PPCany_fcfidu : PatFrags<(ops node:$op), |
| [(PPCfcfidu node:$op), |
| (PPCstrict_fcfidu node:$op)]>; |
| def PPCany_fcfids : PatFrags<(ops node:$op), |
| [(PPCfcfids node:$op), |
| (PPCstrict_fcfids node:$op)]>; |
| def PPCany_fcfidus : PatFrags<(ops node:$op), |
| [(PPCfcfidus node:$op), |
| (PPCstrict_fcfidus node:$op)]>; |
| |
| def PPCcv_fp_to_uint_in_vsr: |
| SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; |
| def PPCcv_fp_to_sint_in_vsr: |
| SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; |
| def PPCstore_scal_int_from_vsr: |
| SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, |
| [SDNPHasChain, SDNPMayStore]>; |
| def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, |
| [SDNPHasChain, SDNPMayStore]>; |
| def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, |
| [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; |
| def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, |
| [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; |
| def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, |
| [SDNPHasChain, SDNPMayLoad]>; |
| def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, |
| [SDNPHasChain, SDNPMayStore]>; |
| def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; |
| |
| // Extract FPSCR (not modeled at the DAG level). |
| def PPCmffs : SDNode<"PPCISD::MFFS", |
| SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, |
| [SDNPHasChain]>; |
| |
| // Perform FADD in round-to-zero mode. |
| def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; |
| def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, |
| [SDNPHasChain]>; |
| |
| def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), |
| [(PPCfaddrtz node:$lhs, node:$rhs), |
| (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; |
| |
| def PPCfsel : SDNode<"PPCISD::FSEL", |
| // Type constraint for fsel. |
| SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, |
| SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; |
| def PPCxsmaxc : SDNode<"PPCISD::XSMAXCDP", SDT_PPCFPMinMax, []>; |
| def PPCxsminc : SDNode<"PPCISD::XSMINCDP", SDT_PPCFPMinMax, []>; |
| def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; |
| def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; |
| def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, |
| [SDNPMayLoad, SDNPMemOperand]>; |
| |
| def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; |
| |
| def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; |
| def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, |
| [SDNPMayLoad]>; |
| def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; |
| def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; |
| def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; |
| def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; |
| def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", |
| SDTypeProfile<1, 3, [ |
| SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; |
| def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; |
| def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; |
| def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; |
| def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; |
| def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", |
| SDTypeProfile<1, 3, [ |
| SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; |
| def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; |
| def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; |
| def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; |
| |
| def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; |
| def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; |
| def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; |
| def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; |
| def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; |
| def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; |
| |
| def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; |
| |
| // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift |
| // amounts. These nodes are generated by the multi-precision shift code. |
| def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; |
| def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; |
| def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; |
| |
| def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; |
| |
| def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; |
| |
| def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", |
| SDTFPUnaryOp, [SDNPHasChain]>; |
| def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", |
| SDTFPUnaryOp, [SDNPHasChain]>; |
| def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", |
| SDTFPUnaryOp, [SDNPHasChain]>; |
| def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", |
| SDTFPUnaryOp, [SDNPHasChain]>; |
| |
| def PPCany_fctidz : PatFrags<(ops node:$op), |
| [(PPCstrict_fctidz node:$op), |
| (PPCfctidz node:$op)]>; |
| def PPCany_fctiwz : PatFrags<(ops node:$op), |
| [(PPCstrict_fctiwz node:$op), |
| (PPCfctiwz node:$op)]>; |
| def PPCany_fctiduz : PatFrags<(ops node:$op), |
| [(PPCstrict_fctiduz node:$op), |
| (PPCfctiduz node:$op)]>; |
| def PPCany_fctiwuz : PatFrags<(ops node:$op), |
| [(PPCstrict_fctiwuz node:$op), |
| (PPCfctiwuz node:$op)]>; |
| |
| // Move 2 i64 values into a VSX register |
| def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", |
| SDTypeProfile<1, 2, |
| [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, |
| SDTCisSameAs<1,2>]>, |
| []>; |
| |
| def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", |
| SDTypeProfile<1, 2, |
| [SDTCisVT<0, f64>, SDTCisVT<1,i32>, |
| SDTCisVT<1,i32>]>, |
| []>; |
| |
| def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", |
| SDTypeProfile<1, 2, |
| [SDTCisVT<0, i32>, SDTCisVT<1, f64>, |
| SDTCisPtrTy<2>]>, |
| []>; |
| |
| // These are target-independent nodes, but have target-specific formats. |
| def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, |
| [SDNPHasChain, SDNPOutGlue]>; |
| def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
| |
| def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; |
| def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
| def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", |
| SDTypeProfile<0, 1, []>, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| |
| // Call nodes for strictfp calls (that define RM). |
| def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", |
| SDTypeProfile<0, 1, []>, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, |
| SDNPVariadic]>; |
| |
| def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, |
| [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; |
| |
| def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, |
| [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; |
| |
| def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", |
| SDTypeProfile<1, 1, [SDTCisInt<0>, |
| SDTCisPtrTy<1>]>, |
| [SDNPHasChain, SDNPSideEffect]>; |
| def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", |
| SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, |
| [SDNPHasChain, SDNPSideEffect]>; |
| |
| def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, |
| [SDNPHasChain, SDNPSideEffect]>; |
| |
| def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, |
| [SDNPHasChain, SDNPSideEffect]>; |
| def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; |
| def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, |
| [SDNPHasChain, SDNPSideEffect]>; |
| |
| def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; |
| def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; |
| |
| def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, |
| [SDNPHasChain, SDNPOptInGlue]>; |
| |
| // PPC-specific atomic operations. |
| def PPCatomicCmpSwap_8 : |
| SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, |
| [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; |
| def PPCatomicCmpSwap_16 : |
| SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, |
| [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; |
| def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, |
| [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; |
| def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, |
| [SDNPHasChain, SDNPMayStore]>; |
| |
| // Instructions to set/unset CR bit 6 for SVR4 vararg calls |
| def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
| def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, |
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
| |
| // Instructions to support dynamic alloca. |
| def SDTDynOp : SDTypeProfile<1, 2, []>; |
| def SDTDynAreaOp : SDTypeProfile<1, 1, []>; |
| def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; |
| def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; |
| def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; |
| |
| // PC Relative Specific Nodes |
| def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; |
| def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", |
| SDTIntUnaryOp, []>; |
| def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", |
| SDTIntUnaryOp, []>; |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC specific transformation functions and pattern fragments. |
| // |
| |
| // A floating point immediate that is not a positive zero and can be converted |
| // to a single precision floating point non-denormal immediate without loss of |
| // information. |
| def nzFPImmAsi32 : PatLeaf<(fpimm), [{ |
| APFloat APFloatOfN = N->getValueAPF(); |
| return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); |
| }]>; |
| |
| // Convert the floating point immediate into a 32 bit floating point immediate |
| // and get a i32 with the resulting bits. |
| def getFPAs32BitInt : SDNodeXForm<fpimm, [{ |
| APFloat APFloatOfN = N->getValueAPF(); |
| convertToNonDenormSingle(APFloatOfN); |
| return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), |
| SDLoc(N), MVT::i32); |
| }]>; |
| |
| // Check if the value can be converted to be single precision immediate, which |
| // can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single |
| // precision before exploiting with XXSPLTI32DX. |
| def nzFPImmAsi64 : PatLeaf<(fpimm), [{ |
| APFloat APFloatOfN = N->getValueAPF(); |
| return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); |
| }]>; |
| |
| // Get the Hi bits of a 64 bit immediate. |
| def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ |
| APFloat APFloatOfN = N->getValueAPF(); |
| bool Unused; |
| APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, |
| &Unused); |
| uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & |
| 0xFFFFFFFF00000000LL) >> 32); |
| return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); |
| }]>; |
| |
| // Get the Lo bits of a 64 bit immediate. |
| def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ |
| APFloat APFloatOfN = N->getValueAPF(); |
| bool Unused; |
| APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, |
| &Unused); |
| uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & |
| 0xFFFFFFFF); |
| return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); |
| }]>; |
| |
| def imm34 : PatLeaf<(imm), [{ |
| return isInt<34>(N->getSExtValue()); |
| }]>; |
| |
| def getImmAs64BitInt : SDNodeXForm<imm, [{ |
| return getI64Imm(N->getSExtValue(), SDLoc(N)); |
| }]>; |
| |
| def SHL32 : SDNodeXForm<imm, [{ |
| // Transformation function: 31 - imm |
| return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); |
| }]>; |
| |
| def SRL32 : SDNodeXForm<imm, [{ |
| // Transformation function: 32 - imm |
| return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) |
| : getI32Imm(0, SDLoc(N)); |
| }]>; |
| |
| def LO16 : SDNodeXForm<imm, [{ |
| // Transformation function: get the low 16 bits. |
| return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); |
| }]>; |
| |
| def HI16 : SDNodeXForm<imm, [{ |
| // Transformation function: shift the immediate value down into the low bits. |
| return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); |
| }]>; |
| |
| def HA16 : SDNodeXForm<imm, [{ |
| // Transformation function: shift the immediate value down into the low bits. |
| long Val = N->getZExtValue(); |
| return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); |
| }]>; |
| def MB : SDNodeXForm<imm, [{ |
| // Transformation function: get the start bit of a mask |
| unsigned mb = 0, me; |
| (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); |
| return getI32Imm(mb, SDLoc(N)); |
| }]>; |
| |
| def ME : SDNodeXForm<imm, [{ |
| // Transformation function: get the end bit of a mask |
| unsigned mb, me = 0; |
| (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); |
| return getI32Imm(me, SDLoc(N)); |
| }]>; |
| def maskimm32 : PatLeaf<(imm), [{ |
| // maskImm predicate - True if immediate is a run of ones. |
| unsigned mb, me; |
| if (N->getValueType(0) == MVT::i32) |
| return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); |
| else |
| return false; |
| }]>; |
| |
| def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ |
| // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit |
| // sign extended field. Used by instructions like 'addi'. |
| return (int32_t)Imm == (short)Imm; |
| }]>; |
| def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ |
| // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit |
| // sign extended field. Used by instructions like 'addi'. |
| return (int64_t)Imm == (short)Imm; |
| }]>; |
| def immZExt16 : PatLeaf<(imm), [{ |
| // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended |
| // field. Used by instructions like 'ori'. |
| return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); |
| }], LO16>; |
| def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ |
| return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); |
| }]>; |
| def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; |
| def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; |
| |
| // imm16Shifted* - These match immediates where the low 16-bits are zero. There |
| // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are |
| // identical in 32-bit mode, but in 64-bit mode, they return true if the |
| // immediate fits into a sign/zero extended 32-bit immediate (with the low bits |
| // clear). |
| def imm16ShiftedZExt : PatLeaf<(imm), [{ |
| // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the |
| // immediate are set. Used by instructions like 'xoris'. |
| return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; |
| }], HI16>; |
| |
| def imm16ShiftedSExt : PatLeaf<(imm), [{ |
| // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the |
| // immediate are set. Used by instructions like 'addis'. Identical to |
| // imm16ShiftedZExt in 32-bit mode. |
| if (N->getZExtValue() & 0xFFFF) return false; |
| if (N->getValueType(0) == MVT::i32) |
| return true; |
| // For 64-bit, make sure it is sext right. |
| return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); |
| }], HI16>; |
| |
| def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ |
| // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit |
| // zero extended field. |
| return isUInt<32>(Imm); |
| }]>; |
| |
| // This is a somewhat weaker condition than actually checking for 4-byte |
| // alignment. It is simply checking that the displacement can be represented |
| // as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form |
| // instructions). |
| // But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require |
| // restricted memrix (4-aligned) constants are alignment sensitive. If these |
| // offsets are hidden behind TOC entries than the values of the lower-order |
| // bits cannot be checked directly. As a result, we need to also incorporate |
| // an alignment check into the relevant patterns. |
| |
| def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; |
| }]>; |
| def DSFormStore : PatFrag<(ops node:$val, node:$ptr), |
| (store node:$val, node:$ptr), [{ |
| return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; |
| }]>; |
| def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ |
| return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; |
| }]>; |
| def DSFormPreStore : PatFrag< |
| (ops node:$val, node:$base, node:$offset), |
| (pre_store node:$val, node:$base, node:$offset), [{ |
| return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; |
| }]>; |
| |
| def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); |
| }]>; |
| def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), |
| (store node:$val, node:$ptr), [{ |
| return cast<StoreSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); |
| }]>; |
| def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ |
| return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); |
| }]>; |
| |
| // This is a somewhat weaker condition than actually checking for 16-byte |
| // alignment. It is simply checking that the displacement can be represented |
| // as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form |
| // instructions). |
| def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| return isOffsetMultipleOf(N, 16); |
| }]>; |
| def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), |
| (store node:$val, node:$ptr), [{ |
| return isOffsetMultipleOf(N, 16); |
| }]>; |
| def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| return !isOffsetMultipleOf(N, 16); |
| }]>; |
| def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), |
| (store node:$val, node:$ptr), [{ |
| return !isOffsetMultipleOf(N, 16); |
| }]>; |
| |
| // PatFrag for binary operation whose operands are both non-constant |
| class BinOpWithoutSImm16Operand<SDNode opcode> : |
| PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ |
| int16_t Imm; |
| return !isIntS16Immediate(N->getOperand(0), Imm) |
| && !isIntS16Immediate(N->getOperand(1), Imm); |
| }]>; |
| |
| def add_without_simm16 : BinOpWithoutSImm16Operand<add>; |
| def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC Flag Definitions. |
| |
| class isPPC64 { bit PPC64 = 1; } |
| class isRecordForm { bit RC = 1; } |
| |
| class RegConstraint<string C> { |
| string Constraints = C; |
| } |
| class NoEncode<string E> { |
| string DisableEncoding = E; |
| } |
| |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC Operand Definitions. |
| |
| // In the default PowerPC assembler syntax, registers are specified simply |
| // by number, so they cannot be distinguished from immediate values (without |
| // looking at the opcode). This means that the default operand matching logic |
| // for the asm parser does not work, and we need to specify custom matchers. |
| // Since those can only be specified with RegisterOperand classes and not |
| // directly on the RegisterClass, all instructions patterns used by the asm |
| // parser need to use a RegisterOperand (instead of a RegisterClass) for |
| // all their register operands. |
| // For this purpose, we define one RegisterOperand for each RegisterClass, |
| // using the same name as the class, just in lower case. |
| |
| def PPCRegGPRCAsmOperand : AsmOperandClass { |
| let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; |
| } |
| def gprc : RegisterOperand<GPRC> { |
| let ParserMatchClass = PPCRegGPRCAsmOperand; |
| } |
| def PPCRegG8RCAsmOperand : AsmOperandClass { |
| let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; |
| } |
| def g8rc : RegisterOperand<G8RC> { |
| let ParserMatchClass = PPCRegG8RCAsmOperand; |
| } |
| def PPCRegG8pRCAsmOperand : AsmOperandClass { |
| let Name = "RegG8pRC"; let PredicateMethod = "isEvenRegNumber"; |
| } |
| def g8prc : RegisterOperand<G8pRC> { |
| let ParserMatchClass = PPCRegG8pRCAsmOperand; |
| } |
| def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { |
| let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; |
| } |
| def gprc_nor0 : RegisterOperand<GPRC_NOR0> { |
| let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; |
| } |
| def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { |
| let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; |
| } |
| def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { |
| let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; |
| } |
| def PPCRegF8RCAsmOperand : AsmOperandClass { |
| let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; |
| } |
| def f8rc : RegisterOperand<F8RC> { |
| let ParserMatchClass = PPCRegF8RCAsmOperand; |
| } |
| def PPCRegF4RCAsmOperand : AsmOperandClass { |
| let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; |
| } |
| def f4rc : RegisterOperand<F4RC> { |
| let ParserMatchClass = PPCRegF4RCAsmOperand; |
| } |
| def PPCRegVRRCAsmOperand : AsmOperandClass { |
| let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; |
| } |
| def vrrc : RegisterOperand<VRRC> { |
| let ParserMatchClass = PPCRegVRRCAsmOperand; |
| } |
| def PPCRegVFRCAsmOperand : AsmOperandClass { |
| let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; |
| } |
| def vfrc : RegisterOperand<VFRC> { |
| let ParserMatchClass = PPCRegVFRCAsmOperand; |
| } |
| def PPCRegCRBITRCAsmOperand : AsmOperandClass { |
| let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; |
| } |
| def crbitrc : RegisterOperand<CRBITRC> { |
| let ParserMatchClass = PPCRegCRBITRCAsmOperand; |
| } |
| def PPCRegCRRCAsmOperand : AsmOperandClass { |
| let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; |
| } |
| def crrc : RegisterOperand<CRRC> { |
| let ParserMatchClass = PPCRegCRRCAsmOperand; |
| } |
| def PPCRegSPERCAsmOperand : AsmOperandClass { |
| let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; |
| } |
| def sperc : RegisterOperand<SPERC> { |
| let ParserMatchClass = PPCRegSPERCAsmOperand; |
| } |
| def PPCRegSPE4RCAsmOperand : AsmOperandClass { |
| let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; |
| } |
| def spe4rc : RegisterOperand<GPRC> { |
| let ParserMatchClass = PPCRegSPE4RCAsmOperand; |
| } |
| |
| def PPCU1ImmAsmOperand : AsmOperandClass { |
| let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u1imm : Operand<i32> { |
| let PrintMethod = "printU1ImmOperand"; |
| let ParserMatchClass = PPCU1ImmAsmOperand; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| |
| def PPCU2ImmAsmOperand : AsmOperandClass { |
| let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u2imm : Operand<i32> { |
| let PrintMethod = "printU2ImmOperand"; |
| let ParserMatchClass = PPCU2ImmAsmOperand; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| |
| def PPCATBitsAsHintAsmOperand : AsmOperandClass { |
| let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; |
| let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. |
| } |
| def atimm : Operand<i32> { |
| let PrintMethod = "printATBitsAsHint"; |
| let ParserMatchClass = PPCATBitsAsHintAsmOperand; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| |
| def PPCU3ImmAsmOperand : AsmOperandClass { |
| let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u3imm : Operand<i32> { |
| let PrintMethod = "printU3ImmOperand"; |
| let ParserMatchClass = PPCU3ImmAsmOperand; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| |
| def PPCU4ImmAsmOperand : AsmOperandClass { |
| let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u4imm : Operand<i32> { |
| let PrintMethod = "printU4ImmOperand"; |
| let ParserMatchClass = PPCU4ImmAsmOperand; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCS5ImmAsmOperand : AsmOperandClass { |
| let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def s5imm : Operand<i32> { |
| let PrintMethod = "printS5ImmOperand"; |
| let ParserMatchClass = PPCS5ImmAsmOperand; |
| let DecoderMethod = "decodeSImmOperand<5>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCU5ImmAsmOperand : AsmOperandClass { |
| let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u5imm : Operand<i32> { |
| let PrintMethod = "printU5ImmOperand"; |
| let ParserMatchClass = PPCU5ImmAsmOperand; |
| let DecoderMethod = "decodeUImmOperand<5>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCU6ImmAsmOperand : AsmOperandClass { |
| let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u6imm : Operand<i32> { |
| let PrintMethod = "printU6ImmOperand"; |
| let ParserMatchClass = PPCU6ImmAsmOperand; |
| let DecoderMethod = "decodeUImmOperand<6>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCU7ImmAsmOperand : AsmOperandClass { |
| let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u7imm : Operand<i32> { |
| let PrintMethod = "printU7ImmOperand"; |
| let ParserMatchClass = PPCU7ImmAsmOperand; |
| let DecoderMethod = "decodeUImmOperand<7>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCU8ImmAsmOperand : AsmOperandClass { |
| let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u8imm : Operand<i32> { |
| let PrintMethod = "printU8ImmOperand"; |
| let ParserMatchClass = PPCU8ImmAsmOperand; |
| let DecoderMethod = "decodeUImmOperand<8>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCU10ImmAsmOperand : AsmOperandClass { |
| let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u10imm : Operand<i32> { |
| let PrintMethod = "printU10ImmOperand"; |
| let ParserMatchClass = PPCU10ImmAsmOperand; |
| let DecoderMethod = "decodeUImmOperand<10>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCU12ImmAsmOperand : AsmOperandClass { |
| let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def u12imm : Operand<i32> { |
| let PrintMethod = "printU12ImmOperand"; |
| let ParserMatchClass = PPCU12ImmAsmOperand; |
| let DecoderMethod = "decodeUImmOperand<12>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCS16ImmAsmOperand : AsmOperandClass { |
| let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; |
| let RenderMethod = "addS16ImmOperands"; |
| } |
| def s16imm : Operand<i32> { |
| let PrintMethod = "printS16ImmOperand"; |
| let EncoderMethod = "getImm16Encoding"; |
| let ParserMatchClass = PPCS16ImmAsmOperand; |
| let DecoderMethod = "decodeSImmOperand<16>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCU16ImmAsmOperand : AsmOperandClass { |
| let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; |
| let RenderMethod = "addU16ImmOperands"; |
| } |
| def u16imm : Operand<i32> { |
| let PrintMethod = "printU16ImmOperand"; |
| let EncoderMethod = "getImm16Encoding"; |
| let ParserMatchClass = PPCU16ImmAsmOperand; |
| let DecoderMethod = "decodeUImmOperand<16>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCS17ImmAsmOperand : AsmOperandClass { |
| let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; |
| let RenderMethod = "addS16ImmOperands"; |
| } |
| def s17imm : Operand<i32> { |
| // This operand type is used for addis/lis to allow the assembler parser |
| // to accept immediates in the range -65536..65535 for compatibility with |
| // the GNU assembler. The operand is treated as 16-bit otherwise. |
| let PrintMethod = "printS16ImmOperand"; |
| let EncoderMethod = "getImm16Encoding"; |
| let ParserMatchClass = PPCS17ImmAsmOperand; |
| let DecoderMethod = "decodeSImmOperand<16>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCS34ImmAsmOperand : AsmOperandClass { |
| let Name = "S34Imm"; |
| let PredicateMethod = "isS34Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def s34imm : Operand<i64> { |
| let PrintMethod = "printS34ImmOperand"; |
| let EncoderMethod = "getImm34EncodingNoPCRel"; |
| let ParserMatchClass = PPCS34ImmAsmOperand; |
| let DecoderMethod = "decodeSImmOperand<34>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def s34imm_pcrel : Operand<i64> { |
| let PrintMethod = "printS34ImmOperand"; |
| let EncoderMethod = "getImm34EncodingPCRel"; |
| let ParserMatchClass = PPCS34ImmAsmOperand; |
| let DecoderMethod = "decodeSImmOperand<34>"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| def PPCImmZeroAsmOperand : AsmOperandClass { |
| let Name = "ImmZero"; |
| let PredicateMethod = "isImmZero"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def immZero : Operand<i32> { |
| let PrintMethod = "printImmZeroOperand"; |
| let ParserMatchClass = PPCImmZeroAsmOperand; |
| let DecoderMethod = "decodeImmZeroOperand"; |
| let OperandType = "OPERAND_IMMEDIATE"; |
| } |
| |
| def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; |
| |
| def PPCDirectBrAsmOperand : AsmOperandClass { |
| let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; |
| let RenderMethod = "addBranchTargetOperands"; |
| } |
| def directbrtarget : Operand<OtherVT> { |
| let PrintMethod = "printBranchOperand"; |
| let EncoderMethod = "getDirectBrEncoding"; |
| let DecoderMethod = "decodeDirectBrTarget"; |
| let ParserMatchClass = PPCDirectBrAsmOperand; |
| let OperandType = "OPERAND_PCREL"; |
| } |
| def absdirectbrtarget : Operand<OtherVT> { |
| let PrintMethod = "printAbsBranchOperand"; |
| let EncoderMethod = "getAbsDirectBrEncoding"; |
| let ParserMatchClass = PPCDirectBrAsmOperand; |
| } |
| def PPCCondBrAsmOperand : AsmOperandClass { |
| let Name = "CondBr"; let PredicateMethod = "isCondBr"; |
| let RenderMethod = "addBranchTargetOperands"; |
| } |
| def condbrtarget : Operand<OtherVT> { |
| let PrintMethod = "printBranchOperand"; |
| let EncoderMethod = "getCondBrEncoding"; |
| let DecoderMethod = "decodeCondBrTarget"; |
| let ParserMatchClass = PPCCondBrAsmOperand; |
| let OperandType = "OPERAND_PCREL"; |
| } |
| def abscondbrtarget : Operand<OtherVT> { |
| let PrintMethod = "printAbsBranchOperand"; |
| let EncoderMethod = "getAbsCondBrEncoding"; |
| let ParserMatchClass = PPCCondBrAsmOperand; |
| } |
| def calltarget : Operand<iPTR> { |
| let PrintMethod = "printBranchOperand"; |
| let EncoderMethod = "getDirectBrEncoding"; |
| let DecoderMethod = "decodeDirectBrTarget"; |
| let ParserMatchClass = PPCDirectBrAsmOperand; |
| let OperandType = "OPERAND_PCREL"; |
| } |
| def abscalltarget : Operand<iPTR> { |
| let PrintMethod = "printAbsBranchOperand"; |
| let EncoderMethod = "getAbsDirectBrEncoding"; |
| let ParserMatchClass = PPCDirectBrAsmOperand; |
| } |
| def PPCCRBitMaskOperand : AsmOperandClass { |
| let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; |
| } |
| def crbitm: Operand<i8> { |
| let PrintMethod = "printcrbitm"; |
| let EncoderMethod = "get_crbitm_encoding"; |
| let DecoderMethod = "decodeCRBitMOperand"; |
| let ParserMatchClass = PPCCRBitMaskOperand; |
| } |
| // Address operands |
| // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). |
| def PPCRegGxRCNoR0Operand : AsmOperandClass { |
| let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; |
| } |
| def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { |
| let ParserMatchClass = PPCRegGxRCNoR0Operand; |
| } |
| |
| // New addressing modes with 34 bit immediates. |
| def PPCDispRI34Operand : AsmOperandClass { |
| let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def dispRI34 : Operand<iPTR> { |
| let ParserMatchClass = PPCDispRI34Operand; |
| } |
| def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value. |
| let PrintMethod = "printMemRegImm34"; |
| let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getMemRI34Encoding"; |
| let DecoderMethod = "decodeMemRI34Operands"; |
| } |
| // memri, imm is a 34-bit value for pc-relative instructions where |
| // base register is set to zero. |
| def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. |
| let PrintMethod = "printMemRegImm34PCRel"; |
| let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); |
| let EncoderMethod = "getMemRI34PCRelEncoding"; |
| let DecoderMethod = "decodeMemRI34PCRelOperands"; |
| } |
| |
| // A version of ptr_rc usable with the asm parser. |
| def PPCRegGxRCOperand : AsmOperandClass { |
| let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; |
| } |
| def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { |
| let ParserMatchClass = PPCRegGxRCOperand; |
| } |
| |
| def PPCDispRIOperand : AsmOperandClass { |
| let Name = "DispRI"; let PredicateMethod = "isS16Imm"; |
| let RenderMethod = "addS16ImmOperands"; |
| } |
| def dispRI : Operand<iPTR> { |
| let ParserMatchClass = PPCDispRIOperand; |
| } |
| def PPCDispRIXOperand : AsmOperandClass { |
| let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def dispRIX : Operand<iPTR> { |
| let ParserMatchClass = PPCDispRIXOperand; |
| } |
| def PPCDispRIHashOperand : AsmOperandClass { |
| let Name = "DispRIHash"; let PredicateMethod = "isHashImmX8"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def dispRIHash : Operand<iPTR> { |
| let ParserMatchClass = PPCDispRIHashOperand; |
| } |
| def PPCDispRIX16Operand : AsmOperandClass { |
| let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def dispRIX16 : Operand<iPTR> { |
| let ParserMatchClass = PPCDispRIX16Operand; |
| } |
| def PPCDispSPE8Operand : AsmOperandClass { |
| let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def dispSPE8 : Operand<iPTR> { |
| let ParserMatchClass = PPCDispSPE8Operand; |
| } |
| def PPCDispSPE4Operand : AsmOperandClass { |
| let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def dispSPE4 : Operand<iPTR> { |
| let ParserMatchClass = PPCDispSPE4Operand; |
| } |
| def PPCDispSPE2Operand : AsmOperandClass { |
| let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; |
| let RenderMethod = "addImmOperands"; |
| } |
| def dispSPE2 : Operand<iPTR> { |
| let ParserMatchClass = PPCDispSPE2Operand; |
| } |
| |
| def memri : Operand<iPTR> { |
| let PrintMethod = "printMemRegImm"; |
| let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getMemRIEncoding"; |
| let DecoderMethod = "decodeMemRIOperands"; |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def memrr : Operand<iPTR> { |
| let PrintMethod = "printMemRegReg"; |
| let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. |
| let PrintMethod = "printMemRegImm"; |
| let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getMemRIXEncoding"; |
| let DecoderMethod = "decodeMemRIXOperands"; |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def memrihash : Operand<iPTR> { |
| // memrihash 8-aligned for ROP Protection Instructions. |
| let PrintMethod = "printMemRegImmHash"; |
| let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getMemRIHashEncoding"; |
| let DecoderMethod = "decodeMemRIHashOperands"; |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} |
| let PrintMethod = "printMemRegImm"; |
| let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getMemRIX16Encoding"; |
| let DecoderMethod = "decodeMemRIX16Operands"; |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. |
| let PrintMethod = "printMemRegImm"; |
| let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getSPE8DisEncoding"; |
| let DecoderMethod = "decodeSPE8Operands"; |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. |
| let PrintMethod = "printMemRegImm"; |
| let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getSPE4DisEncoding"; |
| let DecoderMethod = "decodeSPE4Operands"; |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. |
| let PrintMethod = "printMemRegImm"; |
| let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); |
| let EncoderMethod = "getSPE2DisEncoding"; |
| let DecoderMethod = "decodeSPE2Operands"; |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| |
| // A single-register address. This is used with the SjLj |
| // pseudo-instructions which translates to LD/LWZ. These instructions requires |
| // G8RC_NOX0 registers. |
| def memr : Operand<iPTR> { |
| let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); |
| let OperandType = "OPERAND_MEMORY"; |
| } |
| def PPCTLSRegOperand : AsmOperandClass { |
| let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; |
| let RenderMethod = "addTLSRegOperands"; |
| } |
| def tlsreg32 : Operand<i32> { |
| let EncoderMethod = "getTLSRegEncoding"; |
| let ParserMatchClass = PPCTLSRegOperand; |
| } |
| def tlsgd32 : Operand<i32> {} |
| def tlscall32 : Operand<i32> { |
| let PrintMethod = "printTLSCall"; |
| let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); |
| let EncoderMethod = "getTLSCallEncoding"; |
| } |
| |
| // PowerPC Predicate operand. |
| def pred : Operand<OtherVT> { |
| let PrintMethod = "printPredicateOperand"; |
| let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); |
| } |
| |
| // Define PowerPC specific addressing mode. |
| |
| // d-form |
| def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" |
| // ds-form |
| def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" |
| // dq-form |
| def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" |
| // 8LS:d-form |
| def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" |
| |
| // Below forms are all x-form addressing mode, use three different ones so we |
| // can make a accurate check for x-form instructions in ISEL. |
| // x-form addressing mode whose associated displacement form is D. |
| def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" |
| // x-form addressing mode whose associated displacement form is DS. |
| def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" |
| // x-form addressing mode whose associated displacement form is DQ. |
| def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" |
| |
| def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; |
| |
| // The address in a single register. This is used with the SjLj |
| // pseudo-instructions. |
| def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; |
| |
| /// This is just the offset part of iaddr, used for preinc. |
| def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; |
| |
| // Load and Store Instruction Selection addressing modes. |
| def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; |
| def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; |
| def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; |
| def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; |
| def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; |
| def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>; |
| def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>; |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC Instruction Predicate Definitions. |
| def In32BitMode : Predicate<"!Subtarget->isPPC64()">; |
| def In64BitMode : Predicate<"Subtarget->isPPC64()">; |
| def IsBookE : Predicate<"Subtarget->isBookE()">; |
| def IsNotBookE : Predicate<"!Subtarget->isBookE()">; |
| def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; |
| def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; |
| def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; |
| def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; |
| def IsE500 : Predicate<"Subtarget->isE500()">; |
| def HasSPE : Predicate<"Subtarget->hasSPE()">; |
| def HasICBT : Predicate<"Subtarget->hasICBT()">; |
| def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; |
| def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; |
| def NoNaNsFPMath |
| : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; |
| def NaNsFPMath |
| : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; |
| def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; |
| def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; |
| def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; |
| def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; |
| def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; |
| def HasFPU : Predicate<"Subtarget->hasFPU()">; |
| def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; |
| def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; |
| |
| // AIX assembler may not be modern enough to support some extended mne. |
| def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, |
| AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; |
| def IsAIX : Predicate<"Subtarget->isAIXABI()">; |
| def NotAIX : Predicate<"!Subtarget->isAIXABI()">; |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC Multiclass Definitions. |
| |
| multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XForm_6<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : XForm_6<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| let Defs = [CARRY] in |
| def NAME : XForm_6<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CARRY, CR0] in |
| def _rec : XForm_6<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| let Defs = [CARRY] in |
| def NAME : XForm_10<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CARRY, CR0] in |
| def _rec : XForm_10<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XForm_11<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : XForm_11<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| // Multiclass for instructions which have a record overflow form as well |
| // as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) |
| multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| let BaseName = !strconcat(asmbase, "O") in { |
| let Defs = [XER] in |
| def O : XOForm_1<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o ", asmstr)), itin, |
| []>, RecFormRel; |
| let Defs = [XER, CR0] in |
| def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| // Multiclass for instructions for which the non record form is not cracked |
| // and the record form is cracked (i.e. divw, mullw, etc.) |
| multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel, PPC970_DGroup_First, |
| PPC970_DGroup_Cracked; |
| } |
| let BaseName = !strconcat(asmbase, "O") in { |
| let Defs = [XER] in |
| def O : XOForm_1<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o ", asmstr)), itin, |
| []>, RecFormRel; |
| let Defs = [XER, CR0] in |
| def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| let Defs = [CARRY] in |
| def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CARRY, CR0] in |
| def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| let BaseName = !strconcat(asmbase, "O") in { |
| let Defs = [CARRY, XER] in |
| def O : XOForm_1<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o ", asmstr)), itin, |
| []>, RecFormRel; |
| let Defs = [CARRY, XER, CR0] in |
| def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| let BaseName = !strconcat(asmbase, "O") in { |
| let Defs = [XER] in |
| def O : XOForm_3<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o ", asmstr)), itin, |
| []>, RecFormRel; |
| let Defs = [XER, CR0] in |
| def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| let Defs = [CARRY] in |
| def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CARRY, CR0] in |
| def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| let BaseName = !strconcat(asmbase, "O") in { |
| let Defs = [CARRY, XER] in |
| def O : XOForm_3<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o ", asmstr)), itin, |
| []>, RecFormRel; |
| let Defs = [CARRY, XER, CR0] in |
| def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, |
| !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : MForm_2<opcode, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : MForm_2<opcode, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : MDForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : MDForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : MDSForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : MDSForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| let Defs = [CARRY] in |
| def NAME : XSForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CARRY, CR0] in |
| def _rec : XSForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XSForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR0] in |
| def _rec : XSForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XForm_26<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR1] in |
| def _rec : XForm_26<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : XForm_28<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR1] in |
| def _rec : XForm_28<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : AForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR1] in |
| def _rec : AForm_1<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : AForm_2<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR1] in |
| def _rec : AForm_2<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, |
| string asmbase, string asmstr, InstrItinClass itin, |
| list<dag> pattern> { |
| let BaseName = asmbase in { |
| def NAME : AForm_3<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(" ", asmstr)), itin, |
| pattern>, RecFormRel; |
| let Defs = [CR1] in |
| def _rec : AForm_3<opcode, xo, OOL, IOL, |
| !strconcat(asmbase, !strconcat(". ", asmstr)), itin, |
| []>, isRecordForm, RecFormRel; |
| } |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // PowerPC Instruction Definitions. |
| |
| // Pseudo instructions: |
| |
| let hasCtrlDep = 1 in { |
| let Defs = [R1], Uses = [R1] in { |
| def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), |
| "#ADJCALLSTACKDOWN $amt1 $amt2", |
| [(callseq_start timm:$amt1, timm:$amt2)]>; |
| def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), |
| "#ADJCALLSTACKUP $amt1 $amt2", |
| [(callseq_end timm:$amt1, timm:$amt2)]>; |
| } |
| } // hasCtrlDep |
| |
| let Defs = [R1], Uses = [R1] in |
| def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", |
| [(set i32:$result, |
| (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; |
| def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", |
| [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; |
| // Probed alloca to support stack clash protection. |
| let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { |
| def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), |
| (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", |
| [(set i32:$result, |
| (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; |
| def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs |
| gprc:$fp, gprc:$actual_negsize), |
| (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; |
| def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs |
| gprc:$fp, gprc:$actual_negsize), |
| (ins gprc:$negsize, memri:$fpsi), |
| "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, |
| RegConstraint<"$actual_negsize = $negsize">; |
| def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), |
| (ins i64imm:$stacksize), |
| "#PROBED_STACKALLOC_32", []>; |
| } |
| |
| // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after |
| // instruction selection into a branch sequence. |
| let PPC970_Single = 1 in { |
| // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes |
| // because either operand might become the first operand in an isel, and |
| // that operand cannot be r0. |
| def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, |
| gprc_nor0:$T, gprc_nor0:$F, |
| i32imm:$BROPC), "#SELECT_CC_I4", |
| []>; |
| def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, |
| g8rc_nox0:$T, g8rc_nox0:$F, |
| i32imm:$BROPC), "#SELECT_CC_I8", |
| []>; |
| def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, |
| i32imm:$BROPC), "#SELECT_CC_F4", |
| []>; |
| def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, |
| i32imm:$BROPC), "#SELECT_CC_F8", |
| []>; |
| def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, |
| i32imm:$BROPC), "#SELECT_CC_F16", |
| []>; |
| def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, |
| i32imm:$BROPC), "#SELECT_CC_VRRC", |
| []>; |
| |
| // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition |
| // register bit directly. |
| def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, |
| gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", |
| [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; |
| def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, |
| g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", |
| [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; |
| let Predicates = [HasFPU] in { |
| def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, |
| f4rc:$T, f4rc:$F), "#SELECT_F4", |
| [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; |
| def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, |
| f8rc:$T, f8rc:$F), "#SELECT_F8", |
| [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; |
| def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, |
| vrrc:$T, vrrc:$F), "#SELECT_F16", |
| [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; |
| } |
| def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, |
| vrrc:$T, vrrc:$F), "#SELECT_VRRC", |
| [(set v4i32:$dst, |
| (select i1:$cond, v4i32:$T, v4i32:$F))]>; |
| } |
| |
| // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to |
| // scavenge a register for it. |
| let mayStore = 1 in { |
| def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), |
| "#SPILL_CR", []>; |
| def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), |
| "#SPILL_CRBIT", []>; |
| } |
| |
| // RESTORE_CR - Indicate that we're restoring the CR register (previously |
| // spilled), so we'll need to scavenge a register for it. |
| let mayLoad = 1 in { |
| def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), |
| "#RESTORE_CR", []>; |
| def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), |
| "#RESTORE_CRBIT", []>; |
| } |
| |
| let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { |
| let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in |
| def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, |
| [(retflag)]>, Requires<[In32BitMode]>; |
| let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { |
| let isPredicable = 1 in |
| def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, |
| []>; |
| |
| let isCodeGenOnly = 1 in { |
| def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), |
| "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, |
| []>; |
| |
| def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), |
| "bcctr 12, $bi, 0", IIC_BrB, []>; |
| def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), |
| "bcctr 4, $bi, 0", IIC_BrB, []>; |
| } |
| } |
| } |
| |
| // Set the float rounding mode. |
| let Uses = [RM], Defs = [RM] in { |
| def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), |
| "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; |
| |
| def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), |
| "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; |
| |
| def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), |
| "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; |
| } |
| |
| let Defs = [LR] in |
| def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, |
| PPC970_Unit_BRU; |
| let Defs = [LR] in |
| def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, |
| PPC970_Unit_BRU; |
| |
| let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, |
| hasSideEffects = 0 in { |
| let isBarrier = 1 in { |
| let isPredicable = 1 in |
| def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), |
| "b $dst", IIC_BrB, |
| [(br bb:$dst)]>; |
| def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), |
| "ba $dst", IIC_BrB, []>; |
| } |
| |
| // BCC represents an arbitrary conditional branch on a predicate. |
| // FIXME: should be able to write a pattern for PPCcondbranch, but can't use |
| // a two-value operand where a dag node expects two operands. :( |
| let isCodeGenOnly = 1 in { |
| class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), |
| "b${cond:cc}${cond:pm} ${cond:reg}, $dst" |
| /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; |
| def BCC : BCC_class; |
| |
| // The same as BCC, except that it's not a terminator. Used for introducing |
| // control flow dependency without creating new blocks. |
| let isTerminator = 0 in def CTRL_DEP : BCC_class; |
| |
| def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), |
| "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; |
| |
| let isReturn = 1, Uses = [LR, RM] in |
| def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), |
| "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; |
| } |
| |
| let isCodeGenOnly = 1 in { |
| let Pattern = [(brcond i1:$bi, bb:$dst)] in |
| def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), |
| "bc 12, $bi, $dst">; |
| |
| let Pattern = [(brcond (not i1:$bi), bb:$dst)] in |
| def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), |
| "bc 4, $bi, $dst">; |
| |
| let isReturn = 1, Uses = [LR, RM] in { |
| def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), |
| "bclr 12, $bi, 0", IIC_BrB, []>; |
| def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), |
| "bclr 4, $bi, 0", IIC_BrB, []>; |
| } |
| } |
| |
| let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { |
| def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), |
| "bdzlr", IIC_BrB, []>; |
| def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), |
| "bdnzlr", IIC_BrB, []>; |
| def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), |
| "bdzlr+", IIC_BrB, []>; |
| def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), |
| "bdnzlr+", IIC_BrB, []>; |
| def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), |
| "bdzlr-", IIC_BrB, []>; |
| def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), |
| "bdnzlr-", IIC_BrB, []>; |
| } |
| |
| let Defs = [CTR], Uses = [CTR] in { |
| def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), |
| "bdz $dst">; |
| def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), |
| "bdnz $dst">; |
| def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), |
| "bdza $dst">; |
| def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), |
| "bdnza $dst">; |
| def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), |
| "bdz+ $dst">; |
| def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), |
| "bdnz+ $dst">; |
| def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), |
| "bdza+ $dst">; |
| def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), |
| "bdnza+ $dst">; |
| def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), |
| "bdz- $dst">; |
| def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), |
| "bdnz- $dst">; |
| def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), |
| "bdza- $dst">; |
| def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), |
| "bdnza- $dst">; |
| } |
| } |
| |
| // The unconditional BCL used by the SjLj setjmp code. |
| let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, |
| hasSideEffects = 0 in { |
| let Defs = [LR], Uses = [RM] in { |
| def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), |
| "bcl 20, 31, $dst">; |
| } |
| } |
| |
| let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { |
| // Convenient aliases for call instructions |
| let Uses = [RM] in { |
| def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), |
| "bl $func", IIC_BrB, []>; // See Pat patterns below. |
| def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), |
| "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; |
| |
| let isCodeGenOnly = 1 in { |
| def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), |
| "bl $func", IIC_BrB, []>; |
| def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), |
| "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; |
| def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), |
| "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; |
| |
| def BCL : BForm_4<16, 12, 0, 1, (outs), |
| (ins crbitrc:$bi, condbrtarget:$dst), |
| "bcl 12, $bi, $dst">; |
| def BCLn : BForm_4<16, 4, 0, 1, (outs), |
| (ins crbitrc:$bi, condbrtarget:$dst), |
| "bcl 4, $bi, $dst">; |
| def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, |
| (outs), (ins calltarget:$func), |
| "bl $func\n\tnop", IIC_BrB, []>; |
| } |
| } |
| let Uses = [CTR, RM] in { |
| let isPredicable = 1 in |
| def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), |
| "bctrl", IIC_BrB, [(PPCbctrl)]>, |
| Requires<[In32BitMode]>; |
| |
| let isCodeGenOnly = 1 in { |
| def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), |
| "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, |
| []>; |
| |
| def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), |
| "bcctrl 12, $bi, 0", IIC_BrB, []>; |
| def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), |
| "bcctrl 4, $bi, 0", IIC_BrB, []>; |
| } |
| } |
| let Uses = [LR, RM] in { |
| def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), |
| "blrl", IIC_BrB, []>; |
| |
| let isCodeGenOnly = 1 in { |
| def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), |
| "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, |
| []>; |
| |
| def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), |
| "bclrl 12, $bi, 0", IIC_BrB, []>; |
| def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), |
| "bclrl 4, $bi, 0", IIC_BrB, []>; |
| } |
| } |
| let Defs = [CTR], Uses = [CTR, RM] in { |
| def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), |
| "bdzl $dst">; |
| def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), |
| "bdnzl $dst">; |
| def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), |
| "bdzla $dst">; |
| def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), |
| "bdnzla $dst">; |
| def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), |
| "bdzl+ $dst">; |
| def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), |
| "bdnzl+ $dst">; |
| def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), |
| "bdzla+ $dst">; |
| def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), |
| "bdnzla+ $dst">; |
| def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), |
| "bdzl- $dst">; |
| def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), |
| "bdnzl- $dst">; |
| def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), |
| "bdzla- $dst">; |
| def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), |
| "bdnzla- $dst">; |
| } |
| let Defs = [CTR], Uses = [CTR, LR, RM] in { |
| def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), |
| "bdzlrl", IIC_BrB, []>; |
| def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), |
| "bdnzlrl", IIC_BrB, []>; |
| def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), |
| "bdzlrl+", IIC_BrB, []>; |
| def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), |
| "bdnzlrl+", IIC_BrB, []>; |
| def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), |
| "bdzlrl-", IIC_BrB, []>; |
| def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), |
| "bdnzlrl-", IIC_BrB, []>; |
| } |
| } |
| |
| let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { |
| // Convenient aliases for call instructions |
| let Uses = [RM] in { |
| def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), |
| "bl $func", IIC_BrB, []>; // See Pat patterns below. |
| def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), |
| "bla $func", IIC_BrB, [(PPCcall_rm (i32 imm:$func))]>; |
| |
| def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, |
| (outs), (ins calltarget:$func), |
| "bl $func\n\tnop", IIC_BrB, []>; |
| } |
| let Uses = [CTR, RM] in { |
| let isPredicable = 1 in |
| def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), |
| "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, |
| Requires<[In32BitMode]>; |
| } |
| } |
| |
| let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in |
| def TCRETURNdi :PPCEmitTimePseudo< (outs), |
| (ins calltarget:$dst, i32imm:$offset), |
| "#TC_RETURNd $dst $offset", |
| []>; |
| |
| |
| let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in |
| def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), |
| "#TC_RETURNa $func $offset", |
| [(PPCtc_return (i32 imm:$func), imm:$offset)]>; |
| |
| let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in |
| def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), |
| "#TC_RETURNr $dst $offset", |
| []>; |
| |
| let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, |
| Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { |
| def BCTRL_LWZinto_toc: |
| XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), |
| (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, |
| [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; |
| |
| } |
| |
| let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, |
| Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { |
| def BCTRL_LWZinto_toc_RM: |
| XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), |
| (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, |
| [(PPCbctrl_load_toc_rm iaddr:$src)]>, Requires<[In32BitMode]>; |
| |
| } |
| |
| let isCodeGenOnly = 1, hasSideEffects = 0 in { |
| |
| let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, |
| isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in |
| def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, |
| []>, Requires<[In32BitMode]>; |
| |
| let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, |
| isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in |
| def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), |
| "b $dst", IIC_BrB, |
| []>; |
| |
| let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, |
| isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in |
| def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), |
| "ba $dst", IIC_BrB, |
| []>; |
| |
| } |
| |
| // While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp |
| // is not. |
| let hasSideEffects = 1 in { |
| let Defs = [CTR] in |
| def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), |
| "#EH_SJLJ_SETJMP32", |
| [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, |
| Requires<[In32BitMode]>; |
| } |
| |
| let hasSideEffects = 1, isBarrier = 1 in { |
| let isTerminator = 1 in |
| def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), |
| "#EH_SJLJ_LONGJMP32", |
| [(PPCeh_sjlj_longjmp addr:$buf)]>, |
| Requires<[In32BitMode]>; |
| } |
| |
| // This pseudo is never removed from the function, as it serves as |
| // a terminator. Size is set to 0 to prevent the builtin assembler |
| // from emitting it. |
| let isBranch = 1, isTerminator = 1, Size = 0 in { |
| def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), |
| "#EH_SjLj_Setup\t$dst", []>; |
| } |
| |
| // System call. |
| let PPC970_Unit = 7 in { |
| def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), |
| "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; |
| } |
| |
| // Branch history rolling buffer. |
| def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, |
| [(PPCclrbhrb)]>, |
| PPC970_DGroup_Single; |
| // The $dmy argument used for MFBHRBE is not needed; however, including |
| // it avoids automatic generation of PPCFastISel::fastEmit_i(), which |
| // interferes with necessary special handling (see PPCFastISel.cpp). |
| def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), |
| (ins u10imm:$imm, u10imm:$dmy), |
| "mfbhrbe $rD, $imm", IIC_BrB, |
| [(set i32:$rD, |
| (PPCmfbhrbe imm:$imm, imm:$dmy))]>, |
| PPC970_DGroup_First; |
| |
| def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", |
| IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, |
| PPC970_DGroup_Single; |
| |
| def : InstAlias<"rfebb", (RFEBB 1)>; |
| |
| // DCB* instructions. |
| def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", |
| IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, |
| PPC970_DGroup_Single; |
| def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", |
| IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, |
| PPC970_DGroup_Single; |
| def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", |
| IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, |
| PPC970_DGroup_Single; |
| def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", |
| IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, |
| PPC970_DGroup_Single; |
| def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", |
| IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, |
| PPC970_DGroup_Single; |
| |
| def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst), |
| "dcbf $dst, $TH", IIC_LdStDCBF, []>, |
| PPC970_DGroup_Single; |
| |
| let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { |
| def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), |
| "dcbt $dst, $TH", IIC_LdStDCBF, []>, |
| PPC970_DGroup_Single; |
| def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), |
| "dcbtst $dst, $TH", IIC_LdStDCBF, []>, |
| PPC970_DGroup_Single; |
| } // hasSideEffects = 0 |
| |
| def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), |
| "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; |
| def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), |
| "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; |
| def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), |
| "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; |
| def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), |
| "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; |
| |
| def : Pat<(int_ppc_dcbt xoaddr:$dst), |
| (DCBT 0, xoaddr:$dst)>; |
| def : Pat<(int_ppc_dcbtst xoaddr:$dst), |
| (DCBTST 0, xoaddr:$dst)>; |
| def : Pat<(int_ppc_dcbf xoaddr:$dst), |
| (DCBF 0, xoaddr:$dst)>; |
| def : Pat<(int_ppc_icbt xoaddr:$dst), |
| (ICBT 0, xoaddr:$dst)>; |
| |
| def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), |
| (DCBT 0, xoaddr:$dst)>; // data prefetch for loads |
| def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), |
| (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores |
| def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), |
| (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) |
| |
| def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), |
| (DCBT i32:$TH, xoaddr:$dst)>; |
| def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), |
| (DCBTST i32:$TH, xoaddr:$dst)>; |
| |
| // Atomic operations |
| // FIXME: some of these might be used with constant operands. This will result |
| // in constant materialization instructions that may be redundant. We currently |
| // clean this up in PPCMIPeephole with calls to |
| // PPCInstrInfo::convertToImmediateForm() but we should probably not emit them |
| // in the first place. |
| let Defs = [CR0] in { |
| def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", |
| [(set i32:$dst, (atomic_load_add_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", |
| [(set i32:$dst, (atomic_load_sub_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", |
| [(set i32:$dst, (atomic_load_and_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", |
| [(set i32:$dst, (atomic_load_or_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", |
| [(set i32:$dst, (atomic_load_xor_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", |
| [(set i32:$dst, (atomic_load_nand_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", |
| [(set i32:$dst, (atomic_load_min_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", |
| [(set i32:$dst, (atomic_load_max_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", |
| [(set i32:$dst, (atomic_load_umin_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", |
| [(set i32:$dst, (atomic_load_umax_8 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", |
| [(set i32:$dst, (atomic_load_add_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", |
| [(set i32:$dst, (atomic_load_sub_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", |
| [(set i32:$dst, (atomic_load_and_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", |
| [(set i32:$dst, (atomic_load_or_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", |
| [(set i32:$dst, (atomic_load_xor_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", |
| [(set i32:$dst, (atomic_load_nand_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", |
| [(set i32:$dst, (atomic_load_min_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", |
| [(set i32:$dst, (atomic_load_max_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", |
| [(set i32:$dst, (atomic_load_umin_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", |
| [(set i32:$dst, (atomic_load_umax_16 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", |
| [(set i32:$dst, (atomic_load_add_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", |
| [(set i32:$dst, (atomic_load_sub_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", |
| [(set i32:$dst, (atomic_load_and_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", |
| [(set i32:$dst, (atomic_load_or_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", |
| [(set i32:$dst, (atomic_load_xor_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", |
| [(set i32:$dst, (atomic_load_nand_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", |
| [(set i32:$dst, (atomic_load_min_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", |
| [(set i32:$dst, (atomic_load_max_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", |
| [(set i32:$dst, (atomic_load_umin_32 ForceXForm:$ptr, i32:$incr))]>; |
| def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", |
| [(set i32:$dst, (atomic_load_umax_32 ForceXForm:$ptr, i32:$incr))]>; |
| |
| def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", |
| [(set i32:$dst, (atomic_cmp_swap_8 ForceXForm:$ptr, i32:$old, i32:$new))]>; |
| def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", |
| [(set i32:$dst, (atomic_cmp_swap_16 ForceXForm:$ptr, i32:$old, i32:$new))]>; |
| def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", |
| [(set i32:$dst, (atomic_cmp_swap_32 ForceXForm:$ptr, i32:$old, i32:$new))]>; |
| |
| def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", |
| [(set i32:$dst, (atomic_swap_8 ForceXForm:$ptr, i32:$new))]>; |
| def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", |
| [(set i32:$dst, (atomic_swap_16 ForceXForm:$ptr, i32:$new))]>; |
| def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< |
| (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", |
| [(set i32:$dst, (atomic_swap_32 ForceXForm:$ptr, i32:$new))]>; |
| } |
| |
| def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), |
| (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; |
| def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), |
| (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; |
| |
| // Instructions to support atomic operations |
| let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { |
| def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), |
| "lbarx $rD, $src", IIC_LdStLWARX, []>, |
| Requires<[HasPartwordAtomics]>; |
| |
| def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), |
| "lharx $rD, $src", IIC_LdStLWARX, []>, |
| Requires<[HasPartwordAtomics]>; |
| |
| def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), |
| "lwarx $rD, $src", IIC_LdStLWARX, []>; |
| |
| // Instructions to support lock versions of atomics |
| // (EH=1 - see Power ISA 2.07 Book II 4.4.2) |
| def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), |
| "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, |
| Requires<[HasPartwordAtomics]>; |
| |
| def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), |
| "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, |
| Requires<[HasPartwordAtomics]>; |
| |
|
