| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s |
| |
| --- |
| name: interp_p1_ss |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| ; CHECK-LABEL: name: interp_p1_ss |
| ; CHECK: liveins: $sgpr0, $sgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), [[COPY2]](s32), 1, 1, [[COPY1]](s32) |
| %0:_(s32) = COPY $sgpr0 |
| %1:_(s32) = COPY $sgpr1 |
| %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), %0, 1, 1, %1 |
| ... |
| |
| --- |
| name: interp_p1_vs |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $sgpr0 |
| ; CHECK-LABEL: name: interp_p1_vs |
| ; CHECK: liveins: $vgpr0, $sgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), [[COPY]](s32), 1, 1, [[COPY1]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $sgpr0 |
| %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), %0, 1, 1, %1 |
| ... |
| |
| --- |
| name: interp_p1_sv |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $vgpr0 |
| ; CHECK-LABEL: name: interp_p1_sv |
| ; CHECK: liveins: $sgpr0, $vgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), [[COPY2]](s32), 1, 1, [[V_READFIRSTLANE_B32_]](s32) |
| %0:_(s32) = COPY $sgpr0 |
| %1:_(s32) = COPY $vgpr0 |
| %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), %0, 1, 1, %1 |
| ... |
| |
| --- |
| name: interp_p1_vv |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| ; CHECK-LABEL: name: interp_p1_vv |
| ; CHECK: liveins: $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1 |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), [[COPY]](s32), 1, 1, [[V_READFIRSTLANE_B32_]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1), %0, 1, 1, %1 |
| ... |