llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s

---
name: atomicrmw_and_global_i32

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomicrmw_and_global_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 1)
...

---
name: atomicrmw_and_local_i32

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: atomicrmw_and_local_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    %0:_(p3) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 3)
...

---
name: atomicrmw_and_global_i64

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomicrmw_and_global_i64
    ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 1)
...

---
name: atomicrmw_and_local_i64

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: atomicrmw_and_local_i64
    ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    %0:_(p3) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst (s32), addrspace 3)
...