| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s |
| # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s |
| |
| # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s |
| |
| # SI-ERR-NOT: remark |
| # SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv) |
| # SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs) |
| # SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv) |
| # SI-ERR-NOT: remark |
| |
| --- |
| name: class_s16_vcc_sv |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $vgpr0 |
| ; WAVE32-LABEL: name: class_s16_vcc_sv |
| ; WAVE32: liveins: $sgpr0, $vgpr0 |
| ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec |
| ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] |
| ; WAVE64-LABEL: name: class_s16_vcc_sv |
| ; WAVE64: liveins: $sgpr0, $vgpr0 |
| ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec |
| ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:vgpr(s32) = COPY $vgpr0 |
| %2:sgpr(s16) = G_TRUNC %0 |
| %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: class_s16_vcc_vs |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $vgpr0 |
| ; WAVE32-LABEL: name: class_s16_vcc_vs |
| ; WAVE32: liveins: $sgpr0, $vgpr0 |
| ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec |
| ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] |
| ; WAVE64-LABEL: name: class_s16_vcc_vs |
| ; WAVE64: liveins: $sgpr0, $vgpr0 |
| ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec |
| ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr(s32) = COPY $sgpr0 |
| %2:vgpr(s16) = G_TRUNC %0 |
| %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: class_s16_vcc_vv |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| ; WAVE32-LABEL: name: class_s16_vcc_vv |
| ; WAVE32: liveins: $vgpr0, $vgpr1 |
| ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec |
| ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] |
| ; WAVE64-LABEL: name: class_s16_vcc_vv |
| ; WAVE64: liveins: $vgpr0, $vgpr1 |
| ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec |
| ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:vgpr(s32) = COPY $vgpr1 |
| %2:vgpr(s16) = G_TRUNC %0 |
| %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1 |
| S_ENDPGM 0, implicit %4 |
| ... |