[AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering (#224080) When SCC is live into a scalar frame index user, the scaling path avoids SALU ops that write SCC by computing the address in a VGPR and reading it back with V_READFIRSTLANE_B32. If the destination of that readfirstlane is scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead, scavenge that register with AllowSpill=false. --- <sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
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This repository contains the source code for LLVM, a toolkit for the construction of highly optimized compilers, optimizers, and run-time environments.
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